[PATCH v2 0/4] arm64: dts: imx8qm: collect some small update and fixes

[PATCH v2 0/4] arm64: dts: imx8qm: collect some small update and fixes

[Frank.Li]

Collect some small update and fixes.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
Changes in v2:
- remove two sashiko found issue
  1. remove power-domain-names
  2. remove mu6
- Link to v1: https://patch.msgid.link/20260706-qm_dts-v1-0-14117a48fbdb@nxp.com

---
Frank Li (4):
      arm64: dts: imx8qm-ss-dma: add lpuart4 node
      arm64: dts: imx8qm-ss-audio: add spdif1 node
      arm64: dts: imx8qm-ss-lsio: add lsio mu8 and mu8b
      arm64: dts: imx8-ss-audio: Fix LPCG clock indices for ASRC0

 arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi   |  8 ++---
 arch/arm64/boot/dts/freescale/imx8qm-ss-audio.dtsi | 38 ++++++++++++++++++++++
 arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi   | 15 +++++++++
 arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi  | 21 ++++++++++++
 4 files changed, 78 insertions(+), 4 deletions(-)
---
base-commit: 31bd73273b9bf03a3fe32227b417f00d4a94c6ac
change-id: 20260706-qm_dts-043646b4675b

Best regards,
--  
Frank Li <Frank.Li@nxp.com>

[PATCH v2 1/4] arm64: dts: imx8qm-ss-dma: add lpuart4 node

[Frank.Li]

From: Frank Li <Frank.Li@nxp.com>

Add lpuart4 node for imx8qm.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
change in v4
- remove power-domain-names, found by sashiko
---
 arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi
index 974e193f8dcb9..738c6f05c4ea6 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi
@@ -8,6 +8,21 @@
 /delete-node/ &adma_pwm_lpcg;
 
 &dma_subsys {
+	lpuart4: serial@5a0a0000 {
+		compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
+		reg = <0x5a0a0000 0x1000>;
+		interrupts = <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&gic>;
+		clocks = <&uart4_lpcg IMX_LPCG_CLK_4>, <&uart4_lpcg IMX_LPCG_CLK_0>;
+		clock-names = "ipg", "baud";
+		assigned-clocks = <&clk IMX_SC_R_UART_4 IMX_SC_PM_CLK_PER>;
+		assigned-clock-rates = <80000000>;
+		power-domains = <&pd IMX_SC_R_UART_4>;
+		dmas = <&edma2 20 0 FSL_EDMA_RX>, <&edma2 21 0 0>;
+		dma-names = "rx","tx";
+		status = "disabled";
+	};
+
 	uart4_lpcg: clock-controller@5a4a0000 {
 		compatible = "fsl,imx8qxp-lpcg";
 		reg = <0x5a4a0000 0x10000>;

-- 
2.43.0

[PATCH v2 2/4] arm64: dts: imx8qm-ss-audio: add spdif1 node

[Frank.Li]

From: Frank Li <Frank.Li@nxp.com>

Add spdif1 and related lpcg node for imx8qm.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8qm-ss-audio.dtsi | 38 ++++++++++++++++++++++
 1 file changed, 38 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-audio.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-audio.dtsi
index 7c5386d4ab2b7..5cb644837d936 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm-ss-audio.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-audio.dtsi
@@ -74,6 +74,31 @@ &asrc1_lpcg {
 };
 
 &audio_subsys {
+	spdif1: spdif@59030000 {
+		compatible = "fsl,imx8qm-spdif";
+		reg = <0x59030000 0x10000>;
+		interrupts =  <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>, /* rx */
+			      <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; /* tx */
+		clocks = <&spdif1_lpcg IMX_LPCG_CLK_4>, /* core */
+			 <&clk_dummy>, /* rxtx0 */
+			 <&spdif1_lpcg IMX_LPCG_CLK_5>, /* rxtx1 */
+			 <&clk_dummy>, /* rxtx2 */
+			 <&clk_dummy>, /* rxtx3 */
+			 <&clk_dummy>, /* rxtx4 */
+			 <&audio_ipg_clk>, /* rxtx5 */
+			 <&clk_dummy>, /* rxtx6 */
+			 <&clk_dummy>, /* rxtx7 */
+			 <&clk_dummy>; /* spba */
+		clock-names = "core", "rxtx0",
+			      "rxtx1", "rxtx2",
+			      "rxtx3", "rxtx4",
+			      "rxtx5", "rxtx6",
+			      "rxtx7", "spba";
+		dmas = <&edma0 10 0 5>, <&edma0 11 0 4>;
+		dma-names = "rx", "tx";
+		power-domains = <&pd IMX_SC_R_SPDIF_1>;
+		status = "disabled";
+	};
 
 	sai4: sai@59080000 {
 		compatible = "fsl,imx8qm-sai";
@@ -109,6 +134,19 @@ sai5: sai@59090000 {
 		status = "disabled";
 	};
 
+	spdif1_lpcg: clock-controller@59430000 {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x59430000 0x10000>;
+		#clock-cells = <1>;
+		clocks = <&acm IMX_ADMA_ACM_SPDIF1_TX_CLK_SEL>,
+			 <&audio_ipg_clk>;
+		clock-indices = <IMX_LPCG_CLK_5>, <IMX_LPCG_CLK_4>;
+		clock-output-names = "spdif1_lpcg_tx_clk",
+				     "spdif1_lpcg_gclkw";
+		power-domains = <&pd IMX_SC_R_SPDIF_1>;
+		status = "disabled";
+	};
+
 	sai4_lpcg: clock-controller@59480000 {
 		compatible = "fsl,imx8qxp-lpcg";
 		reg = <0x59480000 0x10000>;

-- 
2.43.0

[PATCH v2 3/4] arm64: dts: imx8qm-ss-lsio: add lsio mu8 and mu8b

[Frank.Li]

From: Frank Li <Frank.Li@nxp.com>

Add mu8 and mu8b mailbox nodes.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
change in v2
- remove reduntant mu6, found by sashiko
---
 arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi
index b483134f84d18..e055d41f77cb0 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi
@@ -3,6 +3,27 @@
  * Copyright 2019-2020 NXP
  *	Dong Aisheng <aisheng.dong@nxp.com>
  */
+&lsio_subsys {
+	lsio_mu8: mailbox@5d230000 {
+		compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu";
+		reg = <0x5d230000 0x10000>;
+		interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+		#mbox-cells = <2>;
+		power-domains = <&pd IMX_SC_R_MU_8A>;
+		status = "disabled";
+	};
+
+	lsio_mu8b: mailbox@5d2c0000 {
+		compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu";
+		reg = <0x5d2c0000 0x10000>;
+		interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
+		#mbox-cells = <2>;
+		fsl,mu-side-b;
+		power-domains = <&pd IMX_SC_R_MU_8B>;
+		status = "disabled";
+	};
+
+};
 
 &lsio_gpio0 {
 	compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";

-- 
2.43.0

[PATCH v2 4/4] arm64: dts: imx8-ss-audio: Fix LPCG clock indices for ASRC0

[Frank.Li]

From: Frank Li <Frank.Li@nxp.com>

The LPCG clock indices for ASRC0 and AUD_PLL_DIV0 are swapped. The ASRC0
LPCG provides only IMX_LPCG_CLK_4, so update the ASRC0 clock consumer to
use IMX_LPCG_CLK_4 instead of the non-existent IMX_LPCG_CLK_0.

Likewise, the AUD_PLL_DIV0 LPCG provides only IMX_LPCG_CLK_0, so update its
clock consumer to use IMX_LPCG_CLK_0 instead of the non-existent
IMX_LPCG_CLK_4.

Fixes: 5125617c7a4d3 ("arm64: dts: imx8qxp: add asrc[0,1], esai0, spdif0 and sai[4,5]")
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi
index 5e4233ccfde46..f473d81f67ffa 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi
@@ -124,10 +124,10 @@ asrc0: asrc@59000000 {
 		compatible = "fsl,imx8qm-asrc";
 		reg = <0x59000000 0x10000>;
 		interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&asrc0_lpcg IMX_LPCG_CLK_0>,
-			 <&asrc0_lpcg IMX_LPCG_CLK_0>,
-			 <&aud_pll_div0_lpcg IMX_LPCG_CLK_4>,
-			 <&aud_pll_div1_lpcg IMX_LPCG_CLK_4>,
+		clocks = <&asrc0_lpcg IMX_LPCG_CLK_4>,
+			 <&asrc0_lpcg IMX_LPCG_CLK_4>,
+			 <&aud_pll_div0_lpcg IMX_LPCG_CLK_0>,
+			 <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>,
 			 <&acm IMX_ADMA_ACM_AUD_CLK0_SEL>,
 			 <&acm IMX_ADMA_ACM_AUD_CLK1_SEL>,
 			 <&clk_dummy>,

-- 
2.43.0

Re: [PATCH v2 2/4] arm64: dts: imx8qm-ss-audio: add spdif1 node

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The new clock controller node `spdif1_lpcg` is incorrectly marked with `status = "disabled";`. In i.MX8 device trees, LPCG (Local Peripheral Clock Gate) nodes provide clocks to hardware blocks and are intended to be enabled by default at the SoC level, as the clock framework automatically manages them. Setting `status = "disabled";` means the device node will not be instantiated by the OF core, and its platform driver (`imx8qxp-lpcg-clk`) will not probe. Consequently, when a board file enables `spdif1` (using `&spdif1 { status = "okay"; };`), the `spdif1` driver will fail to probe with a persistent `-EPROBE_DEFER` error because its required clock provider (`spdif1_lpcg`) is unavailable.
--

--- Patch [2]: [PATCH v2 2/4] arm64: dts: imx8qm-ss-audio: add spdif1 node ---
commit 5e80d17ca35f0e8c498b103cd29fc869f77a9125
Author: Frank Li <Frank.Li@nxp.com>
arm64: dts: imx8qm-ss-audio: add spdif1 node

This commit adds the spdif1 audio node and its corresponding local peripheral
clock gate (LPCG) node to the imx8qm-ss-audio device tree.

> diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-audio.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-audio.dtsi
> --- a/arch/arm64/boot/dts/freescale/imx8qm-ss-audio.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-audio.dtsi
[ ... ]
> @@ -109,6 +134,19 @@ sai5: sai@59090000 {
>  		status = "disabled";
>  	};
>  
> +	spdif1_lpcg: clock-controller@59430000 {
> +		compatible = "fsl,imx8qxp-lpcg";
> +		reg = <0x59430000 0x10000>;
> +		#clock-cells = <1>;
> +		clocks = <&acm IMX_ADMA_ACM_SPDIF1_TX_CLK_SEL>,
> +			 <&audio_ipg_clk>;
> +		clock-indices = <IMX_LPCG_CLK_5>, <IMX_LPCG_CLK_4>;
> +		clock-output-names = "spdif1_lpcg_tx_clk",
> +				     "spdif1_lpcg_gclkw";
> +		power-domains = <&pd IMX_SC_R_SPDIF_1>;
> +		status = "disabled";

[Severity: Medium]
Will this cause a persistent probe deferral for spdif1?

Since LPCG nodes provide clocks to hardware blocks, they are typically enabled
by default at the SoC level so the clock framework can manage them. Setting
the status to disabled here means the clock provider won't probe unless a
board file explicitly enables it.

If a board file only enables spdif1, won't it fail to probe with -EPROBE_DEFER
because its required clock provider is unavailable?

> +	};

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260709-qm_dts-v2-0-3ebcce82bb79@nxp.com?part=2