* [PATCH 2/3] pmdomain: mediatek: Add support for secure modem power domain control
2026-07-14 13:43 [PATCH 0/3] pmdomain: mediatek: Add MT6858 support Nikolai Burov via B4 Relay
2026-07-14 13:43 ` [PATCH 1/3] dt-bindings: power: Add MediaTek MT6858 power domain controller Nikolai Burov via B4 Relay
@ 2026-07-14 13:43 ` Nikolai Burov via B4 Relay
2026-07-14 13:51 ` sashiko-bot
2026-07-14 15:28 ` Matthias Brugger
2026-07-14 13:43 ` [PATCH 3/3] pmdomain: mediatek: Add support for MT6858 SoC Nikolai Burov via B4 Relay
2 siblings, 2 replies; 8+ messages in thread
From: Nikolai Burov via B4 Relay @ 2026-07-14 13:43 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Ulf Hansson
Cc: Matthias Brugger, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, linux-pm, Nikolai Burov, Nikolai Burov
From: Nikolai Burov <nikolai.burov@jolla.com>
On recent MediaTek SoCs such as MT6858, the kernel is required to use
a secure monitor call (SMC) to enable or disable the modem power domain.
The power domain control register can be read, but firmware prevents it
from being modified directly. Other parts of the power sequence, such as
setting the ext_buck_iso register, still need to be performed on the
kernel side.
In preparation for modem support, add a flag to enable this new power
sequence for SoCs that need it.
Signed-off-by: Nikolai Burov <nikolai.burov@jolla.com>
---
drivers/pmdomain/mediatek/mtk-pm-domains.c | 54 +++++++++++++++++++++++++++---
drivers/pmdomain/mediatek/mtk-pm-domains.h | 1 +
include/linux/soc/mediatek/mtk_sip_svc.h | 3 ++
3 files changed, 53 insertions(+), 5 deletions(-)
diff --git a/drivers/pmdomain/mediatek/mtk-pm-domains.c b/drivers/pmdomain/mediatek/mtk-pm-domains.c
index e1cfd4223473..56437b32b252 100644
--- a/drivers/pmdomain/mediatek/mtk-pm-domains.c
+++ b/drivers/pmdomain/mediatek/mtk-pm-domains.c
@@ -57,6 +57,12 @@
#define MTK_SIP_KERNEL_HWCCF_CONTROL MTK_SIP_SMC_CMD(0x540)
+/* Power domain commands for MTK_SIP_KERNEL_CCCI_CONTROL */
+enum {
+ MTK_MD_MTCMOS_ENABLE = 18,
+ MTK_MD_MTCMOS_DISABLE = 19,
+};
+
struct scpsys_domain {
struct generic_pm_domain genpd;
const struct scpsys_domain_data *data;
@@ -615,6 +621,34 @@ static void scpsys_modem_pwrseq_off(struct scpsys_domain *pd)
regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_RST_B_BIT);
}
+static bool scpsys_modem_sec_poll(unsigned long cmd)
+{
+ struct arm_smccc_res res;
+
+ arm_smccc_smc(MTK_SIP_KERNEL_CCCI_CONTROL, cmd, 1, 0, 0, 0, 0, 0, &res);
+
+ return res.a0 == 0;
+}
+
+static int scpsys_modem_sec_power_on(bool on)
+{
+ struct arm_smccc_res res;
+ unsigned long cmd = on ? MTK_MD_MTCMOS_ENABLE : MTK_MD_MTCMOS_DISABLE;
+ bool tmp;
+ int ret;
+
+ arm_smccc_smc(MTK_SIP_KERNEL_CCCI_CONTROL, cmd, 0, 0, 0, 0, 0, 0, &res);
+ if (res.a0 == 0)
+ return 0;
+
+ ret = readx_poll_timeout(scpsys_modem_sec_poll, cmd, tmp, tmp,
+ MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
static int scpsys_power_on(struct generic_pm_domain *genpd)
{
struct scpsys_domain *pd = container_of(genpd, struct scpsys_domain, genpd);
@@ -633,7 +667,9 @@ static int scpsys_power_on(struct generic_pm_domain *genpd)
regmap_clear_bits(scpsys->base, pd->data->ext_buck_iso_offs,
pd->data->ext_buck_iso_mask);
- if (MTK_SCPD_CAPS(pd, MTK_SCPD_MODEM_PWRSEQ))
+ if (MTK_SCPD_CAPS(pd, MTK_SCPD_MODEM_SECURE))
+ ret = scpsys_modem_sec_power_on(true);
+ else if (MTK_SCPD_CAPS(pd, MTK_SCPD_MODEM_PWRSEQ))
ret = scpsys_modem_pwrseq_on(pd);
else
ret = scpsys_ctl_pwrseq_on(pd);
@@ -709,6 +745,12 @@ static int scpsys_power_off(struct generic_pm_domain *genpd)
if (ret < 0)
return ret;
+ if (MTK_SCPD_CAPS(pd, MTK_SCPD_MODEM_SECURE)) {
+ ret = scpsys_modem_sec_power_on(false);
+ if (ret)
+ return ret;
+ }
+
if (pd->data->ext_buck_iso_offs && MTK_SCPD_CAPS(pd, MTK_SCPD_EXT_BUCK_ISO))
regmap_set_bits(scpsys->base, pd->data->ext_buck_iso_offs,
pd->data->ext_buck_iso_mask);
@@ -719,10 +761,12 @@ static int scpsys_power_off(struct generic_pm_domain *genpd)
if (ret < 0)
return ret;
- if (MTK_SCPD_CAPS(pd, MTK_SCPD_MODEM_PWRSEQ))
- scpsys_modem_pwrseq_off(pd);
- else
- scpsys_ctl_pwrseq_off(pd);
+ if (!MTK_SCPD_CAPS(pd, MTK_SCPD_MODEM_SECURE)) {
+ if (MTK_SCPD_CAPS(pd, MTK_SCPD_MODEM_PWRSEQ))
+ scpsys_modem_pwrseq_off(pd);
+ else
+ scpsys_ctl_pwrseq_off(pd);
+ }
/* wait until PWR_ACK = 0 */
ret = readx_poll_timeout(scpsys_domain_is_on, pd, tmp, !tmp, MTK_POLL_DELAY_US,
diff --git a/drivers/pmdomain/mediatek/mtk-pm-domains.h b/drivers/pmdomain/mediatek/mtk-pm-domains.h
index a5dca24cbc2f..b1a3d54a7b01 100644
--- a/drivers/pmdomain/mediatek/mtk-pm-domains.h
+++ b/drivers/pmdomain/mediatek/mtk-pm-domains.h
@@ -17,6 +17,7 @@
#define MTK_SCPD_MODEM_PWRSEQ BIT(10)
#define MTK_SCPD_SKIP_RESET_B BIT(11)
#define MTK_SCPD_INFRA_PWR_CTL BIT(12)
+#define MTK_SCPD_MODEM_SECURE BIT(13)
#define MTK_SCPD_CAPS(_scpd, _x) ((_scpd)->data ? \
(_scpd)->data->caps & (_x) : \
(_scpd)->hwv_data->caps & (_x))
diff --git a/include/linux/soc/mediatek/mtk_sip_svc.h b/include/linux/soc/mediatek/mtk_sip_svc.h
index abe24a73ee19..6c95a29b79fa 100644
--- a/include/linux/soc/mediatek/mtk_sip_svc.h
+++ b/include/linux/soc/mediatek/mtk_sip_svc.h
@@ -22,6 +22,9 @@
ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, MTK_SIP_SMC_CONVENTION, \
ARM_SMCCC_OWNER_SIP, fn_id)
+/* Modem related SMC call */
+#define MTK_SIP_KERNEL_CCCI_CONTROL MTK_SIP_SMC_CMD(0x505)
+
/* DVFSRC SMC calls */
#define MTK_SIP_DVFSRC_VCOREFS_CONTROL MTK_SIP_SMC_CMD(0x506)
--
2.54.0
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH 3/3] pmdomain: mediatek: Add support for MT6858 SoC
2026-07-14 13:43 [PATCH 0/3] pmdomain: mediatek: Add MT6858 support Nikolai Burov via B4 Relay
2026-07-14 13:43 ` [PATCH 1/3] dt-bindings: power: Add MediaTek MT6858 power domain controller Nikolai Burov via B4 Relay
2026-07-14 13:43 ` [PATCH 2/3] pmdomain: mediatek: Add support for secure modem power domain control Nikolai Burov via B4 Relay
@ 2026-07-14 13:43 ` Nikolai Burov via B4 Relay
2026-07-14 13:58 ` sashiko-bot
2 siblings, 1 reply; 8+ messages in thread
From: Nikolai Burov via B4 Relay @ 2026-07-14 13:43 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Ulf Hansson
Cc: Matthias Brugger, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, linux-pm, Nikolai Burov, Nikolai Burov
From: Nikolai Burov <nikolai.burov@jolla.com>
Add support for the power domains found in the MediaTek MT6858 SoC.
Signed-off-by: Nikolai Burov <nikolai.burov@jolla.com>
---
drivers/pmdomain/mediatek/mt6858-pm-domains.h | 462 ++++++++++++++++++++++++++
drivers/pmdomain/mediatek/mtk-pm-domains.c | 5 +
drivers/pmdomain/mediatek/mtk-pm-domains.h | 5 +
3 files changed, 472 insertions(+)
diff --git a/drivers/pmdomain/mediatek/mt6858-pm-domains.h b/drivers/pmdomain/mediatek/mt6858-pm-domains.h
new file mode 100644
index 000000000000..6d85835115b4
--- /dev/null
+++ b/drivers/pmdomain/mediatek/mt6858-pm-domains.h
@@ -0,0 +1,462 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2025 MediaTek Inc.
+ * KY Liu <ky.liu@mediatek.com>
+ * Copyright (c) 2026 Jolla Mobile Ltd
+ * Nikolai Burov <nikolai.burov@jolla.com>
+ */
+
+#ifndef __SOC_MEDIATEK_MT6858_PM_DOMAINS_H
+#define __SOC_MEDIATEK_MT6858_PM_DOMAINS_H
+
+#include "mtk-pm-domains.h"
+#include <dt-bindings/power/mediatek,mt6858-power.h>
+
+/* TOP_AXI registers */
+#define MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_SET 0x0c14
+#define MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_CLR 0x0c18
+#define MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_RDY 0x0c1c
+
+#define MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_DIS0 (BIT(0) | BIT(1) | BIT(18))
+#define MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_ISP_IPE BIT(2)
+#define MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_ISP_IMG1 BIT(3)
+#define MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_VEN0 BIT(12)
+#define MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_VDE0 BIT(20)
+#define MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_CAM_MAIN (BIT(30) | BIT(31))
+
+#define MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_SET 0x0c24
+#define MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_CLR 0x0c28
+#define MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_RDY 0x0c2c
+
+#define MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_ISP_IMG1 BIT(7)
+#define MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_ISP_IPE BIT(8)
+#define MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_CAM_MAIN (BIT(9) | BIT(10))
+#define MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_VEN0 BIT(12)
+#define MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_VDE0 BIT(13)
+#define MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_MM_INFRA (GENMASK(3, 1) | BIT(6))
+#define MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_MM_INFRA_2ND (BIT(0) | BIT(5) | GENMASK(15, 7))
+
+#define MT6858_TOP_AXI_PROT_EN_INFRASYS_STA_0_SET 0x0c44
+#define MT6858_TOP_AXI_PROT_EN_INFRASYS_STA_0_CLR 0x0c48
+#define MT6858_TOP_AXI_PROT_EN_INFRASYS_STA_0_RDY 0x0c4c
+
+#define MT6858_TOP_AXI_PROT_EN_INFRASYS_STA_0_CONN BIT(8)
+#define MT6858_TOP_AXI_PROT_EN_INFRASYS_STA_0_MM_INFRA BIT(16)
+
+#define MT6858_TOP_AXI_PROT_EN_INFRASYS_STA_1_SET 0x0c54
+#define MT6858_TOP_AXI_PROT_EN_INFRASYS_STA_1_CLR 0x0c58
+#define MT6858_TOP_AXI_PROT_EN_INFRASYS_STA_1_RDY 0x0c5c
+
+#define MT6858_TOP_AXI_PROT_EN_INFRASYS_STA_1_MM_INFRA BIT(11)
+#define MT6858_TOP_AXI_PROT_EN_INFRASYS_STA_1_CONN BIT(12)
+
+#define MT6858_TOP_AXI_PROT_EN_EMISYS_STA_0_SET 0x0c64
+#define MT6858_TOP_AXI_PROT_EN_EMISYS_STA_0_CLR 0x0c68
+#define MT6858_TOP_AXI_PROT_EN_EMISYS_STA_0_RDY 0x0c6c
+
+#define MT6858_TOP_AXI_PROT_EN_EMISYS_STA_0_MM_INFRA (BIT(20) | BIT(21))
+
+#define MT6858_TOP_AXI_PROT_EN_PERISYS_STA_0_SET 0x0c84
+#define MT6858_TOP_AXI_PROT_EN_PERISYS_STA_0_CLR 0x0c88
+#define MT6858_TOP_AXI_PROT_EN_PERISYS_STA_0_RDY 0x0c8c
+
+#define MT6858_TOP_AXI_PROT_EN_PERISYS_STA_0_AUDIO BIT(6)
+#define MT6858_TOP_AXI_PROT_EN_PERISYS_STA_0_SSUSB BIT(7)
+
+#define MT6858_TOP_AXI_PROT_EN_MCU_STA_0_SET 0x0c94
+#define MT6858_TOP_AXI_PROT_EN_MCU_STA_0_CLR 0x0c98
+#define MT6858_TOP_AXI_PROT_EN_MCU_STA_0_RDY 0x0c9c
+
+#define MT6858_TOP_AXI_PROT_EN_MCU_STA_0_CONN BIT(1)
+#define MT6858_TOP_AXI_PROT_EN_MCU_STA_0_CONN_2ND BIT(0)
+
+/* {IMG,IPE,CAM}_SUBx registers */
+#define MT6858_SUBx_PROT_EN_SET 0x03c4
+#define MT6858_SUBx_PROT_EN_CLR 0x03c8
+#define MT6858_SUBx_PROT_EN_STA 0x03cc
+
+#define MT6858_IMG_SUB0_PROT_EN_SMI_ISP_IMG1 (BIT(0) | BIT(1))
+
+#define MT6858_IPE_SUB0_PROT_EN_SMI_ISP_IPE (BIT(0) | BIT(1))
+
+#define MT6858_CAM_SUB0_PROT_EN_SMI_CAM_MAIN BIT(0)
+#define MT6858_CAM_SUB0_PROT_EN_SMI_CAM_SUBB BIT(1)
+
+#define MT6858_CAM_SUB1_PROT_EN_SMI_CAM_MAIN BIT(0)
+#define MT6858_CAM_SUB1_PROT_EN_SMI_CAM_SUBA BIT(1)
+
+/* VLP_AXI registers */
+#define MT6858_VLP_AXI_PROT_EN_SET 0x0214
+#define MT6858_VLP_AXI_PROT_EN_CLR 0x0218
+#define MT6858_VLP_AXI_PROT_EN_STA 0x021c
+
+#define MT6858_VLP_AXI_PROT_EN_MM_PROC BIT(8)
+#define MT6858_VLP_AXI_PROT_EN_MM_PROC_2ND (BIT(9) | BIT(10))
+
+/* PWR_CON registers */
+#define MT6858_PWR_ACK BIT(30)
+#define MT6858_PWR_ACK_2ND BIT(31)
+
+static enum scpsys_bus_prot_block scpsys_bus_prot_blocks_mt6858[] = {
+ BUS_PROT_BLOCK_INFRA,
+ BUS_PROT_BLOCK_IMG_SUB0,
+ BUS_PROT_BLOCK_CAM_SUB1,
+ BUS_PROT_BLOCK_CAM_SUB0,
+ BUS_PROT_BLOCK_IPE_SUB0,
+ BUS_PROT_BLOCK_VLP,
+};
+
+static const struct scpsys_domain_data scpsys_domain_data_mt6858[] = {
+ [MT6858_POWER_DOMAIN_MD] = {
+ .name = "md",
+ .sta_mask = MT6858_PWR_ACK,
+ .ctl_offs = 0xe00,
+ .pwr_sta_offs = 0xe00,
+ .pwr_sta2nd_offs = 0xe00,
+ .ext_buck_iso_offs = 0xf20,
+ .ext_buck_iso_mask = GENMASK(1, 0),
+ .caps = MTK_SCPD_MODEM_SECURE | MTK_SCPD_EXT_BUCK_ISO |
+ MTK_SCPD_KEEP_DEFAULT_OFF,
+ },
+ [MT6858_POWER_DOMAIN_CONN] = {
+ .name = "conn",
+ .sta_mask = MT6858_PWR_ACK,
+ .sta2nd_mask = MT6858_PWR_ACK_2ND,
+ .ctl_offs = 0xe04,
+ .pwr_sta_offs = 0xe04,
+ .pwr_sta2nd_offs = 0xe04,
+ .bp_cfg = {
+ BUS_PROT_WR_IGN(INFRA,
+ MT6858_TOP_AXI_PROT_EN_MCU_STA_0_CONN,
+ MT6858_TOP_AXI_PROT_EN_MCU_STA_0_SET,
+ MT6858_TOP_AXI_PROT_EN_MCU_STA_0_CLR,
+ MT6858_TOP_AXI_PROT_EN_MCU_STA_0_RDY),
+ BUS_PROT_WR_IGN(INFRA,
+ MT6858_TOP_AXI_PROT_EN_INFRASYS_STA_1_CONN,
+ MT6858_TOP_AXI_PROT_EN_INFRASYS_STA_1_SET,
+ MT6858_TOP_AXI_PROT_EN_INFRASYS_STA_1_CLR,
+ MT6858_TOP_AXI_PROT_EN_INFRASYS_STA_1_RDY),
+ BUS_PROT_WR_IGN(INFRA,
+ MT6858_TOP_AXI_PROT_EN_MCU_STA_0_CONN_2ND,
+ MT6858_TOP_AXI_PROT_EN_MCU_STA_0_SET,
+ MT6858_TOP_AXI_PROT_EN_MCU_STA_0_CLR,
+ MT6858_TOP_AXI_PROT_EN_MCU_STA_0_RDY),
+ BUS_PROT_WR_IGN(INFRA,
+ MT6858_TOP_AXI_PROT_EN_INFRASYS_STA_0_CONN,
+ MT6858_TOP_AXI_PROT_EN_INFRASYS_STA_0_SET,
+ MT6858_TOP_AXI_PROT_EN_INFRASYS_STA_0_CLR,
+ MT6858_TOP_AXI_PROT_EN_INFRASYS_STA_0_RDY),
+ },
+ .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
+ },
+ [MT6858_POWER_DOMAIN_AUDIO] = {
+ .name = "audio",
+ .sta_mask = MT6858_PWR_ACK,
+ .sta2nd_mask = MT6858_PWR_ACK_2ND,
+ .ctl_offs = 0xe18,
+ .pwr_sta_offs = 0xe18,
+ .pwr_sta2nd_offs = 0xe18,
+ .sram_pdn_bits = BIT(8),
+ .sram_pdn_ack_bits = BIT(12),
+ .bp_cfg = {
+ BUS_PROT_WR_IGN(INFRA,
+ MT6858_TOP_AXI_PROT_EN_PERISYS_STA_0_AUDIO,
+ MT6858_TOP_AXI_PROT_EN_PERISYS_STA_0_SET,
+ MT6858_TOP_AXI_PROT_EN_PERISYS_STA_0_CLR,
+ MT6858_TOP_AXI_PROT_EN_PERISYS_STA_0_RDY),
+ },
+ },
+ [MT6858_POWER_DOMAIN_ISP_IMG1] = {
+ .name = "isp-img1",
+ .sta_mask = MT6858_PWR_ACK,
+ .sta2nd_mask = MT6858_PWR_ACK_2ND,
+ .ctl_offs = 0xe28,
+ .pwr_sta_offs = 0xe28,
+ .pwr_sta2nd_offs = 0xe28,
+ .sram_pdn_bits = BIT(8),
+ .sram_pdn_ack_bits = BIT(12),
+ .bp_cfg = {
+ BUS_PROT_WR_IGN(INFRA,
+ MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_ISP_IMG1,
+ MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_SET,
+ MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_CLR,
+ MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_RDY),
+ BUS_PROT_WR_IGN(INFRA,
+ MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_ISP_IMG1,
+ MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_SET,
+ MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_CLR,
+ MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_RDY),
+ BUS_PROT_WR_IGN(IMG_SUB0,
+ MT6858_IMG_SUB0_PROT_EN_SMI_ISP_IMG1,
+ MT6858_SUBx_PROT_EN_SET,
+ MT6858_SUBx_PROT_EN_CLR,
+ MT6858_SUBx_PROT_EN_STA),
+ },
+ .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
+ },
+ [MT6858_POWER_DOMAIN_ISP_IMG2] = {
+ .name = "isp-img2",
+ .sta_mask = MT6858_PWR_ACK,
+ .sta2nd_mask = MT6858_PWR_ACK_2ND,
+ .ctl_offs = 0xe2c,
+ .pwr_sta_offs = 0xe2c,
+ .pwr_sta2nd_offs = 0xe2c,
+ .sram_pdn_bits = BIT(8),
+ .sram_pdn_ack_bits = BIT(12),
+ .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
+ },
+ [MT6858_POWER_DOMAIN_ISP_IPE] = {
+ .name = "isp-ipe",
+ .sta_mask = MT6858_PWR_ACK,
+ .sta2nd_mask = MT6858_PWR_ACK_2ND,
+ .ctl_offs = 0xe30,
+ .pwr_sta_offs = 0xe30,
+ .pwr_sta2nd_offs = 0xe30,
+ .sram_pdn_bits = BIT(8),
+ .sram_pdn_ack_bits = BIT(12),
+ .bp_cfg = {
+ BUS_PROT_WR_IGN(INFRA,
+ MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_ISP_IPE,
+ MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_SET,
+ MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_CLR,
+ MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_RDY),
+ BUS_PROT_WR_IGN(INFRA,
+ MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_ISP_IPE,
+ MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_SET,
+ MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_CLR,
+ MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_RDY),
+ BUS_PROT_WR_IGN(IPE_SUB0,
+ MT6858_IPE_SUB0_PROT_EN_SMI_ISP_IPE,
+ MT6858_SUBx_PROT_EN_SET,
+ MT6858_SUBx_PROT_EN_CLR,
+ MT6858_SUBx_PROT_EN_STA),
+ },
+ .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
+ },
+ [MT6858_POWER_DOMAIN_VDE0] = {
+ .name = "vde0",
+ .sta_mask = MT6858_PWR_ACK,
+ .sta2nd_mask = MT6858_PWR_ACK_2ND,
+ .ctl_offs = 0xe34,
+ .pwr_sta_offs = 0xe34,
+ .pwr_sta2nd_offs = 0xe34,
+ .sram_pdn_bits = BIT(8),
+ .sram_pdn_ack_bits = BIT(12),
+ .bp_cfg = {
+ BUS_PROT_WR_IGN(INFRA,
+ MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_VDE0,
+ MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_SET,
+ MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_CLR,
+ MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_RDY),
+ BUS_PROT_WR_IGN(INFRA,
+ MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_VDE0,
+ MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_SET,
+ MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_CLR,
+ MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_RDY),
+ },
+ },
+ [MT6858_POWER_DOMAIN_VEN0] = {
+ .name = "ven0",
+ .sta_mask = MT6858_PWR_ACK,
+ .sta2nd_mask = MT6858_PWR_ACK_2ND,
+ .ctl_offs = 0xe3c,
+ .pwr_sta_offs = 0xe3c,
+ .pwr_sta2nd_offs = 0xe3c,
+ .sram_pdn_bits = BIT(8),
+ .sram_pdn_ack_bits = BIT(12),
+ .bp_cfg = {
+ BUS_PROT_WR_IGN(INFRA,
+ MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_VEN0,
+ MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_SET,
+ MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_CLR,
+ MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_RDY),
+ BUS_PROT_WR_IGN(INFRA,
+ MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_VEN0,
+ MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_SET,
+ MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_CLR,
+ MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_RDY),
+ },
+ },
+ [MT6858_POWER_DOMAIN_CAM_MAIN] = {
+ .name = "cam-main",
+ .sta_mask = MT6858_PWR_ACK,
+ .sta2nd_mask = MT6858_PWR_ACK_2ND,
+ .ctl_offs = 0xe44,
+ .pwr_sta_offs = 0xe44,
+ .pwr_sta2nd_offs = 0xe44,
+ .sram_pdn_bits = BIT(8),
+ .sram_pdn_ack_bits = BIT(12),
+ .bp_cfg = {
+ BUS_PROT_WR_IGN(INFRA,
+ MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_CAM_MAIN,
+ MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_SET,
+ MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_CLR,
+ MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_RDY),
+ BUS_PROT_WR_IGN(INFRA,
+ MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_CAM_MAIN,
+ MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_SET,
+ MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_CLR,
+ MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_RDY),
+ BUS_PROT_WR_IGN(CAM_SUB0,
+ MT6858_CAM_SUB0_PROT_EN_SMI_CAM_MAIN,
+ MT6858_SUBx_PROT_EN_SET,
+ MT6858_SUBx_PROT_EN_CLR,
+ MT6858_SUBx_PROT_EN_STA),
+ BUS_PROT_WR_IGN(CAM_SUB1,
+ MT6858_CAM_SUB1_PROT_EN_SMI_CAM_MAIN,
+ MT6858_SUBx_PROT_EN_SET,
+ MT6858_SUBx_PROT_EN_CLR,
+ MT6858_SUBx_PROT_EN_STA),
+ },
+ .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
+ },
+ [MT6858_POWER_DOMAIN_CAM_SUBA] = {
+ .name = "cam-suba",
+ .sta_mask = MT6858_PWR_ACK,
+ .sta2nd_mask = MT6858_PWR_ACK_2ND,
+ .ctl_offs = 0xe4c,
+ .pwr_sta_offs = 0xe4c,
+ .pwr_sta2nd_offs = 0xe4c,
+ .sram_pdn_bits = BIT(8),
+ .sram_pdn_ack_bits = BIT(12),
+ .bp_cfg = {
+ BUS_PROT_WR_IGN(CAM_SUB1,
+ MT6858_CAM_SUB1_PROT_EN_SMI_CAM_SUBA,
+ MT6858_SUBx_PROT_EN_SET,
+ MT6858_SUBx_PROT_EN_CLR,
+ MT6858_SUBx_PROT_EN_STA),
+ },
+ .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
+ },
+ [MT6858_POWER_DOMAIN_CAM_SUBB] = {
+ .name = "cam-subb",
+ .sta_mask = MT6858_PWR_ACK,
+ .sta2nd_mask = MT6858_PWR_ACK_2ND,
+ .ctl_offs = 0xe50,
+ .pwr_sta_offs = 0xe50,
+ .pwr_sta2nd_offs = 0xe50,
+ .sram_pdn_bits = BIT(8),
+ .sram_pdn_ack_bits = BIT(12),
+ .bp_cfg = {
+ BUS_PROT_WR_IGN(CAM_SUB0,
+ MT6858_CAM_SUB0_PROT_EN_SMI_CAM_SUBB,
+ MT6858_SUBx_PROT_EN_SET,
+ MT6858_SUBx_PROT_EN_CLR,
+ MT6858_SUBx_PROT_EN_STA),
+ },
+ .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
+ },
+ [MT6858_POWER_DOMAIN_DIS0] = {
+ .name = "dis0",
+ .sta_mask = MT6858_PWR_ACK,
+ .sta2nd_mask = MT6858_PWR_ACK_2ND,
+ .ctl_offs = 0xe6c,
+ .pwr_sta_offs = 0xe6c,
+ .pwr_sta2nd_offs = 0xe6c,
+ .sram_pdn_bits = BIT(8),
+ .sram_pdn_ack_bits = BIT(12),
+ .bp_cfg = {
+ BUS_PROT_WR_IGN(INFRA,
+ MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_DIS0,
+ MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_SET,
+ MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_CLR,
+ MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_RDY),
+ },
+ },
+ [MT6858_POWER_DOMAIN_MM_INFRA] = {
+ .name = "mm-infra",
+ .sta_mask = MT6858_PWR_ACK,
+ .sta2nd_mask = MT6858_PWR_ACK_2ND,
+ .ctl_offs = 0xe74,
+ .pwr_sta_offs = 0xe74,
+ .pwr_sta2nd_offs = 0xe74,
+ .sram_pdn_bits = BIT(8),
+ .sram_pdn_ack_bits = BIT(12),
+ .bp_cfg = {
+ BUS_PROT_WR_IGN(INFRA,
+ MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_MM_INFRA,
+ MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_SET,
+ MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_CLR,
+ MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_RDY),
+ BUS_PROT_WR_IGN(INFRA,
+ MT6858_TOP_AXI_PROT_EN_INFRASYS_STA_1_MM_INFRA,
+ MT6858_TOP_AXI_PROT_EN_INFRASYS_STA_1_SET,
+ MT6858_TOP_AXI_PROT_EN_INFRASYS_STA_1_CLR,
+ MT6858_TOP_AXI_PROT_EN_INFRASYS_STA_1_RDY),
+ BUS_PROT_WR_IGN(INFRA,
+ MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_MM_INFRA_2ND,
+ MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_SET,
+ MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_CLR,
+ MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_RDY),
+ BUS_PROT_WR_IGN(INFRA,
+ MT6858_TOP_AXI_PROT_EN_INFRASYS_STA_0_MM_INFRA,
+ MT6858_TOP_AXI_PROT_EN_INFRASYS_STA_0_SET,
+ MT6858_TOP_AXI_PROT_EN_INFRASYS_STA_0_CLR,
+ MT6858_TOP_AXI_PROT_EN_INFRASYS_STA_0_RDY),
+ BUS_PROT_WR_IGN(INFRA,
+ MT6858_TOP_AXI_PROT_EN_EMISYS_STA_0_MM_INFRA,
+ MT6858_TOP_AXI_PROT_EN_EMISYS_STA_0_SET,
+ MT6858_TOP_AXI_PROT_EN_EMISYS_STA_0_CLR,
+ MT6858_TOP_AXI_PROT_EN_EMISYS_STA_0_RDY),
+ },
+ },
+ [MT6858_POWER_DOMAIN_MM_PROC_DORMANT] = {
+ .name = "mm-proc-dormant",
+ .sta_mask = MT6858_PWR_ACK,
+ .sta2nd_mask = MT6858_PWR_ACK_2ND,
+ .ctl_offs = 0xe78,
+ .pwr_sta_offs = 0xe78,
+ .pwr_sta2nd_offs = 0xe78,
+ .sram_pdn_bits = BIT(9),
+ .sram_pdn_ack_bits = BIT(13),
+ .bp_cfg = {
+ BUS_PROT_WR_IGN(VLP,
+ MT6858_VLP_AXI_PROT_EN_MM_PROC,
+ MT6858_VLP_AXI_PROT_EN_SET,
+ MT6858_VLP_AXI_PROT_EN_CLR,
+ MT6858_VLP_AXI_PROT_EN_STA),
+ BUS_PROT_WR_IGN(VLP,
+ MT6858_VLP_AXI_PROT_EN_MM_PROC_2ND,
+ MT6858_VLP_AXI_PROT_EN_SET,
+ MT6858_VLP_AXI_PROT_EN_CLR,
+ MT6858_VLP_AXI_PROT_EN_STA),
+ },
+ .caps = MTK_SCPD_SRAM_ISO | MTK_SCPD_SRAM_PDN_INVERTED,
+ },
+ [MT6858_POWER_DOMAIN_CSI_RX] = {
+ .name = "csi-rx",
+ .sta_mask = MT6858_PWR_ACK,
+ .sta2nd_mask = MT6858_PWR_ACK_2ND,
+ .ctl_offs = 0xe98,
+ .pwr_sta_offs = 0xe98,
+ .pwr_sta2nd_offs = 0xe98,
+ .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
+ },
+ [MT6858_POWER_DOMAIN_SSUSB] = {
+ .name = "ssusb",
+ .sta_mask = MT6858_PWR_ACK,
+ .sta2nd_mask = MT6858_PWR_ACK_2ND,
+ .ctl_offs = 0xea4,
+ .pwr_sta_offs = 0xea4,
+ .pwr_sta2nd_offs = 0xea4,
+ .sram_pdn_bits = BIT(8),
+ .sram_pdn_ack_bits = BIT(12),
+ .bp_cfg = {
+ BUS_PROT_WR_IGN(INFRA,
+ MT6858_TOP_AXI_PROT_EN_PERISYS_STA_0_SSUSB,
+ MT6858_TOP_AXI_PROT_EN_PERISYS_STA_0_SET,
+ MT6858_TOP_AXI_PROT_EN_PERISYS_STA_0_CLR,
+ MT6858_TOP_AXI_PROT_EN_PERISYS_STA_0_RDY),
+ },
+ },
+};
+
+static const struct scpsys_soc_data mt6858_scpsys_data = {
+ .domains_data = scpsys_domain_data_mt6858,
+ .num_domains = ARRAY_SIZE(scpsys_domain_data_mt6858),
+ .bus_prot_blocks = scpsys_bus_prot_blocks_mt6858,
+ .num_bus_prot_blocks = ARRAY_SIZE(scpsys_bus_prot_blocks_mt6858),
+ .type = SCPSYS_MTCMOS_TYPE_DIRECT_CTL,
+};
+
+#endif /* __SOC_MEDIATEK_MT6858_PM_DOMAINS_H */
diff --git a/drivers/pmdomain/mediatek/mtk-pm-domains.c b/drivers/pmdomain/mediatek/mtk-pm-domains.c
index 56437b32b252..d50d2c780cd9 100644
--- a/drivers/pmdomain/mediatek/mtk-pm-domains.c
+++ b/drivers/pmdomain/mediatek/mtk-pm-domains.c
@@ -20,6 +20,7 @@
#include "mt6735-pm-domains.h"
#include "mt6795-pm-domains.h"
+#include "mt6858-pm-domains.h"
#include "mt6893-pm-domains.h"
#include "mt8167-pm-domains.h"
#include "mt8173-pm-domains.h"
@@ -1196,6 +1197,10 @@ static const struct of_device_id scpsys_of_match[] = {
.compatible = "mediatek,mt6795-power-controller",
.data = &mt6795_scpsys_data,
},
+ {
+ .compatible = "mediatek,mt6858-power-controller",
+ .data = &mt6858_scpsys_data,
+ },
{
.compatible = "mediatek,mt6893-power-controller",
.data = &mt6893_scpsys_data,
diff --git a/drivers/pmdomain/mediatek/mtk-pm-domains.h b/drivers/pmdomain/mediatek/mtk-pm-domains.h
index b1a3d54a7b01..af55bfb0f599 100644
--- a/drivers/pmdomain/mediatek/mtk-pm-domains.h
+++ b/drivers/pmdomain/mediatek/mtk-pm-domains.h
@@ -65,6 +65,11 @@ enum scpsys_bus_prot_block {
BUS_PROT_BLOCK_INFRA_NAO,
BUS_PROT_BLOCK_SMI,
BUS_PROT_BLOCK_SPM,
+ BUS_PROT_BLOCK_IMG_SUB0,
+ BUS_PROT_BLOCK_CAM_SUB1,
+ BUS_PROT_BLOCK_CAM_SUB0,
+ BUS_PROT_BLOCK_IPE_SUB0,
+ BUS_PROT_BLOCK_VLP,
BUS_PROT_BLOCK_COUNT,
};
--
2.54.0
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