[PATCH v7] arm64: dts: s32g: Add GPR syscon region

[PATCH v7] arm64: dts: s32g: Add GPR syscon region

[Jared Kangas]

From: Dan Carpenter <error27@gmail.com>

Add the GPR syscon region for the s32 chipset.

Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org>
[jkangas@redhat.com: GPR syscon resized from 0x3000 to 0x100]
Tested-by: Jared Kangas <jkangas@redhat.com>
Signed-off-by: Jared Kangas <jkangas@redhat.com>
---
Revision of Dan's v6 patch based on discussion in [1] to avoid a panic
when reading the debugfs regmap's registers file.

[1]: https://lore.kernel.org/all/aej2X2Gp-UI3Vmvo@rh-jkangas-kernel/

v7: Shrink gpr size from 0x3000 -> 0x100, add 'arm64:' prefix to subject
v6: no change
v5: no change
v4: no change
v3: no change
v2: Remove #address-cells and #size-cells
---
 arch/arm64/boot/dts/freescale/s32g2.dtsi | 6 ++++++
 arch/arm64/boot/dts/freescale/s32g3.dtsi | 6 ++++++
 2 files changed, 12 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
index 809019ea0e299..81280ec6b07a9 100644
--- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
@@ -325,6 +325,11 @@ usdhc0-200mhz-grp4 {
 			};
 		};
 
+		gpr: syscon@4007c000 {
+			compatible = "nxp,s32g2-gpr", "syscon";
+			reg = <0x4007c000 0x100>;
+		};
+
 		ocotp: nvmem@400a4000 {
 			compatible = "nxp,s32g2-ocotp";
 			reg = <0x400a4000 0x400>;
@@ -795,6 +800,7 @@ gmac0: ethernet@4033c000 {
 			compatible = "nxp,s32g2-dwmac";
 			reg = <0x4033c000 0x2000>, /* gmac IP */
 			      <0x4007c004 0x4>;    /* GMAC_0_CTRL_STS */
+			nxp,phy-sel = <&gpr 0x4>;
 			interrupt-parent = <&gic>;
 			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "macirq";
diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi
index 22e80fc03f9c7..da35083a5e0e5 100644
--- a/arch/arm64/boot/dts/freescale/s32g3.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi
@@ -383,6 +383,11 @@ usdhc0-200mhz-grp4 {
 			};
 		};
 
+		gpr: syscon@4007c000 {
+			compatible = "nxp,s32g3-gpr", "syscon";
+			reg = <0x4007c000 0x100>;
+		};
+
 		ocotp: nvmem@400a4000 {
 			compatible = "nxp,s32g3-ocotp", "nxp,s32g2-ocotp";
 			reg = <0x400a4000 0x400>;
@@ -874,6 +879,7 @@ gmac0: ethernet@4033c000 {
 			compatible = "nxp,s32g2-dwmac";
 			reg = <0x4033c000 0x2000>, /* gmac IP */
 			      <0x4007c004 0x4>;    /* GMAC_0_CTRL_STS */
+			nxp,phy-sel = <&gpr 0x4>;
 			interrupt-parent = <&gic>;
 			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "macirq";

---
base-commit: fce2dfa773ced15f27dd27cd0b482a7473cdcf2a
change-id: 20260717-upstream-s32g-gpr-syscon-75f926f868d4

Best regards,
-- 
Jared Kangas <jkangas@redhat.com>

Re: [PATCH v7] arm64: dts: s32g: Add GPR syscon region

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] The newly added `gpr: syscon@4007c000` node is inserted out of numerical address order in the device tree.
--

--- Patch [1]: [PATCH v7] arm64: dts: s32g: Add GPR syscon region ---
commit 1ee5b4988128c1ccf8969bc9b1f12c66a53c7919
Author: Dan Carpenter <error27@gmail.com>

arm64: dts: s32g: Add GPR syscon region

This commit adds the GPR syscon region for the s32 chipset. It resizes the
GPR syscon from 0x3000 to 0x100 to avoid a panic when reading the debugfs
regmap's registers file. The changes update the device tree files for both
s32g2 and s32g3.

> diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> index 809019ea0e299..81280ec6b07a9 100644
> --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
> +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> @@ -325,6 +325,11 @@ usdhc0-200mhz-grp4 {
>  			};
>  		};
>  
> +		gpr: syscon@4007c000 {
> +			compatible = "nxp,s32g2-gpr", "syscon";
> +			reg = <0x4007c000 0x100>;
> +		};

[Severity: Low]
This isn't a bug, but should the gpr: syscon@4007c000 node be inserted in
numerical address order? It appears to be placed after the pinctrl@4009c240
node (which contains usdhc0-200mhz-grp4). To maintain standard numerical
sorting, it would typically be positioned before pinctrl@4009c240.

> +
>  		ocotp: nvmem@400a4000 {

[ ... ]

> diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi
> index 22e80fc03f9c7..da35083a5e0e5 100644
> --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi
> +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi
> @@ -383,6 +383,11 @@ usdhc0-200mhz-grp4 {
>  			};
>  		};
>  
> +		gpr: syscon@4007c000 {
> +			compatible = "nxp,s32g3-gpr", "syscon";
> +			reg = <0x4007c000 0x100>;
> +		};

[Severity: Low]
This isn't a bug, but similarly to the s32g2.dtsi changes, does this node
also break numerical address sorting? It seems to follow a node with a higher
address.

> +
>  		ocotp: nvmem@400a4000 {

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260717-upstream-s32g-gpr-syscon-v7-1-ee198f287682@redhat.com?part=1

Re: [PATCH v7] arm64: dts: s32g: Add GPR syscon region

[Krzysztof Kozlowski]

On 17/07/2026 22:33, Jared Kangas wrote:
> From: Dan Carpenter <error27@gmail.com>
> 
> Add the GPR syscon region for the s32 chipset.
> 
> Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org>
> [jkangas@redhat.com: GPR syscon resized from 0x3000 to 0x100]
> Tested-by: Jared Kangas <jkangas@redhat.com>

Your SoB implies that. We do not add Tb tags to own work. Otherwise, why
would you send code which you did not test? Same for Rb tag.

> Signed-off-by: Jared Kangas <jkangas@redhat.com>

Best regards,
Krzysztof