* [PATCH v3 0/3] Enable mutliple peripherals in IPQ5210
@ 2026-07-23 9:08 Varadarajan Narayanan
2026-07-23 9:08 ` [PATCH v3 1/3] arm64: dts: qcom: ipq5210: Add nodes for multiple peripherals Varadarajan Narayanan
` (2 more replies)
0 siblings, 3 replies; 7+ messages in thread
From: Varadarajan Narayanan @ 2026-07-23 9:08 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Varadarajan Narayanan
This couple of patches enable mutliple peripherals like USB, PCIe etc.
Additionally, it enables CPUfreq and thermal tripping points.
Please refer to [1] for initial review comments on the PCIe related DT
changes.
1 - https://lore.kernel.org/linux-arm-msm/20260514-pci-ipq5210-v1-0-a09436200b35@oss.qualcomm.com/
Signed-off-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com>
---
Changes in v3:
- Address v2 comments
- Introduce RDP504 common dtsi and two board specific dts files one
for NAND and one for eMMC
- Move 'dr_mode' to board file instead of SoC file
- Dropped 'polling-delay-passive = 0' and 'polling-delay = 0'
- Use THERMAL_NO_LIMIT in 'cooling-device'
- '\n' before status = okay
- Removed 'num-lanes' from pcie0 & pcie1 nodes
- Link to v2: https://lore.kernel.org/r/20260715-08-dts-v2-0-b060b68e0256@oss.qualcomm.com
Changes in v2:
- Change usb3@8a00000 -> usb@8a00000
- Ignore other comments as they are covered in the following prerequisite
prerequisite-message-id: <20260514-icc-ipq5210-v1-0-b5070dfbe460@oss.qualcomm.com>
- Link to v1: https://lore.kernel.org/r/20260707-08-dts-v1-0-fce82e14cd1d@oss.qualcomm.com
---
Varadarajan Narayanan (3):
arm64: dts: qcom: ipq5210: Add nodes for multiple peripherals
arm64: dts: qcom: ipq5210: Introduce RDP504 common DT file
arm64: dts: qcom: ipq5210: Introduce RDP504 variant specific DT file
.../arm64/boot/dts/qcom/ipq5210-rdp504-common.dtsi | 209 +++++++
arch/arm64/boot/dts/qcom/ipq5210-rdp504-nand.dts | 17 +
arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts | 64 +--
arch/arm64/boot/dts/qcom/ipq5210.dtsi | 604 ++++++++++++++++++++-
4 files changed, 825 insertions(+), 69 deletions(-)
---
base-commit: 06a508eb73747a8a71bed89f5766226e433594c5
change-id: 20260706-08-dts-e830bb27c72b
prerequisite-message-id: <20260514-icc-ipq5210-v1-0-b5070dfbe460@oss.qualcomm.com>
prerequisite-patch-id: 0b6145b6635b18fe79fbbff5815041b43778c5ed
prerequisite-patch-id: 924c6ff7baf4283ac7991ee94c803a00fc5cece4
prerequisite-patch-id: c2fe1800fe769dccd37f94c19860a07f979e3c4c
prerequisite-message-id: <20260615085218.1421347-1-varadarajan.narayanan@oss.qualcomm.com>
prerequisite-patch-id: 66aa95814074faffb61393faa30396c42af41126
prerequisite-patch-id: 0a03dc1c91a2f0c03af823aa43f59a9005eb8607
prerequisite-message-id: <20260701-mailbox-v2-1-5e6ebc874e4e@oss.qualcomm.com>
prerequisite-patch-id: 956b405a71f384354b5c35a44b97a0a2dcf65eb3
prerequisite-message-id: <20260703-apss-clk-v3-0-4785e89a9c58@oss.qualcomm.com>
prerequisite-patch-id: d9efdd8a09b028b1343243c5f0e78cf3e8b1e253
prerequisite-patch-id: 36cf721e00f3f5bbc3ccdc0d39503c5899771085
prerequisite-patch-id: 35e083bb85434a34d86467e53b9eae14f78da125
Best regards,
--
Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com>
^ permalink raw reply [flat|nested] 7+ messages in thread* [PATCH v3 1/3] arm64: dts: qcom: ipq5210: Add nodes for multiple peripherals 2026-07-23 9:08 [PATCH v3 0/3] Enable mutliple peripherals in IPQ5210 Varadarajan Narayanan @ 2026-07-23 9:08 ` Varadarajan Narayanan 2026-07-23 9:26 ` sashiko-bot 2026-07-23 9:08 ` [PATCH v3 2/3] arm64: dts: qcom: ipq5210: Introduce RDP504 common DT file Varadarajan Narayanan 2026-07-23 9:08 ` [PATCH v3 3/3] arm64: dts: qcom: ipq5210: Introduce RDP504 variant specific " Varadarajan Narayanan 2 siblings, 1 reply; 7+ messages in thread From: Varadarajan Narayanan @ 2026-07-23 9:08 UTC (permalink / raw) To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley Cc: linux-arm-msm, devicetree, linux-kernel, Varadarajan Narayanan Describe common IPQ5210 SoC peripherals in the base DTSI so board DTS files can enable the hardware they use. Add nodes for USB, PCIe, QPIC NAND/BAM, QFPROM, TSENS and thermal zones. Also describe the CPU OPP table and CPU cooling cells needed for CPU frequency scaling and thermal throttling. Signed-off-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com> --- arch/arm64/boot/dts/qcom/ipq5210.dtsi | 604 +++++++++++++++++++++++++++++++++- 1 file changed, 598 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5210.dtsi b/arch/arm64/boot/dts/qcom/ipq5210.dtsi index 20e8b240642c..760435dd2a8d 100644 --- a/arch/arm64/boot/dts/qcom/ipq5210.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5210.dtsi @@ -4,7 +4,9 @@ */ #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/qcom,apss-ipq.h> #include <dt-bindings/clock/qcom,ipq5210-gcc.h> +#include <dt-bindings/interconnect/qcom,ipq5210.h> #include <dt-bindings/reset/qcom,ipq5210-gcc.h> / { @@ -28,36 +30,48 @@ cpus { #address-cells = <1>; #size-cells = <0>; - cpu@0 { + cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x0>; enable-method = "psci"; next-level-cache = <&l2_0>; + #cooling-cells = <2>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + operating-points-v2 = <&cpu_opp_table>; }; - cpu@1 { + cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x1>; enable-method = "psci"; next-level-cache = <&l2_0>; + #cooling-cells = <2>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + operating-points-v2 = <&cpu_opp_table>; }; - cpu@2 { + cpu2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x2>; enable-method = "psci"; next-level-cache = <&l2_0>; + #cooling-cells = <2>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + operating-points-v2 = <&cpu_opp_table>; }; - cpu@3 { + cpu3: cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x3>; enable-method = "psci"; next-level-cache = <&l2_0>; + #cooling-cells = <2>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + operating-points-v2 = <&cpu_opp_table>; }; l2_0: l2-cache { @@ -84,6 +98,40 @@ memory@80000000 { reg = <0x0 0x80000000 0x0 0x0>; }; + cpu_opp_table: opp-table-cpu { + compatible = "operating-points-v2-kryo-cpu"; + opp-shared; + nvmem-cells = <&cpu_speed_bin>; + + opp-816000000 { + opp-hz = /bits/ 64 <816000000>; + opp-supported-hw = <0x3>; + opp-microvolt = <850000>; + clock-latency-ns = <200000>; + }; + + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-supported-hw = <0x3>; + opp-microvolt = <850000>; + clock-latency-ns = <200000>; + }; + + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-supported-hw = <0x3>; + opp-microvolt = <850000>; + clock-latency-ns = <200000>; + }; + + opp-1416000000 { + opp-hz = /bits/ 64 <1416000000>; + opp-supported-hw = <0x1>; + opp-microvolt = <1000000>; + clock-latency-ns = <200000>; + }; + }; + pmu { compatible = "arm,cortex-a53-pmu"; interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; @@ -130,6 +178,170 @@ soc@0 { dma-ranges = <0 0 0 0 0x10 0>; ranges = <0 0 0 0 0x10 0>; + qusb_phy_0: phy@7b000 { + compatible = "qcom,ipq5210-qusb2-phy", "qcom,ipq6018-qusb2-phy"; + reg = <0x0 0x0007b000 0x0 0x180>; + #phy-cells = <0>; + + clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, + <&xo_board>; + clock-names = "cfg_ahb", + "ref"; + + resets = <&gcc GCC_QUSB2_0_PHY_BCR>; + status = "disabled"; + }; + + ssphy_0: phy@7d000 { + compatible = "qcom,ipq5210-qmp-usb3-phy", "qcom,ipq9574-qmp-usb3-phy"; + reg = <0x0 0x0007d000 0x0 0xa00>; + #phy-cells = <0>; + + clocks = <&gcc GCC_USB0_AUX_CLK>, + <&xo_board>, + <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB0_PIPE_CLK>; + clock-names = "aux", + "ref", + "cfg_ahb", + "pipe"; + + resets = <&gcc GCC_USB0_PHY_BCR>, + <&gcc GCC_USB3PHY_0_PHY_BCR>; + reset-names = "phy", + "phy_phy"; + + #clock-cells = <0>; + clock-output-names = "usb0_pipe_clk"; + + status = "disabled"; + }; + + pcie0_phy: phy@84000 { + compatible = "qcom,ipq5210-qmp-gen3x1-pcie-phy"; + reg = <0x0 0x00084000 0x0 0x1000>; + + clocks = <&gcc GCC_PCIE0_AUX_CLK>, + <&gcc GCC_PCIE0_AHB_CLK>, + <&gcc GCC_PCIE0_PIPE_CLK>; + clock-names = "aux", "cfg_ahb", "pipe"; + + assigned-clocks = <&gcc GCC_PCIE0_AUX_CLK>; + assigned-clock-rates = <20000000>; + + resets = <&gcc GCC_PCIE0_PHY_BCR>, + <&gcc GCC_PCIE0PHY_PHY_BCR>; + reset-names = "phy", "common"; + + #clock-cells = <0>; + clock-output-names = "pcie0_pipe_clk"; + + #phy-cells = <0>; + status = "disabled"; + }; + + pcie1_phy: phy@f4000 { + compatible = "qcom,ipq5210-qmp-gen3x2-pcie-phy", + "qcom,ipq9574-qmp-gen3x2-pcie-phy"; + reg = <0x0 0x000f4000 0x0 0x2000>; + + clocks = <&gcc GCC_PCIE1_AUX_CLK>, + <&gcc GCC_PCIE1_AHB_CLK>, + <&gcc GCC_PCIE1_PIPE_CLK>; + clock-names = "aux", "cfg_ahb", "pipe"; + + assigned-clocks = <&gcc GCC_PCIE1_AUX_CLK>; + assigned-clock-rates = <20000000>; + + resets = <&gcc GCC_PCIE1_PHY_BCR>, + <&gcc GCC_PCIE1PHY_PHY_BCR>; + reset-names = "phy", "common"; + + #clock-cells = <0>; + clock-output-names = "pcie1_pipe_clk"; + + #phy-cells = <0>; + status = "disabled"; + }; + + efuse@a4000 { + compatible = "qcom,ipq5210-qfprom", "qcom,qfprom"; + reg = <0x0 0x000a4000 0x0 0x741>; + #address-cells = <1>; + #size-cells = <1>; + + cpu_speed_bin: cpu-speed-bin@28 { + reg = <0x28 0x1>; + bits = <0 8>; + }; + + tsens_sens11_off: s11@3dd { + reg = <0x3dd 0x1>; + bits = <4 4>; + }; + + tsens_sens12_off: s12@3de { + reg = <0x3de 0x1>; + bits = <0 4>; + }; + + tsens_sens13_off: s13@3de { + reg = <0x3de 0x1>; + bits = <4 4>; + }; + + tsens_sens14_off: s14@3e5 { + reg = <0x3e5 0x2>; + bits = <7 4>; + }; + + tsens_sens15_off: s15@3e6 { + reg = <0x3e6 0x1>; + bits = <3 4>; + }; + + tsens_mode: mode@419 { + reg = <0x419 0x1>; + bits = <0 3>; + }; + + tsens_base0: base0@419 { + reg = <0x419 0x2>; + bits = <3 10>; + }; + + tsens_base1: base1@41a { + reg = <0x41a 0x2>; + bits = <5 10>; + }; + }; + + tsens: thermal-sensor@4a9000 { + compatible = "qcom,ipq5210-tsens", "qcom,ipq5332-tsens"; + reg = <0x0 0x004a9000 0x0 0x1000>, + <0x0 0x004a8000 0x0 0x1000>; + nvmem-cells = <&tsens_mode>, + <&tsens_base0>, + <&tsens_base1>, + <&tsens_sens11_off>, + <&tsens_sens12_off>, + <&tsens_sens13_off>, + <&tsens_sens14_off>, + <&tsens_sens15_off>; + nvmem-cell-names = "mode", + "base0", + "base1", + "tsens_sens11_off", + "tsens_sens12_off", + "tsens_sens13_off", + "tsens_sens14_off", + "tsens_sens15_off"; + interrupts = <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "combined"; + #thermal-sensor-cells = <1>; + #qcom,sensors = <5>; + }; + tlmm: pinctrl@1000000 { compatible = "qcom,ipq5210-tlmm"; reg = <0x0 0x01000000 0x0 0x300000>; @@ -146,8 +358,8 @@ gcc: clock-controller@1800000 { reg = <0x0 0x01800000 0x0 0x40000>; clocks = <&xo_board>, <&sleep_clk>, - <0>, - <0>, + <&pcie0_phy>, + <&pcie1_phy>, <0>, <0>; #clock-cells = <1>; @@ -205,6 +417,87 @@ sdhc: mmc@7804000 { status = "disabled"; }; + qpic_bam: dma-controller@7984000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x0 0x07984000 0x0 0x1c000>; + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_QPIC_AHB_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + status = "disabled"; + }; + + qpic_nand: spi@79b0000 { + compatible = "qcom,ipq5210-snand", "qcom,ipq9574-snand"; + reg = <0x0 0x079b0000 0x0 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QPIC_CLK>, + <&gcc GCC_QPIC_AHB_CLK>, + <&gcc GCC_QPIC_IO_MACRO_CLK>; + clock-names = "core", + "aon", + "iom"; + + dmas = <&qpic_bam 0>, + <&qpic_bam 1>, + <&qpic_bam 2>; + dma-names = "tx", + "rx", + "cmd"; + + status = "disabled"; + }; + + usb3: usb@8a00000 { + compatible = "qcom,ipq5210-dwc3", "qcom,snps-dwc3"; + reg = <0x0 0x08a00000 0x0 0x200000>; + + clocks = <&gcc GCC_CNOC_USB_CLK>, + <&gcc GCC_USB0_MASTER_CLK>, + <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB0_SLEEP_CLK>, + <&gcc GCC_USB0_MOCK_UTMI_CLK>; + + clock-names = "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi"; + + assigned-clocks = <&gcc GCC_USB0_MASTER_CLK>, + <&gcc GCC_USB0_MOCK_UTMI_CLK>; + assigned-clock-rates = <200000000>, + <24000000>; + + interrupts-extended = <&intc GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "dwc_usb3", + "pwr_event", + "qusb2_phy", + "dp_hs_phy_irq", + "dm_hs_phy_irq"; + + phys = <&qusb_phy_0>, + <&ssphy_0>; + phy-names = "usb2-phy", + "usb3-phy"; + + resets = <&gcc GCC_USB_BCR>; + + tx-fifo-resize; + snps,is-utmi-l1-suspend; + snps,hird-threshold = /bits/ 8 <0x0>; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + + status = "disabled"; + }; + intc: interrupt-controller@b000000 { compatible = "qcom,msm-qgic2"; interrupt-controller; @@ -244,6 +537,24 @@ watchdog@b017000 { clocks = <&sleep_clk>; }; + apcs_glb: mailbox@b111000 { + compatible = "qcom,ipq5210-apcs-apps-global", + "qcom,ipq6018-apcs-apps-global"; + reg = <0x0 0x0b111000 0x0 0x1000>; + #clock-cells = <1>; + clocks = <&a53pll>, <&xo_board>, <&gcc GPLL0>; + clock-names = "pll", "xo", "gpll0"; + #mbox-cells = <1>; + }; + + a53pll: clock@b116000 { + compatible = "qcom,ipq5210-a53pll"; + reg = <0x0 0x0b116000 0x0 0x1000>; + #clock-cells = <0>; + clocks = <&xo_board>; + clock-names = "xo"; + }; + timer@b120000 { compatible = "arm,armv7-timer-mem"; reg = <0x0 0x0b120000 0x0 0x1000>; @@ -307,6 +618,287 @@ frame@b128000 { status = "disabled"; }; }; + + pcie1: pcie@50000000 { + compatible = "qcom,pcie-ipq5210", "qcom,pcie-ipq9574"; + reg = <0x0 0x50000000 0x0 0xf1c>, + <0x0 0x50000f20 0x0 0xa8>, + <0x0 0x50001000 0x0 0x1000>, + <0x0 0x000f0000 0x0 0x3000>, + <0x0 0x50100000 0x0 0x1000>, + <0x0 0x000f6000 0x0 0x1000>; + reg-names = "dbi", + "elbi", + "atu", + "parf", + "config", + "mhi"; + device_type = "pci"; + linux,pci-domain = <1>; + bus-range = <0x00 0xff>; + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x01000000 0x0 0x0 0x0 0x50200000 0x0 0x00100000>, + <0x02000000 0x0 0x0 0x0 0x50300000 0x0 0x0fd00000>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; + + interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "global"; + + clocks = <&gcc GCC_PCIE1_AXI_M_CLK>, + <&gcc GCC_PCIE1_AXI_S_CLK>, + <&gcc GCC_PCIE1_AXI_S_BRIDGE_CLK>, + <&gcc GCC_PCIE1_RCHNG_CLK>, + <&gcc GCC_PCIE1_AHB_CLK>, + <&gcc GCC_PCIE1_AUX_CLK>; + clock-names = "axi_m", + "axi_s", + "axi_bridge", + "rchng", + "ahb", + "aux"; + + resets = <&gcc GCC_PCIE1_PIPE_ARES>, + <&gcc GCC_PCIE1_CORE_STICKY_RESET>, + <&gcc GCC_PCIE1_AXI_S_STICKY_RESET>, + <&gcc GCC_PCIE1_AXI_S_ARES>, + <&gcc GCC_PCIE1_AXI_M_STICKY_RESET>, + <&gcc GCC_PCIE1_AXI_M_ARES>, + <&gcc GCC_PCIE1_AUX_ARES>, + <&gcc GCC_PCIE1_AHB_ARES>; + reset-names = "pipe", + "sticky", + "axi_s_sticky", + "axi_s", + "axi_m_sticky", + "axi_m", + "aux", + "ahb"; + + interconnects = <&gcc MASTER_CNOC_PCIE1 &gcc SLAVE_CNOC_PCIE1>, + <&gcc MASTER_SNOC_PCIE1 &gcc SLAVE_SNOC_PCIE1>; + interconnect-names = "pcie-mem", "cpu-pcie"; + + status = "disabled"; + + pcie1_port0: pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + phys = <&pcie1_phy>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + }; + + pcie0: pcie@70000000 { + compatible = "qcom,pcie-ipq5210", "qcom,pcie-ipq9574"; + reg = <0x0 0x70000000 0x0 0xf1c>, + <0x0 0x70000f20 0x0 0xa8>, + <0x0 0x70001000 0x0 0x1000>, + <0x0 0x00080000 0x0 0x3000>, + <0x0 0x70100000 0x0 0x1000>, + <0x0 0x00086000 0x0 0x1000>; + reg-names = "dbi", + "elbi", + "atu", + "parf", + "config", + "mhi"; + device_type = "pci"; + linux,pci-domain = <0>; + bus-range = <0x00 0xff>; + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x01000000 0x0 0x0 0x0 0x70200000 0x0 0x00100000>, + <0x02000000 0x0 0x0 0x0 0x70300000 0x0 0x0fd00000>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; + + interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "global"; + + clocks = <&gcc GCC_PCIE0_AXI_M_CLK>, + <&gcc GCC_PCIE0_AXI_S_CLK>, + <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>, + <&gcc GCC_PCIE0_RCHNG_CLK>, + <&gcc GCC_PCIE0_AHB_CLK>, + <&gcc GCC_PCIE0_AUX_CLK>; + clock-names = "axi_m", + "axi_s", + "axi_bridge", + "rchng", + "ahb", + "aux"; + + resets = <&gcc GCC_PCIE0_PIPE_ARES>, + <&gcc GCC_PCIE0_CORE_STICKY_RESET>, + <&gcc GCC_PCIE0_AXI_S_STICKY_RESET>, + <&gcc GCC_PCIE0_AXI_S_ARES>, + <&gcc GCC_PCIE0_AXI_M_STICKY_RESET>, + <&gcc GCC_PCIE0_AXI_M_ARES>, + <&gcc GCC_PCIE0_AUX_ARES>, + <&gcc GCC_PCIE0_AHB_ARES>; + reset-names = "pipe", + "sticky", + "axi_s_sticky", + "axi_s", + "axi_m_sticky", + "axi_m", + "aux", + "ahb"; + + interconnects = <&gcc MASTER_CNOC_PCIE0 &gcc SLAVE_CNOC_PCIE0>, + <&gcc MASTER_SNOC_PCIE0 &gcc SLAVE_SNOC_PCIE0>; + interconnect-names = "pcie-mem", "cpu-pcie"; + + status = "disabled"; + + pcie0_port0: pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + phys = <&pcie0_phy>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + }; + }; + + thermal_zones: thermal-zones { + ethphy-thermal { + thermal-sensors = <&tsens 11>; + + trips { + ethphy-critical { + temperature = <125000>; + hysteresis = <9000>; + type = "critical"; + }; + }; + }; + + pon-uniphy-thermal { + thermal-sensors = <&tsens 12>; + + trips { + pon-uniphy-critical { + temperature = <125000>; + hysteresis = <9000>; + type = "critical"; + }; + }; + }; + + nss-top-thermal { + thermal-sensors = <&tsens 13>; + + trips { + nss-top-critical { + temperature = <125000>; + hysteresis = <9000>; + type = "critical"; + }; + }; + }; + + cpu0-thermal { + thermal-sensors = <&tsens 14>; + + trips { + cpu-critical { + temperature = <120000>; + hysteresis = <9000>; + type = "critical"; + }; + + cpu0_thermal_alert: cpu-passive { + temperature = <110000>; + hysteresis = <9000>; + type = "passive"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu0_thermal_alert>; + /* Set maximum frequency as 816 MHz */ + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu1-thermal { + thermal-sensors = <&tsens 15>; + + trips { + cpu-critical { + temperature = <120000>; + hysteresis = <9000>; + type = "critical"; + }; + + cpu-passive { + temperature = <110000>; + hysteresis = <9000>; + type = "passive"; + }; + }; + }; }; timer { -- 2.34.1 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH v3 1/3] arm64: dts: qcom: ipq5210: Add nodes for multiple peripherals 2026-07-23 9:08 ` [PATCH v3 1/3] arm64: dts: qcom: ipq5210: Add nodes for multiple peripherals Varadarajan Narayanan @ 2026-07-23 9:26 ` sashiko-bot 0 siblings, 0 replies; 7+ messages in thread From: sashiko-bot @ 2026-07-23 9:26 UTC (permalink / raw) To: Varadarajan Narayanan; +Cc: conor+dt, robh, devicetree Thank you for your contribution! Sashiko AI review found 5 potential issue(s) to consider: - [High] Missing `#interconnect-cells` property in the `gcc` clock controller node. - [High] TSENS thermal sensor interrupt is incorrectly configured as edge-triggered. - [High] Missing fallback compatible string for `pcie0_phy`. - [Low] Missing `<dt-bindings/thermal/thermal.h>` include for `THERMAL_NO_LIMIT` macro. - [Low] Included interconnect bindings header file does not exist. -- --- Patch [1]: [PATCH v3 1/3] arm64: dts: qcom: ipq5210: Add nodes for multiple peripherals --- commit b50b502c781c4dc3d469ed6c9eaf41d79df96251 Author: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com> arm64: dts: qcom: ipq5210: Add nodes for multiple peripherals This commit describes common IPQ5210 SoC peripherals in the base DTSI so board DTS files can enable the hardware they use. It adds nodes for USB, PCIe, QPIC NAND/BAM, QFPROM, TSENS, and thermal zones, as well as the CPU OPP table and CPU cooling cells. > diff --git a/arch/arm64/boot/dts/qcom/ipq5210.dtsi b/arch/arm64/boot/dts/qcom/ipq5210.dtsi > index 2cdc10529c489..18e4a1dfa2682 100644 > --- a/arch/arm64/boot/dts/qcom/ipq5210.dtsi > +++ b/arch/arm64/boot/dts/qcom/ipq5210.dtsi > @@ -4,7 +4,9 @@ > */ > > #include <dt-bindings/interrupt-controller/arm-gic.h> > +#include <dt-bindings/clock/qcom,apss-ipq.h> > #include <dt-bindings/clock/qcom,ipq5210-gcc.h> > +#include <dt-bindings/interconnect/qcom,ipq5210.h> [Severity: Low] Does this dt-bindings interconnect header exist yet? Including a non-existent header will cause a preprocessor fatal error during the device tree build. [ ... ] > + pcie0_phy: phy@84000 { > + compatible = "qcom,ipq5210-qmp-gen3x1-pcie-phy"; [Severity: High] Is this missing a fallback compatible string? Unlike pcie1_phy and the USB PHYs in this patch, pcie0_phy only lists the new compatible string. Without a known fallback string, such as "qcom,ipq9574-qmp-gen3x1-pcie-phy", will the existing QMP PCIe PHY driver fail to bind and permanently break the PCIe0 subsystem? [ ... ] > + tsens: thermal-sensor@4a9000 { > + compatible = "qcom,ipq5210-tsens", "qcom,ipq5332-tsens"; > + reg = <0x0 0x004a9000 0x0 0x1000>, > + <0x0 0x004a8000 0x0 0x1000>; [ ... ] > + interrupts = <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>; > + interrupt-names = "combined"; [Severity: High] Should this TSENS interrupt be configured as level-sensitive instead of edge-triggered? TSENS hardware typically emits active-high level-sensitive interrupts for thermal thresholds. If configured as IRQ_TYPE_EDGE_RISING, a second thermal threshold crossed while the interrupt line is already asserted will not generate a new rising edge. This could cause the interrupt controller to miss the event, silently breaking thermal throttling and potentially causing hardware damage. [ ... ] > @@ -146,8 +358,8 @@ gcc: clock-controller@1800000 { > reg = <0x0 0x01800000 0x0 0x40000>; > clocks = <&xo_board>, > <&sleep_clk>, > - <0>, > - <0>, > + <&pcie0_phy>, > + <&pcie1_phy>, > <0>, > <0>; [Severity: High] Since the gcc node acts as an interconnect provider for the new pcie0 and pcie1 nodes, does it need an #interconnect-cells = <1>; property? Without the #interconnect-cells property in the provider node, calls to of_interconnect_get() from the PCIe drivers will fail with -EINVAL, causing driver probe failures for all consumers. [ ... ] > + cpu0-thermal { > + thermal-sensors = <&tsens 14>; [ ... ] > + cooling-maps { > + map0 { > + trip = <&cpu0_thermal_alert>; > + /* Set maximum frequency as 816 MHz */ > + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, [Severity: Low] Can this cause a syntax error during the device tree compilation? This line relies on THERMAL_NO_LIMIT being defined, but the required <dt-bindings/thermal/thermal.h> header was not included in this file. The C preprocessor will not expand the macro, leaving it as a string token, which causes a dtc syntax error when evaluating the integer expressions. -- Sashiko AI review · https://sashiko.dev/#/patchset/20260723-08-dts-v3-0-074eb131f382@oss.qualcomm.com?part=1 ^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v3 2/3] arm64: dts: qcom: ipq5210: Introduce RDP504 common DT file 2026-07-23 9:08 [PATCH v3 0/3] Enable mutliple peripherals in IPQ5210 Varadarajan Narayanan 2026-07-23 9:08 ` [PATCH v3 1/3] arm64: dts: qcom: ipq5210: Add nodes for multiple peripherals Varadarajan Narayanan @ 2026-07-23 9:08 ` Varadarajan Narayanan 2026-07-23 9:17 ` sashiko-bot 2026-07-23 9:08 ` [PATCH v3 3/3] arm64: dts: qcom: ipq5210: Introduce RDP504 variant specific " Varadarajan Narayanan 2 siblings, 1 reply; 7+ messages in thread From: Varadarajan Narayanan @ 2026-07-23 9:08 UTC (permalink / raw) To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley Cc: linux-arm-msm, devicetree, linux-kernel, Varadarajan Narayanan RDP504 has USB, PCIe and SPI NAND devices populated. EMMC and NAND share the GPIOs. The board has to be reworked to change from EMMC to NAND variant. Rename ipq5210-rdp504.dts as ipq5210-rdp504-common.dtsi and include it in variant specific DTS file. Describe the fixed USB regulators, PCIe reset GPIOs, QPIC SPI NAND flash and required pinctrl states. Enable QPIC BAM, USB and PCIe for the board. Signed-off-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com> --- .../arm64/boot/dts/qcom/ipq5210-rdp504-common.dtsi | 209 +++++++++++++++++++++ arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts | 79 -------- 2 files changed, 209 insertions(+), 79 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5210-rdp504-common.dtsi b/arch/arm64/boot/dts/qcom/ipq5210-rdp504-common.dtsi new file mode 100644 index 000000000000..30c8560822b5 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq5210-rdp504-common.dtsi @@ -0,0 +1,209 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include "ipq5210.dtsi" + +/ { + aliases { + serial0 = &uart1; + }; + + chosen { + stdout-path = "serial0"; + }; + + vreg_misc_3p3: regulator-usb-3p3 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-name = "usb_hs_vdda_3p3"; + }; + + vreg_misc_1p8: regulator-usb-1p8 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + regulator-name = "vdda_1p8_usb"; + }; + + vreg_misc_0p925: regulator-usb-0p925 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <925000>; + regulator-boot-on; + regulator-always-on; + regulator-name = "vdd_core_usb"; + }; +}; + +&pcie0 { + pinctrl-0 = <&pcie0_default_state>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie0_phy { + status = "okay"; +}; + +&pcie0_port0 { + reset-gpios = <&tlmm 32 GPIO_ACTIVE_LOW>; +}; + +&pcie1 { + pinctrl-0 = <&pcie1_default_state>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie1_phy { + status = "okay"; +}; + +&pcie1_port0 { + reset-gpios = <&tlmm 29 GPIO_ACTIVE_LOW>; +}; + +&qpic_bam { + status = "okay"; +}; + +&qpic_nand { + pinctrl-0 = <&qpic_snand_default_state>; + pinctrl-names = "default"; + + flash@0 { + compatible = "spi-nand"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + nand-ecc-engine = <&qpic_nand>; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + }; +}; + +&qusb_phy_0 { + vdd-supply = <&vreg_misc_0p925>; + vdda-pll-supply = <&vreg_misc_1p8>; + vdda-phy-dpdm-supply = <&vreg_misc_3p3>; + + status = "okay"; +}; + +&sdhc { + max-frequency = <192000000>; + bus-width = <4>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + pinctrl-0 = <&sdhc_default_state>; + pinctrl-names = "default"; +}; + +&sleep_clk { + clock-frequency = <32000>; +}; + +&ssphy_0 { + vdda-pll-supply = <&vreg_misc_1p8>; + vdda-phy-supply = <&vreg_misc_0p925>; + + status = "okay"; +}; + +&tlmm { + pcie1_default_state: pcie1-default-state { + pins = "gpio29"; + function = "gpio"; + drive-strength = <6>; + bias-pull-down; + }; + + pcie0_default_state: pcie0-default-state { + pins = "gpio32"; + function = "gpio"; + drive-strength = <6>; + bias-pull-down; + }; + + qpic_snand_default_state: qpic-snand-default-state { + data-pins { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + function = "qspi_data"; + drive-strength = <8>; + bias-disable; + }; + + cs-pins { + pins = "gpio4"; + function = "qspi_cs_n"; + drive-strength = <8>; + bias-disable; + }; + + clock-pins { + pins = "gpio5"; + function = "qspi_clk"; + drive-strength = <8>; + bias-disable; + }; + }; + + qup_uart1_default_state: qup-uart1-default-state { + pins = "gpio38", "gpio39"; + function = "qup_se1"; + drive-strength = <6>; + bias-pull-down; + }; + + sdhc_default_state: sdhc-default-state { + data-pins { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + function = "sdc_data"; + drive-strength = <8>; + bias-pull-up; + }; + + cmd-pins { + pins = "gpio4"; + function = "sdc_cmd"; + drive-strength = <8>; + bias-pull-up; + }; + + clk-pins { + pins = "gpio5"; + function = "sdc_clk"; + drive-strength = <8>; + bias-disable; + }; + }; +}; + +&uart1 { + pinctrl-0 = <&qup_uart1_default_state>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&usb3 { + dr_mode = "host"; + + status = "okay"; +}; + +&xo_board { + clock-frequency = <24000000>; +}; diff --git a/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts b/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts deleted file mode 100644 index 941f866ecfe9..000000000000 --- a/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts +++ /dev/null @@ -1,79 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - */ - -/dts-v1/; - -#include "ipq5210.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. IPQ5210 RDP504"; - compatible = "qcom,ipq5210-rdp504", "qcom,ipq5210"; - - aliases { - serial0 = &uart1; - }; - - chosen { - stdout-path = "serial0"; - }; -}; - -&sdhc { - max-frequency = <192000000>; - bus-width = <4>; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - pinctrl-0 = <&sdhc_default_state>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&sleep_clk { - clock-frequency = <32000>; -}; - -&tlmm { - qup_uart1_default_state: qup-uart1-default-state { - pins = "gpio38", "gpio39"; - function = "qup_se1"; - drive-strength = <6>; - bias-pull-down; - }; - - sdhc_default_state: sdhc-default-state { - clk-pins { - pins = "gpio5"; - function = "sdc_clk"; - drive-strength = <8>; - bias-disable; - }; - - cmd-pins { - pins = "gpio4"; - function = "sdc_cmd"; - drive-strength = <8>; - bias-pull-up; - }; - - data-pins { - pins = "gpio0", "gpio1", "gpio2", "gpio3"; - function = "sdc_data"; - drive-strength = <8>; - bias-pull-up; - }; - }; -}; - -&uart1 { - pinctrl-0 = <&qup_uart1_default_state>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&xo_board { - clock-frequency = <24000000>; -}; -- 2.34.1 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH v3 2/3] arm64: dts: qcom: ipq5210: Introduce RDP504 common DT file 2026-07-23 9:08 ` [PATCH v3 2/3] arm64: dts: qcom: ipq5210: Introduce RDP504 common DT file Varadarajan Narayanan @ 2026-07-23 9:17 ` sashiko-bot 0 siblings, 0 replies; 7+ messages in thread From: sashiko-bot @ 2026-07-23 9:17 UTC (permalink / raw) To: Varadarajan Narayanan; +Cc: robh, devicetree, conor+dt Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: - [Low] The commit deletes `ipq5210-rdp504.dts` without removing its corresponding build target from the Makefile or introducing the promised replacement variant DTS files, which breaks the build pipeline. -- --- Patch [2]: [PATCH v3 2/3] arm64: dts: qcom: ipq5210: Introduce RDP504 common DT file --- commit 99961f95ec5ae7b25b1fb15a9e2cd99c99fc0456 Author: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com> arm64: dts: qcom: ipq5210: Introduce RDP504 common DT file This commit renames the IPQ5210 RDP504 device tree file to a common .dtsi file to allow sharing configurations between EMMC and NAND variants. It also adds fixed USB regulators, PCIe reset GPIOs, and QPIC SPI NAND nodes. > RDP504 has USB, PCIe and SPI NAND devices populated. EMMC and NAND > share the GPIOs. The board has to be reworked to change from EMMC > to NAND variant. Rename ipq5210-rdp504.dts as ipq5210-rdp504-common.dtsi > and include it in variant specific DTS file. [Severity: Low] The commit message mentions including the new common file in variant-specific DTS files, but it looks like those new variant .dts files were omitted from this patch. Are they meant to be included here? [ ... ] > diff --git a/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts b/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts > deleted file mode 100644 > index 941f866ecfe95..0000000000000 > --- a/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts > +++ /dev/null [Severity: Low] Does deleting this file without removing its entry from the Makefile cause a build regression? Kbuild will likely fail with a missing target error because dtb-$(CONFIG_ARCH_QCOM) += ipq5210-rdp504.dtb appears to still be present in arch/arm64/boot/dts/qcom/Makefile. -- Sashiko AI review · https://sashiko.dev/#/patchset/20260723-08-dts-v3-0-074eb131f382@oss.qualcomm.com?part=2 ^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v3 3/3] arm64: dts: qcom: ipq5210: Introduce RDP504 variant specific DT file 2026-07-23 9:08 [PATCH v3 0/3] Enable mutliple peripherals in IPQ5210 Varadarajan Narayanan 2026-07-23 9:08 ` [PATCH v3 1/3] arm64: dts: qcom: ipq5210: Add nodes for multiple peripherals Varadarajan Narayanan 2026-07-23 9:08 ` [PATCH v3 2/3] arm64: dts: qcom: ipq5210: Introduce RDP504 common DT file Varadarajan Narayanan @ 2026-07-23 9:08 ` Varadarajan Narayanan 2026-07-23 9:16 ` sashiko-bot 2 siblings, 1 reply; 7+ messages in thread From: Varadarajan Narayanan @ 2026-07-23 9:08 UTC (permalink / raw) To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley Cc: linux-arm-msm, devicetree, linux-kernel, Varadarajan Narayanan Add two DT files, one for the default eMMC variant and one for the NAND variant. Signed-off-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com> --- arch/arm64/boot/dts/qcom/ipq5210-rdp504-nand.dts | 17 +++++++++++++++++ arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts | 17 +++++++++++++++++ 2 files changed, 34 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5210-rdp504-nand.dts b/arch/arm64/boot/dts/qcom/ipq5210-rdp504-nand.dts new file mode 100644 index 000000000000..0902681669b4 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq5210-rdp504-nand.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; + +#include "ipq5210-rdp504-common.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. IPQ5210 RDP504"; + compatible = "qcom,ipq5210-rdp504", "qcom,ipq5210"; +}; + +&qpic_nand { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts b/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts new file mode 100644 index 000000000000..cd65826944e3 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; + +#include "ipq5210-rdp504-common.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. IPQ5210 RDP504"; + compatible = "qcom,ipq5210-rdp504", "qcom,ipq5210"; +}; + +&sdhc { + status = "okay"; +}; -- 2.34.1 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH v3 3/3] arm64: dts: qcom: ipq5210: Introduce RDP504 variant specific DT file 2026-07-23 9:08 ` [PATCH v3 3/3] arm64: dts: qcom: ipq5210: Introduce RDP504 variant specific " Varadarajan Narayanan @ 2026-07-23 9:16 ` sashiko-bot 0 siblings, 0 replies; 7+ messages in thread From: sashiko-bot @ 2026-07-23 9:16 UTC (permalink / raw) To: Varadarajan Narayanan; +Cc: conor+dt, devicetree, robh Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider: - [Medium] The eMMC and NAND variants of the IPQ5210 RDP504 board use identical `model` and `compatible` strings, making them indistinguishable to the bootloader and userspace. - [Low] The newly added device tree file `ipq5210-rdp504-nand.dts` is missing from the subsystem `Makefile`, meaning it will not be compiled. -- --- Patch [3]: [PATCH v3 3/3] arm64: dts: qcom: ipq5210: Introduce RDP504 variant specific DT file --- commit 063e69c2f98cf6d7bdbb548ab9f8b5c63c82cda2 Author: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com> arm64: dts: qcom: ipq5210: Introduce RDP504 variant specific DT file Add two DT files, one for the default eMMC variant and one for the NAND variant. > diff --git a/arch/arm64/boot/dts/qcom/ipq5210-rdp504-nand.dts b/arch/arm64/boot/dts/qcom/ipq5210-rdp504-nand.dts > new file mode 100644 > index 0000000000000..0902681669b4b > --- /dev/null > +++ b/arch/arm64/boot/dts/qcom/ipq5210-rdp504-nand.dts [Severity: Low] Is a change to arch/arm64/boot/dts/qcom/Makefile missing from this patch? Without adding this file to the Makefile (e.g., dtb-$(CONFIG_ARCH_QCOM) += ipq5210-rdp504-nand.dtb), the build system will silently ignore it and fail to produce the DTB. > @@ -0,0 +1,17 @@ > +// SPDX-License-Identifier: BSD-3-Clause > +/* > + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. > + */ > + > +/dts-v1/; > + > +#include "ipq5210-rdp504-common.dtsi" > + > +/ { > + model = "Qualcomm Technologies, Inc. IPQ5210 RDP504"; > + compatible = "qcom,ipq5210-rdp504", "qcom,ipq5210"; [Severity: Medium] Both the NAND and eMMC variants use identical model and compatible strings. Will this make it impossible for a bootloader or userspace to dynamically distinguish between the two distinct hardware configurations? If a generic bootloader relies on the compatible or model strings to match hardware to a DTB, could this ambiguity cause the wrong DTB to be selected? [ ... ] > diff --git a/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts b/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts > new file mode 100644 > index 0000000000000..cd65826944e34 > --- /dev/null > +++ b/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts > @@ -0,0 +1,17 @@ > +// SPDX-License-Identifier: BSD-3-Clause > +/* > + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. > + */ > + > +/dts-v1/; > + > +#include "ipq5210-rdp504-common.dtsi" > + > +/ { > + model = "Qualcomm Technologies, Inc. IPQ5210 RDP504"; > + compatible = "qcom,ipq5210-rdp504", "qcom,ipq5210"; [Severity: Medium] Does this eMMC variant also need distinct model and compatible strings to safely differentiate it from the NAND variant above? -- Sashiko AI review · https://sashiko.dev/#/patchset/20260723-08-dts-v3-0-074eb131f382@oss.qualcomm.com?part=3 ^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2026-07-23 9:26 UTC | newest] Thread overview: 7+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2026-07-23 9:08 [PATCH v3 0/3] Enable mutliple peripherals in IPQ5210 Varadarajan Narayanan 2026-07-23 9:08 ` [PATCH v3 1/3] arm64: dts: qcom: ipq5210: Add nodes for multiple peripherals Varadarajan Narayanan 2026-07-23 9:26 ` sashiko-bot 2026-07-23 9:08 ` [PATCH v3 2/3] arm64: dts: qcom: ipq5210: Introduce RDP504 common DT file Varadarajan Narayanan 2026-07-23 9:17 ` sashiko-bot 2026-07-23 9:08 ` [PATCH v3 3/3] arm64: dts: qcom: ipq5210: Introduce RDP504 variant specific " Varadarajan Narayanan 2026-07-23 9:16 ` sashiko-bot
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox