[PATCH 0/4] spi: spacemit: support K3 SPI controllers

[PATCH 0/4] spi: spacemit: support K3 SPI controllers

[Zhengyu He]

This series adds K3 PDMA request numbers, documents the K3 SPI
compatible, and enables SPI0 on the K3 CoM260-IFX.

This series is available here:
  https://github.com/imguoguo/linux/tree/k3-com260-spi-v1

This series is based on v7.2-rc2.

Signed-off-by: Zhengyu He <hezhy472013@gmail.com>
---
Zhengyu He (3):
      spi: dt-bindings: spacemit: add K3 SPI compatible
      riscv: dts: spacemit: add SPI controllers for K3
      riscv: dts: spacemit: enable SPI0 on K3 CoM260-IFX

liyeshan (1):
      riscv: dts: spacemit: add K3 PDMA request numbers

 .../devicetree/bindings/spi/spacemit,k1-spi.yaml   |  6 +-
 arch/riscv/boot/dts/spacemit/k3-com260-ifx.dts     | 13 +++-
 arch/riscv/boot/dts/spacemit/k3-pdma.h             | 83 ++++++++++++++++++++++
 arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi       | 21 ++++++
 arch/riscv/boot/dts/spacemit/k3.dtsi               | 49 ++++++++++++-
 5 files changed, 169 insertions(+), 3 deletions(-)
---
base-commit: 8cdeaa50eae8dad34885515f62559ee83e7e8dda
change-id: 20260716-k3-com260-spi-v7-2-rc2-b4-preview-20260716-077f86d144f0

Best regards,
--  
Zhengyu He <hezhy472013@gmail.com>

[PATCH 1/4] riscv: dts: spacemit: add K3 PDMA request numbers

[Zhengyu He]

From: liyeshan <yeshan.li@spacemit.com>

Add a local DTS header that gives symbolic names to the SpacemiT K3
PDMA request lines of the non-secure peripherals. Device trees can use
these K3_PDMA_* macros instead of hard-coded request numbers when wiring
a peripheral "dmas" property.

Signed-off-by: liyeshan <yeshan.li@spacemit.com>
Signed-off-by: Guodong Xu <docular.xu@gmail.com>
Signed-off-by: Zhengyu He <hezhy472013@gmail.com>
---
 arch/riscv/boot/dts/spacemit/k3-pdma.h | 83 ++++++++++++++++++++++++++++++++++
 1 file changed, 83 insertions(+)

diff --git a/arch/riscv/boot/dts/spacemit/k3-pdma.h b/arch/riscv/boot/dts/spacemit/k3-pdma.h
new file mode 100644
index 000000000000..a5b723ad616a
--- /dev/null
+++ b/arch/riscv/boot/dts/spacemit/k3-pdma.h
@@ -0,0 +1,83 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * DMA request number (DRQ) definitions for non-secure peripherals of
+ * the SpacemiT K3 PDMA.
+ *
+ * Copyright (c) 2025 SpacemiT
+ * Copyright (c) 2026 Guodong Xu <docular.xu@gmail.com>
+ */
+
+#ifndef _DTS_SPACEMIT_K3_PDMA_H
+#define _DTS_SPACEMIT_K3_PDMA_H
+
+/* UART DMA request numbers */
+#define K3_PDMA_UART0_TX	3
+#define K3_PDMA_UART0_RX	4
+#define K3_PDMA_UART2_TX	5
+#define K3_PDMA_UART2_RX	6
+#define K3_PDMA_UART3_TX	7
+#define K3_PDMA_UART3_RX	8
+#define K3_PDMA_UART4_TX	9
+#define K3_PDMA_UART4_RX	10
+#define K3_PDMA_UART5_TX	25
+#define K3_PDMA_UART5_RX	26
+#define K3_PDMA_UART6_TX	27
+#define K3_PDMA_UART6_RX	28
+#define K3_PDMA_UART7_TX	29
+#define K3_PDMA_UART7_RX	30
+#define K3_PDMA_UART8_TX	31
+#define K3_PDMA_UART8_RX	32
+#define K3_PDMA_UART9_TX	33
+#define K3_PDMA_UART9_RX	34
+#define K3_PDMA_UART10_TX	53
+#define K3_PDMA_UART10_RX	54
+
+/* I2C DMA request numbers */
+#define K3_PDMA_I2C0_TX	11
+#define K3_PDMA_I2C0_RX	12
+#define K3_PDMA_I2C1_TX	13
+#define K3_PDMA_I2C1_RX	14
+#define K3_PDMA_I2C2_TX	15
+#define K3_PDMA_I2C2_RX	16
+#define K3_PDMA_I2C4_TX	17
+#define K3_PDMA_I2C4_RX	18
+#define K3_PDMA_I2C5_TX	35
+#define K3_PDMA_I2C5_RX	36
+#define K3_PDMA_I2C6_TX	37
+#define K3_PDMA_I2C6_RX	38
+#define K3_PDMA_I2C8_TX	41
+#define K3_PDMA_I2C8_RX	42
+
+/* SSP/SPI DMA request numbers */
+#define K3_PDMA_SSP3_TX	19
+#define K3_PDMA_SSP3_RX	20
+#define K3_PDMA_SSPA0_TX	21
+#define K3_PDMA_SSPA0_RX	22
+#define K3_PDMA_SSPA1_TX	23
+#define K3_PDMA_SSPA1_RX	24
+#define K3_PDMA_SSPA2_TX	56
+#define K3_PDMA_SSPA2_RX	57
+#define K3_PDMA_SSPA3_TX	58
+#define K3_PDMA_SSPA3_RX	59
+#define K3_PDMA_SSPA4_TX	60
+#define K3_PDMA_SSPA4_RX	61
+#define K3_PDMA_SSPA5_TX	62
+#define K3_PDMA_SSPA5_RX	63
+
+/* CAN DMA request numbers */
+#define K3_PDMA_CAN0_RX	43
+#define K3_PDMA_CAN1_RX	44
+#define K3_PDMA_CAN2_RX	51
+#define K3_PDMA_CAN3_RX	52
+
+/* SSP0/1 DMA request numbers */
+#define K3_PDMA_SSP0_TX	64
+#define K3_PDMA_SSP0_RX	65
+#define K3_PDMA_SSP1_TX	66
+#define K3_PDMA_SSP1_RX	67
+
+/* QSPI DMA request numbers */
+#define K3_PDMA_QSPI_RX	84
+#define K3_PDMA_QSPI_TX	85
+
+#endif /* _DTS_SPACEMIT_K3_PDMA_H */

-- 
2.53.0

[PATCH 2/4] spi: dt-bindings: spacemit: add K3 SPI compatible

[Zhengyu He]

The K3 SPI controller is compatible with K1, so allow K3 device trees to
use "spacemit,k1-spi" as fallback.

Signed-off-by: Cody Kang <cody.kang.hk@outlook.com>
Signed-off-by: Zhengyu He <hezhy472013@gmail.com>
---
 Documentation/devicetree/bindings/spi/spacemit,k1-spi.yaml | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/spi/spacemit,k1-spi.yaml b/Documentation/devicetree/bindings/spi/spacemit,k1-spi.yaml
index e82c7f8d0b98..5d86cc87e4fb 100644
--- a/Documentation/devicetree/bindings/spi/spacemit,k1-spi.yaml
+++ b/Documentation/devicetree/bindings/spi/spacemit,k1-spi.yaml
@@ -24,7 +24,11 @@ allOf:
 
 properties:
   compatible:
-    const: spacemit,k1-spi
+    oneOf:
+      - const: spacemit,k1-spi
+      - items:
+          - const: spacemit,k3-spi
+          - const: spacemit,k1-spi
 
   reg:
     maxItems: 1

-- 
2.53.0

[PATCH 3/4] riscv: dts: spacemit: add SPI controllers for K3

[Zhengyu He]

Add the SPI controller nodes for K3.

Signed-off-by: Cody Kang <cody.kang.hk@outlook.com>
Signed-off-by: Zhengyu He <hezhy472013@gmail.com>
---
 arch/riscv/boot/dts/spacemit/k3.dtsi | 49 +++++++++++++++++++++++++++++++++++-
 1 file changed, 48 insertions(+), 1 deletion(-)

diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi
index 19fc9b49668e..dc44b5c77d41 100644
--- a/arch/riscv/boot/dts/spacemit/k3.dtsi
+++ b/arch/riscv/boot/dts/spacemit/k3.dtsi
@@ -5,8 +5,10 @@
  */
 
 #include <dt-bindings/clock/spacemit,k3-clocks.h>
-#include <dt-bindings/reset/spacemit,k3-resets.h>
 #include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/reset/spacemit,k3-resets.h>
+
+#include "k3-pdma.h"
 
 /dts-v1/;
 
@@ -927,6 +929,21 @@ pwm7: pwm@d401bc00 {
 			status = "disabled";
 		};
 
+		spi3: spi@d401c000 {
+			compatible = "spacemit,k3-spi", "spacemit,k1-spi";
+			reg = <0x0 0xd401c000 0x0 0x30>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clocks = <&syscon_apbc CLK_APBC_SPI3>,
+				 <&syscon_apbc CLK_APBC_SPI3_BUS>;
+			clock-names = "core", "bus";
+			resets = <&syscon_apbc RESET_APBC_SPI3>;
+			interrupts = <55 IRQ_TYPE_LEVEL_HIGH>;
+			dmas = <&pdma K3_PDMA_SSP3_RX>, <&pdma K3_PDMA_SSP3_TX>;
+			dma-names = "rx", "tx";
+			status = "disabled";
+		};
+
 		pwm8: pwm@d4020000 {
 			compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm";
 			reg = <0x0 0xd4020000 0x0 0x10>;
@@ -1081,6 +1098,36 @@ uart10: serial@d401f000 {
 			status = "disabled";
 		};
 
+		spi0: spi@d4040000 {
+			compatible = "spacemit,k3-spi", "spacemit,k1-spi";
+			reg = <0x0 0xd4040000 0x0 0x30>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clocks = <&syscon_apbc CLK_APBC_SPI0>,
+				 <&syscon_apbc CLK_APBC_SPI0_BUS>;
+			clock-names = "core", "bus";
+			resets = <&syscon_apbc RESET_APBC_SPI0>;
+			interrupts = <283 IRQ_TYPE_LEVEL_HIGH>;
+			dmas = <&pdma K3_PDMA_SSP0_RX>, <&pdma K3_PDMA_SSP0_TX>;
+			dma-names = "rx", "tx";
+			status = "disabled";
+		};
+
+		spi1: spi@d4040800 {
+			compatible = "spacemit,k3-spi", "spacemit,k1-spi";
+			reg = <0x0 0xd4040800 0x0 0x30>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clocks = <&syscon_apbc CLK_APBC_SPI1>,
+				 <&syscon_apbc CLK_APBC_SPI1_BUS>;
+			clock-names = "core", "bus";
+			resets = <&syscon_apbc RESET_APBC_SPI1>;
+			interrupts = <282 IRQ_TYPE_LEVEL_HIGH>;
+			dmas = <&pdma K3_PDMA_SSP1_RX>, <&pdma K3_PDMA_SSP1_TX>;
+			dma-names = "rx", "tx";
+			status = "disabled";
+		};
+
 		syscon_mpmu: system-controller@d4050000 {
 			compatible = "spacemit,k3-syscon-mpmu";
 			reg = <0x0 0xd4050000 0x0 0x10000>;

-- 
2.53.0

[PATCH 4/4] riscv: dts: spacemit: enable SPI0 on K3 CoM260-IFX

[Zhengyu He]

SPI0 is the first enabled PDMA consumer on CoM260-IFX, so enable the
PDMA controller together with SPI0.

The board exposes SPI0 on its 40-pin header:

  pin 19: MOSI
  pin 21: MISO
  pin 23: SCLK
  pin 24: CS0

Define the pinctrl state used by this header wiring, and describe the SPI
NOR on chip select 0 for the current validation setup.

(This was tested using a Winbond W25Q64JV SPI NOR chip.)

Signed-off-by: Cody Kang <cody.kang.hk@outlook.com>
Signed-off-by: Zhengyu He <hezhy472013@gmail.com>
---
 arch/riscv/boot/dts/spacemit/k3-com260-ifx.dts | 13 ++++++++++++-
 arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi   | 21 +++++++++++++++++++++
 2 files changed, 33 insertions(+), 1 deletion(-)

diff --git a/arch/riscv/boot/dts/spacemit/k3-com260-ifx.dts b/arch/riscv/boot/dts/spacemit/k3-com260-ifx.dts
index 238bb03d0e9e..01a7135df864 100644
--- a/arch/riscv/boot/dts/spacemit/k3-com260-ifx.dts
+++ b/arch/riscv/boot/dts/spacemit/k3-com260-ifx.dts
@@ -11,11 +11,22 @@ / {
 	compatible = "spacemit,k3-com260-ifx", "spacemit,k3-com260", "spacemit,k3";
 
 	aliases {
-		serial0 = &uart0;
 		ethernet0 = &eth1;
+		serial0 = &uart0;
+		spi0 = &spi0;
 	};
 
 	chosen {
 		stdout-path = "serial0:115200n8";
 	};
 };
+
+&pdma {
+	status = "okay";
+};
+
+&spi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&ssp0_2_cfg>;
+	status = "okay";
+};
diff --git a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi
index 3ee1471f3798..9b7617f3846c 100644
--- a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi
+++ b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi
@@ -679,6 +679,27 @@ pwm19-2-pins {
 		};
 	};
 
+	/omit-if-no-ref/
+	ssp0_2_cfg: ssp0-2-cfg {
+		ssp0-0-pins {
+			pinmux = <K3_PADCONF(104, 1)>,  /* ssp0 tx */
+				 <K3_PADCONF(105, 1)>,  /* ssp0 rx */
+				 <K3_PADCONF(106, 1)>;  /* ssp0 clk */
+
+			bias-disable;
+			drive-strength = <25>;
+			power-source = <1800>;
+		};
+
+		ssp0-1-pins {
+			pinmux = <K3_PADCONF(107, 1)>;  /* ssp0 frm */
+
+			bias-pull-up = <0>;
+			drive-strength = <25>;
+			power-source = <1800>;
+		};
+	};
+
 	/omit-if-no-ref/
 	uart0_0_cfg: uart0-0-cfg {
 		uart0-0-pins {

-- 
2.53.0

Re: [PATCH 4/4] riscv: dts: spacemit: enable SPI0 on K3 CoM260-IFX

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Medium] The commit message claims to describe a SPI NOR flash chip on chip select 0, but the corresponding device tree node is absent.
- [Medium] The pinctrl configuration sets the SPI pad voltage to 1.8V, which conflicts with the 3.3V Winbond W25Q64JV SPI NOR flash mentioned in the commit message.
--

--- Patch [4]: [PATCH 4/4] riscv: dts: spacemit: enable SPI0 on K3 CoM260-IFX ---
commit 195bf5fbf14f1dbf36d3f0697603287770b0c9db
Author: Zhengyu He <hezhy472013@gmail.com>

riscv: dts: spacemit: enable SPI0 on K3 CoM260-IFX

This commit enables the PDMA controller and SPI0 on the K3 CoM260-IFX board.
It also adds the pinctrl states for the SPI0 pins exposed on the board's 40-pin
header.

> diff --git a/arch/riscv/boot/dts/spacemit/k3-com260-ifx.dts b/arch/riscv/boot/dts/spacemit/k3-com260-ifx.dts
> --- a/arch/riscv/boot/dts/spacemit/k3-com260-ifx.dts
> +++ b/arch/riscv/boot/dts/spacemit/k3-com260-ifx.dts
[ ... ]
> +&spi0 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&ssp0_2_cfg>;
> +	status = "okay";
> +};

[Severity: Medium]
The commit message states this patch will "describe the SPI NOR on chip select
0 for the current validation setup", but is the child node for the flash chip
missing here?

> diff --git a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi
> --- a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi
> +++ b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi
[ ... ]
> +	/omit-if-no-ref/
> +	ssp0_2_cfg: ssp0-2-cfg {
> +		ssp0-0-pins {
> +			pinmux = <K3_PADCONF(104, 1)>,  /* ssp0 tx */
> +				 <K3_PADCONF(105, 1)>,  /* ssp0 rx */
> +				 <K3_PADCONF(106, 1)>;  /* ssp0 clk */
> +
> +			bias-disable;
> +			drive-strength = <25>;
> +			power-source = <1800>;

[Severity: Medium]
Does this 1.8V power source configuration match the validation setup described
in the commit message?

The commit message mentions testing with a Winbond W25Q64JV, which is a 3.3V
component (the 1.8V equivalent is the W25Q64JW). If the SoC IO is driving
1.8V signals without a level shifter, it might fail to meet the 3.3V chip's
input high voltage thresholds. Could this be a typo in the commit message, or
is the power-source value incorrect for this board?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260717-k3-com260-spi-v7-2-rc2-b4-preview-20260716-v1-0-969a1b0f783f@gmail.com?part=4

Re: (subset) [PATCH 0/4] spi: spacemit: support K3 SPI controllers

[Mark Brown]

On Fri, 17 Jul 2026 07:45:24 -0700, Zhengyu He wrote:
> spi: spacemit: support K3 SPI controllers
> 
> This series adds K3 PDMA request numbers, documents the K3 SPI
> compatible, and enables SPI0 on the K3 CoM260-IFX.
> 
> This series is available here:
>   https://github.com/imguoguo/linux/tree/k3-com260-spi-v1
> 
> [...]

Applied to

   https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-7.2

Thanks!

[2/4] spi: dt-bindings: spacemit: add K3 SPI compatible
      https://git.kernel.org/broonie/spi/c/6389eaf11d6c

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark

Re: [PATCH 4/4] riscv: dts: spacemit: enable SPI0 on K3 CoM260-IFX

[Yixun Lan]

Hi Zhengyu,


On 07:45 Fri 17 Jul     , Zhengyu He wrote:
> SPI0 is the first enabled PDMA consumer on CoM260-IFX, so enable the
> PDMA controller together with SPI0.
> 
> The board exposes SPI0 on its 40-pin header:
> 
>   pin 19: MOSI
>   pin 21: MISO
>   pin 23: SCLK
>   pin 24: CS0
> 
> Define the pinctrl state used by this header wiring, and describe the SPI
> NOR on chip select 0 for the current validation setup.
> 
> (This was tested using a Winbond W25Q64JV SPI NOR chip.)
> 
It's fine to test spi controller with an external attached NOR flash,
but doesn't make sense to enable it permanently in board dts level.

I think it's probably better to provide as an independent dtso file,
which more flexible to let user decide to enable it or not..

Anyway, I will leave out this patch for further discussion, and
only pick patch 1 & 3 for now, thanks

> Signed-off-by: Cody Kang <cody.kang.hk@outlook.com>
> Signed-off-by: Zhengyu He <hezhy472013@gmail.com>
> ---
>  arch/riscv/boot/dts/spacemit/k3-com260-ifx.dts | 13 ++++++++++++-
>  arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi   | 21 +++++++++++++++++++++
>  2 files changed, 33 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/riscv/boot/dts/spacemit/k3-com260-ifx.dts b/arch/riscv/boot/dts/spacemit/k3-com260-ifx.dts
> index 238bb03d0e9e..01a7135df864 100644
> --- a/arch/riscv/boot/dts/spacemit/k3-com260-ifx.dts
> +++ b/arch/riscv/boot/dts/spacemit/k3-com260-ifx.dts
> @@ -11,11 +11,22 @@ / {
>  	compatible = "spacemit,k3-com260-ifx", "spacemit,k3-com260", "spacemit,k3";
>  
>  	aliases {
> -		serial0 = &uart0;
>  		ethernet0 = &eth1;
> +		serial0 = &uart0;
> +		spi0 = &spi0;
>  	};
>  
>  	chosen {
>  		stdout-path = "serial0:115200n8";
>  	};
>  };
> +
> +&pdma {
> +	status = "okay";
> +};
> +
> +&spi0 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&ssp0_2_cfg>;
> +	status = "okay";
> +};

..
> diff --git a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi
> index 3ee1471f3798..9b7617f3846c 100644
> --- a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi
> +++ b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi
> @@ -679,6 +679,27 @@ pwm19-2-pins {
>  		};
>  	};
>  
> +	/omit-if-no-ref/
> +	ssp0_2_cfg: ssp0-2-cfg {
> +		ssp0-0-pins {
> +			pinmux = <K3_PADCONF(104, 1)>,  /* ssp0 tx */
> +				 <K3_PADCONF(105, 1)>,  /* ssp0 rx */
> +				 <K3_PADCONF(106, 1)>;  /* ssp0 clk */
> +
> +			bias-disable;
> +			drive-strength = <25>;
> +			power-source = <1800>;
> +		};
> +
> +		ssp0-1-pins {
> +			pinmux = <K3_PADCONF(107, 1)>;  /* ssp0 frm */
> +
> +			bias-pull-up = <0>;
> +			drive-strength = <25>;
> +			power-source = <1800>;
> +		};
> +	};
> +
If you can put spi pinctrl data as a separate patch, then I'd be happy
to include, just be sure to list all spi controller pinctrl info

>  	/omit-if-no-ref/
>  	uart0_0_cfg: uart0-0-cfg {
>  		uart0-0-pins {
> 
> -- 
> 2.53.0
> 

-- 
Yixun Lan (dlan)

Re: [PATCH 3/4] riscv: dts: spacemit: add SPI controllers for K3

[Yixun Lan]

On 07:45 Fri 17 Jul     , Zhengyu He wrote:
> Add the SPI controller nodes for K3.
> 
> Signed-off-by: Cody Kang <cody.kang.hk@outlook.com>
> Signed-off-by: Zhengyu He <hezhy472013@gmail.com>

Reviewed-by: Yixun Lan <dlan@kernel.org>

> ---
>  arch/riscv/boot/dts/spacemit/k3.dtsi | 49 +++++++++++++++++++++++++++++++++++-
>  1 file changed, 48 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi
> index 19fc9b49668e..dc44b5c77d41 100644
> --- a/arch/riscv/boot/dts/spacemit/k3.dtsi
> +++ b/arch/riscv/boot/dts/spacemit/k3.dtsi
> @@ -5,8 +5,10 @@
>   */
>  
>  #include <dt-bindings/clock/spacemit,k3-clocks.h>
> -#include <dt-bindings/reset/spacemit,k3-resets.h>
>  #include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/reset/spacemit,k3-resets.h>
> +
> +#include "k3-pdma.h"
>  
>  /dts-v1/;
>  
> @@ -927,6 +929,21 @@ pwm7: pwm@d401bc00 {
>  			status = "disabled";
>  		};
>  
> +		spi3: spi@d401c000 {
> +			compatible = "spacemit,k3-spi", "spacemit,k1-spi";
> +			reg = <0x0 0xd401c000 0x0 0x30>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			clocks = <&syscon_apbc CLK_APBC_SPI3>,
> +				 <&syscon_apbc CLK_APBC_SPI3_BUS>;
> +			clock-names = "core", "bus";
> +			resets = <&syscon_apbc RESET_APBC_SPI3>;
> +			interrupts = <55 IRQ_TYPE_LEVEL_HIGH>;
> +			dmas = <&pdma K3_PDMA_SSP3_RX>, <&pdma K3_PDMA_SSP3_TX>;
> +			dma-names = "rx", "tx";
> +			status = "disabled";
> +		};
> +
>  		pwm8: pwm@d4020000 {
>  			compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm";
>  			reg = <0x0 0xd4020000 0x0 0x10>;
> @@ -1081,6 +1098,36 @@ uart10: serial@d401f000 {
>  			status = "disabled";
>  		};
>  
> +		spi0: spi@d4040000 {
> +			compatible = "spacemit,k3-spi", "spacemit,k1-spi";
> +			reg = <0x0 0xd4040000 0x0 0x30>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			clocks = <&syscon_apbc CLK_APBC_SPI0>,
> +				 <&syscon_apbc CLK_APBC_SPI0_BUS>;
> +			clock-names = "core", "bus";
> +			resets = <&syscon_apbc RESET_APBC_SPI0>;
> +			interrupts = <283 IRQ_TYPE_LEVEL_HIGH>;
> +			dmas = <&pdma K3_PDMA_SSP0_RX>, <&pdma K3_PDMA_SSP0_TX>;
> +			dma-names = "rx", "tx";
> +			status = "disabled";
> +		};
> +
> +		spi1: spi@d4040800 {
> +			compatible = "spacemit,k3-spi", "spacemit,k1-spi";
> +			reg = <0x0 0xd4040800 0x0 0x30>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			clocks = <&syscon_apbc CLK_APBC_SPI1>,
> +				 <&syscon_apbc CLK_APBC_SPI1_BUS>;
> +			clock-names = "core", "bus";
> +			resets = <&syscon_apbc RESET_APBC_SPI1>;
> +			interrupts = <282 IRQ_TYPE_LEVEL_HIGH>;
> +			dmas = <&pdma K3_PDMA_SSP1_RX>, <&pdma K3_PDMA_SSP1_TX>;
> +			dma-names = "rx", "tx";
> +			status = "disabled";
> +		};
> +
>  		syscon_mpmu: system-controller@d4050000 {
>  			compatible = "spacemit,k3-syscon-mpmu";
>  			reg = <0x0 0xd4050000 0x0 0x10000>;
> 
> -- 
> 2.53.0
> 

-- 
Yixun Lan (dlan)

Re: [PATCH 1/4] riscv: dts: spacemit: add K3 PDMA request numbers

[Yixun Lan]

Hi Zhengyu,

On 07:45 Fri 17 Jul     , Zhengyu He wrote:
> From: liyeshan <yeshan.li@spacemit.com>
> 
> Add a local DTS header that gives symbolic names to the SpacemiT K3
> PDMA request lines of the non-secure peripherals. Device trees can use
> these K3_PDMA_* macros instead of hard-coded request numbers when wiring
> a peripheral "dmas" property.
> 
> Signed-off-by: liyeshan <yeshan.li@spacemit.com>
> Signed-off-by: Guodong Xu <docular.xu@gmail.com>
> Signed-off-by: Zhengyu He <hezhy472013@gmail.com>

Reviewed-by: Yixun Lan <dlan@kernel.org>

> ---
>  arch/riscv/boot/dts/spacemit/k3-pdma.h | 83 ++++++++++++++++++++++++++++++++++
>  1 file changed, 83 insertions(+)
> 
> diff --git a/arch/riscv/boot/dts/spacemit/k3-pdma.h b/arch/riscv/boot/dts/spacemit/k3-pdma.h
> new file mode 100644
> index 000000000000..a5b723ad616a
> --- /dev/null
> +++ b/arch/riscv/boot/dts/spacemit/k3-pdma.h
> @@ -0,0 +1,83 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
> +/*
> + * DMA request number (DRQ) definitions for non-secure peripherals of
> + * the SpacemiT K3 PDMA.
> + *
> + * Copyright (c) 2025 SpacemiT
> + * Copyright (c) 2026 Guodong Xu <docular.xu@gmail.com>
> + */
> +
> +#ifndef _DTS_SPACEMIT_K3_PDMA_H
> +#define _DTS_SPACEMIT_K3_PDMA_H
> +
> +/* UART DMA request numbers */
> +#define K3_PDMA_UART0_TX	3
> +#define K3_PDMA_UART0_RX	4
> +#define K3_PDMA_UART2_TX	5
> +#define K3_PDMA_UART2_RX	6
> +#define K3_PDMA_UART3_TX	7
> +#define K3_PDMA_UART3_RX	8
> +#define K3_PDMA_UART4_TX	9
> +#define K3_PDMA_UART4_RX	10
> +#define K3_PDMA_UART5_TX	25
> +#define K3_PDMA_UART5_RX	26
> +#define K3_PDMA_UART6_TX	27
> +#define K3_PDMA_UART6_RX	28
> +#define K3_PDMA_UART7_TX	29
> +#define K3_PDMA_UART7_RX	30
> +#define K3_PDMA_UART8_TX	31
> +#define K3_PDMA_UART8_RX	32
> +#define K3_PDMA_UART9_TX	33
> +#define K3_PDMA_UART9_RX	34
> +#define K3_PDMA_UART10_TX	53
> +#define K3_PDMA_UART10_RX	54
> +
> +/* I2C DMA request numbers */
> +#define K3_PDMA_I2C0_TX	11
> +#define K3_PDMA_I2C0_RX	12
> +#define K3_PDMA_I2C1_TX	13
> +#define K3_PDMA_I2C1_RX	14
> +#define K3_PDMA_I2C2_TX	15
> +#define K3_PDMA_I2C2_RX	16
> +#define K3_PDMA_I2C4_TX	17
> +#define K3_PDMA_I2C4_RX	18
> +#define K3_PDMA_I2C5_TX	35
> +#define K3_PDMA_I2C5_RX	36
> +#define K3_PDMA_I2C6_TX	37
> +#define K3_PDMA_I2C6_RX	38
> +#define K3_PDMA_I2C8_TX	41
> +#define K3_PDMA_I2C8_RX	42
> +
> +/* SSP/SPI DMA request numbers */
> +#define K3_PDMA_SSP3_TX	19
> +#define K3_PDMA_SSP3_RX	20
> +#define K3_PDMA_SSPA0_TX	21
> +#define K3_PDMA_SSPA0_RX	22
> +#define K3_PDMA_SSPA1_TX	23
> +#define K3_PDMA_SSPA1_RX	24
> +#define K3_PDMA_SSPA2_TX	56
> +#define K3_PDMA_SSPA2_RX	57
> +#define K3_PDMA_SSPA3_TX	58
> +#define K3_PDMA_SSPA3_RX	59
> +#define K3_PDMA_SSPA4_TX	60
> +#define K3_PDMA_SSPA4_RX	61
> +#define K3_PDMA_SSPA5_TX	62
> +#define K3_PDMA_SSPA5_RX	63
> +
> +/* CAN DMA request numbers */
> +#define K3_PDMA_CAN0_RX	43
> +#define K3_PDMA_CAN1_RX	44
> +#define K3_PDMA_CAN2_RX	51
> +#define K3_PDMA_CAN3_RX	52
> +
> +/* SSP0/1 DMA request numbers */
> +#define K3_PDMA_SSP0_TX	64
> +#define K3_PDMA_SSP0_RX	65
> +#define K3_PDMA_SSP1_TX	66
> +#define K3_PDMA_SSP1_RX	67
> +
> +/* QSPI DMA request numbers */
> +#define K3_PDMA_QSPI_RX	84
> +#define K3_PDMA_QSPI_TX	85
> +
> +#endif /* _DTS_SPACEMIT_K3_PDMA_H */
> 
> -- 
> 2.53.0
> 

-- 
Yixun Lan (dlan)