* [PATCH v7 1/3] drm/bridge: ti-sn65dsi83: Simplify error condition logic
2026-07-28 12:20 [PATCH v7 0/3] drm/bridge: ti-sn65dsi83: Add reverse lvds lanes support Wojciech Dubowik
@ 2026-07-28 12:20 ` Wojciech Dubowik
2026-07-28 12:20 ` [PATCH v7 2/3] dt-bindings: display: sn65dsi83: Add output data-lanes property Wojciech Dubowik
2026-07-28 12:20 ` [PATCH v7 3/3] drm/bridge: ti-sn65dsi83: Add reversed lvds lanes support Wojciech Dubowik
2 siblings, 0 replies; 5+ messages in thread
From: Wojciech Dubowik @ 2026-07-28 12:20 UTC (permalink / raw)
To: linux-kernel
Cc: Wojciech Dubowik, Andrzej Hajda, Neil Armstrong, Robert Foss,
Laurent Pinchart, Jonas Karlman, Jernej Skrabec, Luca Ceresoli,
David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Marek Vasut, dri-devel, devicetree
From: Wojciech Dubowik <Wojciech.Dubowik@mt.com>
Simplify error condition logic in lvds device tree property parsing. It
makes it easier to add extra properties without handling complex goto
entries.
Reviewed-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
Tested-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
Signed-off-by: Wojciech Dubowik <Wojciech.Dubowik@mt.com>
---
drivers/gpu/drm/bridge/ti-sn65dsi83.c | 43 ++++++++-------------------
1 file changed, 13 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi83.c b/drivers/gpu/drm/bridge/ti-sn65dsi83.c
index 42b451432bbb..f8a786953526 100644
--- a/drivers/gpu/drm/bridge/ti-sn65dsi83.c
+++ b/drivers/gpu/drm/bridge/ti-sn65dsi83.c
@@ -825,48 +825,35 @@ static int sn65dsi83_select_lvds_vod_swing(struct device *dev,
static int sn65dsi83_parse_lvds_endpoint(struct sn65dsi83 *ctx, int channel)
{
struct device *dev = ctx->dev;
- struct device_node *endpoint;
- int endpoint_reg;
+ int endpoint_reg = (channel == CHANNEL_A) ? 2 : 3;
+ struct device_node *endpoint __free(device_node) =
+ of_graph_get_endpoint_by_regs(dev->of_node, endpoint_reg, -1);
/* Set so the property can be freely selected if not defined */
u32 lvds_vod_swing_data[2] = { 0, 1000000 };
u32 lvds_vod_swing_clk[2] = { 0, 1000000 };
/* Set default near end terminataion to 200 Ohm */
u32 lvds_term = 200;
int lvds_vod_swing_conf;
- int ret = 0;
int ret_data;
int ret_clock;
- if (channel == CHANNEL_A)
- endpoint_reg = 2;
- else
- endpoint_reg = 3;
-
- endpoint = of_graph_get_endpoint_by_regs(dev->of_node, endpoint_reg, -1);
-
of_property_read_u32(endpoint, "ti,lvds-termination-ohms", &lvds_term);
if (lvds_term == 100)
ctx->lvds_term_conf[channel] = OHM_100;
else if (lvds_term == 200)
ctx->lvds_term_conf[channel] = OHM_200;
- else {
- ret = -EINVAL;
- goto exit;
- }
+ else
+ return -EINVAL;
ret_data = of_property_read_u32_array(endpoint, "ti,lvds-vod-swing-data-microvolt",
lvds_vod_swing_data, ARRAY_SIZE(lvds_vod_swing_data));
- if (ret_data != 0 && ret_data != -EINVAL) {
- ret = ret_data;
- goto exit;
- }
+ if (ret_data != 0 && ret_data != -EINVAL)
+ return ret_data;
ret_clock = of_property_read_u32_array(endpoint, "ti,lvds-vod-swing-clock-microvolt",
lvds_vod_swing_clk, ARRAY_SIZE(lvds_vod_swing_clk));
- if (ret_clock != 0 && ret_clock != -EINVAL) {
- ret = ret_clock;
- goto exit;
- }
+ if (ret_clock != 0 && ret_clock != -EINVAL)
+ return ret_clock;
/* Use default value if both properties are NOT defined. */
if (ret_data == -EINVAL && ret_clock == -EINVAL)
@@ -876,17 +863,13 @@ static int sn65dsi83_parse_lvds_endpoint(struct sn65dsi83 *ctx, int channel)
if (!ret_data || !ret_clock) {
lvds_vod_swing_conf = sn65dsi83_select_lvds_vod_swing(dev, lvds_vod_swing_data,
lvds_vod_swing_clk, ctx->lvds_term_conf[channel]);
- if (lvds_vod_swing_conf < 0) {
- ret = lvds_vod_swing_conf;
- goto exit;
- }
+ if (lvds_vod_swing_conf < 0)
+ return lvds_vod_swing_conf;
}
ctx->lvds_vod_swing_conf[channel] = lvds_vod_swing_conf;
- ret = 0;
-exit:
- of_node_put(endpoint);
- return ret;
+
+ return 0;
}
static int sn65dsi83_parse_dt(struct sn65dsi83 *ctx, enum sn65dsi83_model model)
--
2.47.3
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH v7 2/3] dt-bindings: display: sn65dsi83: Add output data-lanes property
2026-07-28 12:20 [PATCH v7 0/3] drm/bridge: ti-sn65dsi83: Add reverse lvds lanes support Wojciech Dubowik
2026-07-28 12:20 ` [PATCH v7 1/3] drm/bridge: ti-sn65dsi83: Simplify error condition logic Wojciech Dubowik
@ 2026-07-28 12:20 ` Wojciech Dubowik
2026-07-28 12:29 ` sashiko-bot
2026-07-28 12:20 ` [PATCH v7 3/3] drm/bridge: ti-sn65dsi83: Add reversed lvds lanes support Wojciech Dubowik
2 siblings, 1 reply; 5+ messages in thread
From: Wojciech Dubowik @ 2026-07-28 12:20 UTC (permalink / raw)
To: linux-kernel
Cc: Wojciech Dubowik, Andrzej Hajda, Neil Armstrong, Robert Foss,
Laurent Pinchart, Jonas Karlman, Jernej Skrabec, Luca Ceresoli,
David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Marek Vasut, dri-devel, devicetree
From: Wojciech Dubowik <Wojciech.Dubowik@mt.com>
Add an optional output lvds data lanes property with two allowed values
for default and reversed layout.
Signed-off-by: Wojciech Dubowik <Wojciech.Dubowik@mt.com>
---
.../bindings/display/bridge/ti,sn65dsi83.yaml | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi83.yaml b/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi83.yaml
index e69b6343a8eb..0eb3913acc9d 100644
--- a/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi83.yaml
+++ b/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi83.yaml
@@ -125,6 +125,21 @@ $defs:
lanes in microvolts.
maxItems: 2
+ data-lanes:
+ description:
+ Array of physical LVDS data lane indexes
+ oneOf:
+ - items:
+ - const: 1
+ - const: 2
+ - const: 3
+ - const: 4
+ - items:
+ - const: 4
+ - const: 3
+ - const: 2
+ - const: 1
+
allOf:
- if:
properties:
--
2.47.3
^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PATCH v7 2/3] dt-bindings: display: sn65dsi83: Add output data-lanes property
2026-07-28 12:20 ` [PATCH v7 2/3] dt-bindings: display: sn65dsi83: Add output data-lanes property Wojciech Dubowik
@ 2026-07-28 12:29 ` sashiko-bot
0 siblings, 0 replies; 5+ messages in thread
From: sashiko-bot @ 2026-07-28 12:29 UTC (permalink / raw)
To: Wojciech Dubowik; +Cc: devicetree, conor+dt, dri-devel, robh
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The `data-lanes` property requires exactly 4 items, breaking support for 18-bit (3-lane) LVDS configurations.
--
--- Patch [2]: [PATCH v7 2/3] dt-bindings: display: sn65dsi83: Add output data-lanes property ---
commit 9dc2b5a1e0c25c9fb7936d93599a48a919079b3b
Author: Wojciech Dubowik <Wojciech.Dubowik@mt.com>
dt-bindings: display: sn65dsi83: Add output data-lanes property
Add an optional output lvds data lanes property with two allowed values
for default and reversed layout.
> diff --git a/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi83.yaml b/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi83.yaml
> index e69b6343a8ebb..0eb3913acc9d4 100644
> --- a/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi83.yaml
> +++ b/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi83.yaml
> @@ -125,6 +125,21 @@ $defs:
> lanes in microvolts.
> maxItems: 2
>
> + data-lanes:
> + description:
> + Array of physical LVDS data lane indexes
> + oneOf:
> + - items:
> + - const: 1
> + - const: 2
> + - const: 3
> + - const: 4
> + - items:
> + - const: 4
> + - const: 3
> + - const: 2
> + - const: 1
[Severity: Medium]
Will this strict 4-item constraint break validation for 18-bit (3-lane) LVDS
configurations?
In dt-schema, specifying an items list automatically implies minItems equal to
the length of the list unless explicitly overridden. Without a minItems setting
defined here, the schema will reject arrays shorter than 4 elements, such as
data-lanes = <1 2 3> or <4 3 2>.
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260728122032.692482-1-wojciech.dubowik@mt.com?part=2
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v7 3/3] drm/bridge: ti-sn65dsi83: Add reversed lvds lanes support
2026-07-28 12:20 [PATCH v7 0/3] drm/bridge: ti-sn65dsi83: Add reverse lvds lanes support Wojciech Dubowik
2026-07-28 12:20 ` [PATCH v7 1/3] drm/bridge: ti-sn65dsi83: Simplify error condition logic Wojciech Dubowik
2026-07-28 12:20 ` [PATCH v7 2/3] dt-bindings: display: sn65dsi83: Add output data-lanes property Wojciech Dubowik
@ 2026-07-28 12:20 ` Wojciech Dubowik
2 siblings, 0 replies; 5+ messages in thread
From: Wojciech Dubowik @ 2026-07-28 12:20 UTC (permalink / raw)
To: linux-kernel
Cc: Wojciech Dubowik, Andrzej Hajda, Neil Armstrong, Robert Foss,
Laurent Pinchart, Jonas Karlman, Jernej Skrabec, Luca Ceresoli,
David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Marek Vasut, dri-devel, devicetree
From: Wojciech Dubowik <Wojciech.Dubowik@mt.com>
The chip supports output lvds lanes in two orders, the default <1 2 3 4>
and <4 3 2 1>. Add parsing of an optional output lvds data-lanes property
so we can inform chip that the lanes have been reversed.
Reviewed-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
Signed-off-by: Wojciech Dubowik <Wojciech.Dubowik@mt.com>
---
drivers/gpu/drm/bridge/ti-sn65dsi83.c | 31 +++++++++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi83.c b/drivers/gpu/drm/bridge/ti-sn65dsi83.c
index f8a786953526..182e58a0ed41 100644
--- a/drivers/gpu/drm/bridge/ti-sn65dsi83.c
+++ b/drivers/gpu/drm/bridge/ti-sn65dsi83.c
@@ -148,6 +148,18 @@ enum sn65dsi83_lvds_term {
OHM_200
};
+enum {
+ LANE_MAPPING_NORMAL,
+ LANE_MAPPING_REVERSE,
+};
+
+#define DATA_LANES_COUNT 4
+
+static const u32 supported_data_lane_mapping[][DATA_LANES_COUNT] = {
+ [LANE_MAPPING_NORMAL] = { 1, 2, 3, 4 },
+ [LANE_MAPPING_REVERSE] = { 4, 3, 2, 1},
+};
+
enum sn65dsi83_model {
MODEL_SN65DSI83,
MODEL_SN65DSI84,
@@ -163,6 +175,7 @@ struct sn65dsi83 {
struct regulator *vcc;
bool lvds_dual_link;
bool lvds_dual_link_even_odd_swap;
+ bool lvds_reverse_lanes_conf[2];
int lvds_vod_swing_conf[2];
int lvds_term_conf[2];
int irq;
@@ -644,6 +657,10 @@ static void sn65dsi83_atomic_pre_enable(struct drm_bridge *bridge,
regmap_write(ctx->regmap, REG_LVDS_LANE,
(ctx->lvds_dual_link_even_odd_swap ?
REG_LVDS_LANE_EVEN_ODD_SWAP : 0) |
+ (ctx->lvds_reverse_lanes_conf[CHANNEL_A] ?
+ REG_LVDS_LANE_CHA_REVERSE_LVDS : 0) |
+ (ctx->lvds_reverse_lanes_conf[CHANNEL_B] ?
+ REG_LVDS_LANE_CHB_REVERSE_LVDS : 0) |
(ctx->lvds_term_conf[CHANNEL_A] ?
REG_LVDS_LANE_CHA_LVDS_TERM : 0) |
(ctx->lvds_term_conf[CHANNEL_B] ?
@@ -833,6 +850,7 @@ static int sn65dsi83_parse_lvds_endpoint(struct sn65dsi83 *ctx, int channel)
u32 lvds_vod_swing_clk[2] = { 0, 1000000 };
/* Set default near end terminataion to 200 Ohm */
u32 lvds_term = 200;
+ u32 data_lanes[DATA_LANES_COUNT];
int lvds_vod_swing_conf;
int ret_data;
int ret_clock;
@@ -845,6 +863,19 @@ static int sn65dsi83_parse_lvds_endpoint(struct sn65dsi83 *ctx, int channel)
else
return -EINVAL;
+ ret_data = of_property_read_u32_array(endpoint, "data-lanes", data_lanes,
+ ARRAY_SIZE(data_lanes));
+ if (!ret_data) {
+ if (memcmp(data_lanes,
+ supported_data_lane_mapping[LANE_MAPPING_REVERSE],
+ sizeof(data_lanes)) == 0)
+ ctx->lvds_reverse_lanes_conf[channel] = true;
+ else if (memcmp(data_lanes,
+ supported_data_lane_mapping[LANE_MAPPING_NORMAL],
+ sizeof(data_lanes)) != 0)
+ return dev_err_probe(dev, -EINVAL, "invalid data lanes mapping\n");
+ }
+
ret_data = of_property_read_u32_array(endpoint, "ti,lvds-vod-swing-data-microvolt",
lvds_vod_swing_data, ARRAY_SIZE(lvds_vod_swing_data));
if (ret_data != 0 && ret_data != -EINVAL)
--
2.47.3
^ permalink raw reply related [flat|nested] 5+ messages in thread