From: sashiko-bot@kernel.org
To: "Louis-Alexis Eyraud" <louisalexis.eyraud@collabora.com>
Cc: devicetree@vger.kernel.org, robh@kernel.org, conor+dt@kernel.org
Subject: Re: [PATCH v4 01/24] dt-bindings: clock: mediatek: Make '#clock-cells' required for MT8186
Date: Thu, 30 Jul 2026 10:05:28 +0000 [thread overview]
Message-ID: <20260730100528.604A61F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260729-mt8189-clocks-system-base-v4-1-e356b813a64c@collabora.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
Pre-existing issues:
- [Medium] The `#reset-cells` property is defined in the schema but is not conditionally enforced as a required property for the `mediatek,mt8186-infracfg_ao` hardware variant, which acts as a reset provider. This is a direct violation of the Device Tree Bindings Subsystem Guidelines ('Hardware Variant Required Properties').
--
--- Patch [1]: [PATCH v4 01/24] dt-bindings: clock: mediatek: Make '#clock-cells' required for MT8186 ---
commit d082742287ef7b48509a30300eb93b62072332ca
Author: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
dt-bindings: clock: mediatek: Make '#clock-cells' required for MT8186
This commit adds '#clock-cells' to the required properties list for both
the MT8186 clock and sys-clock device tree bindings. This enforces that
clock provider nodes properly define this property during validation.
[ ... ]
> diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-clock.yaml
> index 1c446fbc5108c..f8acc02cafeeb 100644
> --- a/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-clock.yaml
> +++ b/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-clock.yaml
> @@ -45,6 +45,7 @@ properties:
> required:
> - compatible
> - reg
> + - '#clock-cells'
[Severity: Medium]
This is a pre-existing issue, but while we are updating the required properties
here, should the schema also conditionally enforce '#reset-cells' for the
mediatek,mt8186-infracfg_ao variant?
The '#reset-cells' property is defined in the schema but lacks an
allOf: if-then block to conditionally enforce it specifically for the
mediatek,mt8186-infracfg_ao hardware variant, which acts as a reset provider.
Without this enforcement, device trees configuring the
mediatek,mt8186-infracfg_ao variant but omitting the mandatory '#reset-cells'
property will silently pass schema validation when running dt_binding_check.
>
> additionalProperties: false
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260729-mt8189-clocks-system-base-v4-0-e356b813a64c@collabora.com?part=1
next prev parent reply other threads:[~2026-07-30 10:05 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-29 10:02 [PATCH v4 00/24] MT8189: Add support for system and base clock controllers Louis-Alexis Eyraud
2026-07-29 10:02 ` [PATCH v4 01/24] dt-bindings: clock: mediatek: Make '#clock-cells' required for MT8186 Louis-Alexis Eyraud
2026-07-30 10:05 ` sashiko-bot [this message]
2026-07-29 10:02 ` [PATCH v4 02/24] dt-bindings: clock: mediatek: Make '#clock-cells' required for MT8192 Louis-Alexis Eyraud
2026-07-29 10:02 ` [PATCH v4 03/24] dt-bindings: clock: mediatek: Make '#clock-cells' required for MT8195 Louis-Alexis Eyraud
2026-07-29 10:02 ` [PATCH v4 04/24] dt-bindings: clock: mediatek: reorder MT8186 compatibles Louis-Alexis Eyraud
2026-07-29 10:02 ` [PATCH v4 05/24] dt-bindings: clock: mediatek: regroup MT8188 dt-bindings into MT8186 Louis-Alexis Eyraud
2026-07-30 10:05 ` sashiko-bot
2026-07-29 10:02 ` [PATCH v4 06/24] dt-bindings: clock: mediatek: regroup MT8192 " Louis-Alexis Eyraud
2026-07-30 10:05 ` sashiko-bot
2026-07-29 10:02 ` [PATCH v4 07/24] dt-bindings: clock: mediatek: regroup MT8195 " Louis-Alexis Eyraud
2026-07-29 10:02 ` [PATCH v4 08/24] dt-bindings: clock: mediatek: Add MT8189 system/base clocks and resets Louis-Alexis Eyraud
2026-07-29 10:02 ` [PATCH v4 09/24] clk: mediatek: Harmonize mtk_pll_fenc related symbol names Louis-Alexis Eyraud
2026-07-29 10:02 ` [PATCH v4 10/24] clk: mediatek: pll: Add BAR reset register offsets Louis-Alexis Eyraud
2026-07-30 10:05 ` sashiko-bot
2026-07-29 10:02 ` [PATCH v4 11/24] clk: mediatek: pll: split default prepare/unprepare callbacks Louis-Alexis Eyraud
2026-07-29 10:02 ` [PATCH v4 12/24] clk: mediatek: pll: Add ops for PLLs using set/clr regs Louis-Alexis Eyraud
2026-07-30 10:05 ` sashiko-bot
2026-07-29 10:02 ` [PATCH v4 13/24] clk: mediatek: pllfh: Add configurable clock ops to mtk_pllfh_data Louis-Alexis Eyraud
2026-07-30 10:05 ` sashiko-bot
2026-07-29 10:02 ` [PATCH v4 14/24] clk: mediatek: pllfh: Add ops for PLLs using set/clr regs Louis-Alexis Eyraud
2026-07-30 10:05 ` sashiko-bot
2026-07-29 10:02 ` [PATCH v4 15/24] clk: mediatek: Add MT8189 apmixedsys clock support Louis-Alexis Eyraud
2026-07-30 10:05 ` sashiko-bot
2026-07-29 10:03 ` [PATCH v4 16/24] clk: mediatek: Add MT8189 topckgen " Louis-Alexis Eyraud
2026-07-30 10:05 ` sashiko-bot
2026-07-29 10:03 ` [PATCH v4 17/24] clk: mediatek: Add MT8189 vlpckgen " Louis-Alexis Eyraud
2026-07-29 10:03 ` [PATCH v4 18/24] clk: mediatek: Add MT8189 vlpcfg " Louis-Alexis Eyraud
2026-07-29 10:03 ` [PATCH v4 19/24] clk: mediatek: Add MT8189 bus " Louis-Alexis Eyraud
2026-07-29 10:03 ` [PATCH v4 20/24] clk: mediatek: Add MT8189 dbgao " Louis-Alexis Eyraud
2026-07-29 10:03 ` [PATCH v4 21/24] clk: mediatek: Add MT8189 dvfsrc " Louis-Alexis Eyraud
2026-07-29 10:03 ` [PATCH v4 22/24] clk: mediatek: Add MT8189 i2c " Louis-Alexis Eyraud
2026-07-29 10:03 ` [PATCH v4 23/24] clk: mediatek: Add MT8189 scp " Louis-Alexis Eyraud
2026-07-29 10:03 ` [PATCH v4 24/24] clk: mediatek: Add MT8189 ufs " Louis-Alexis Eyraud
2026-07-30 10:05 ` sashiko-bot
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