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From: sashiko-bot@kernel.org
To: "Louis-Alexis Eyraud" <louisalexis.eyraud@collabora.com>
Cc: devicetree@vger.kernel.org, conor+dt@kernel.org, robh@kernel.org
Subject: Re: [PATCH v4 24/24] clk: mediatek: Add MT8189 ufs clock support
Date: Thu, 30 Jul 2026 10:05:34 +0000	[thread overview]
Message-ID: <20260730100534.DE4EA1F00A3A@smtp.kernel.org> (raw)
In-Reply-To: <20260729-mt8189-clocks-system-base-v4-24-e356b813a64c@collabora.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:

Pre-existing issues:
- [High] Missing `of_clk_del_provider()` in the error path of `__mtk_clk_simple_probe()` when reset controller registration fails, leading to a Use-After-Free.
--

--- Patch [24]: [PATCH v4 24/24] clk: mediatek: Add MT8189 ufs clock support ---
commit 73843c3d7b6ae3d2d34edc45116556bb9d3c1e8b
Author: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>

clk: mediatek: Add MT8189 ufs clock support

Add support for the MT8189 ufs clock controller, which provides clock
gate control for Universal Flash Storage.

> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt8189-ufs.c

[ ... ]

> +static const struct mtk_clk_desc ufscfg_ao_reg_mcd = {
> +	.clks = ufscfg_ao_reg_clks,
> +	.num_clks = ARRAY_SIZE(ufscfg_ao_reg_clks),
> +	.rst_desc = &ufscfg_ao_rst_desc,
> +};

[ ... ]

> +static struct platform_driver clk_mt8189_ufs_drv = {
> +	.probe = mtk_clk_simple_probe,
> +	.remove = mtk_clk_simple_remove,
> +	.driver = {
> +		.name = "clk-mt8189-ufs",
> +		.of_match_table = of_match_clk_mt8189_ufs,
> +	},
> +};

[Severity: High]
This isn't a bug introduced by this patch, but since this new driver uses
mtk_clk_simple_probe() and registers a reset controller (rst_desc), it
exposes a pre-existing issue in the error handling path of
__mtk_clk_simple_probe().

If mtk_register_reset_controller_with_dev() fails, the code jumps to
unregister_clks:

drivers/clk/mediatek/clk-mtk.c:__mtk_clk_simple_probe() {
    ...
    if (mcd->rst_desc) {
        r = mtk_register_reset_controller_with_dev(&pdev->dev,
                                                   mcd->rst_desc);
        if (r)
            goto unregister_clks;
    }
    ...
unregister_clks:
    ...
free_data:
    mtk_free_clk_data(clk_data);
}

Does this cleanup path leave a dangling pointer in the OF clock provider list?

It appears to free clk_data but fails to call of_clk_del_provider() to remove
the successfully registered clock provider.

If another driver attempts to look up a clock via the device tree after
probe failure, could of_clk_hw_onecell_get() dereference the freed clk_data
and cause a use-after-free?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260729-mt8189-clocks-system-base-v4-0-e356b813a64c@collabora.com?part=24

      reply	other threads:[~2026-07-30 10:05 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-29 10:02 [PATCH v4 00/24] MT8189: Add support for system and base clock controllers Louis-Alexis Eyraud
2026-07-29 10:02 ` [PATCH v4 01/24] dt-bindings: clock: mediatek: Make '#clock-cells' required for MT8186 Louis-Alexis Eyraud
2026-07-30 10:05   ` sashiko-bot
2026-07-29 10:02 ` [PATCH v4 02/24] dt-bindings: clock: mediatek: Make '#clock-cells' required for MT8192 Louis-Alexis Eyraud
2026-07-29 10:02 ` [PATCH v4 03/24] dt-bindings: clock: mediatek: Make '#clock-cells' required for MT8195 Louis-Alexis Eyraud
2026-07-29 10:02 ` [PATCH v4 04/24] dt-bindings: clock: mediatek: reorder MT8186 compatibles Louis-Alexis Eyraud
2026-07-29 10:02 ` [PATCH v4 05/24] dt-bindings: clock: mediatek: regroup MT8188 dt-bindings into MT8186 Louis-Alexis Eyraud
2026-07-30 10:05   ` sashiko-bot
2026-07-29 10:02 ` [PATCH v4 06/24] dt-bindings: clock: mediatek: regroup MT8192 " Louis-Alexis Eyraud
2026-07-30 10:05   ` sashiko-bot
2026-07-29 10:02 ` [PATCH v4 07/24] dt-bindings: clock: mediatek: regroup MT8195 " Louis-Alexis Eyraud
2026-07-29 10:02 ` [PATCH v4 08/24] dt-bindings: clock: mediatek: Add MT8189 system/base clocks and resets Louis-Alexis Eyraud
2026-07-29 10:02 ` [PATCH v4 09/24] clk: mediatek: Harmonize mtk_pll_fenc related symbol names Louis-Alexis Eyraud
2026-07-29 10:02 ` [PATCH v4 10/24] clk: mediatek: pll: Add BAR reset register offsets Louis-Alexis Eyraud
2026-07-30 10:05   ` sashiko-bot
2026-07-29 10:02 ` [PATCH v4 11/24] clk: mediatek: pll: split default prepare/unprepare callbacks Louis-Alexis Eyraud
2026-07-29 10:02 ` [PATCH v4 12/24] clk: mediatek: pll: Add ops for PLLs using set/clr regs Louis-Alexis Eyraud
2026-07-30 10:05   ` sashiko-bot
2026-07-29 10:02 ` [PATCH v4 13/24] clk: mediatek: pllfh: Add configurable clock ops to mtk_pllfh_data Louis-Alexis Eyraud
2026-07-30 10:05   ` sashiko-bot
2026-07-29 10:02 ` [PATCH v4 14/24] clk: mediatek: pllfh: Add ops for PLLs using set/clr regs Louis-Alexis Eyraud
2026-07-30 10:05   ` sashiko-bot
2026-07-29 10:02 ` [PATCH v4 15/24] clk: mediatek: Add MT8189 apmixedsys clock support Louis-Alexis Eyraud
2026-07-30 10:05   ` sashiko-bot
2026-07-29 10:03 ` [PATCH v4 16/24] clk: mediatek: Add MT8189 topckgen " Louis-Alexis Eyraud
2026-07-30 10:05   ` sashiko-bot
2026-07-29 10:03 ` [PATCH v4 17/24] clk: mediatek: Add MT8189 vlpckgen " Louis-Alexis Eyraud
2026-07-29 10:03 ` [PATCH v4 18/24] clk: mediatek: Add MT8189 vlpcfg " Louis-Alexis Eyraud
2026-07-29 10:03 ` [PATCH v4 19/24] clk: mediatek: Add MT8189 bus " Louis-Alexis Eyraud
2026-07-29 10:03 ` [PATCH v4 20/24] clk: mediatek: Add MT8189 dbgao " Louis-Alexis Eyraud
2026-07-29 10:03 ` [PATCH v4 21/24] clk: mediatek: Add MT8189 dvfsrc " Louis-Alexis Eyraud
2026-07-29 10:03 ` [PATCH v4 22/24] clk: mediatek: Add MT8189 i2c " Louis-Alexis Eyraud
2026-07-29 10:03 ` [PATCH v4 23/24] clk: mediatek: Add MT8189 scp " Louis-Alexis Eyraud
2026-07-29 10:03 ` [PATCH v4 24/24] clk: mediatek: Add MT8189 ufs " Louis-Alexis Eyraud
2026-07-30 10:05   ` sashiko-bot [this message]

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