* [PATCH v2] arm64: dts: broadcom: bcm2712: adjust display status
@ 2026-08-01 10:19 Peter Robinson
2026-08-01 10:30 ` sashiko-bot
0 siblings, 1 reply; 2+ messages in thread
From: Peter Robinson @ 2026-08-01 10:19 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Broadcom internal kernel review list, Stefan Wahren, Phil Elwell,
devicetree, linux-rpi-kernel, linux-arm-kernel
Cc: Peter Robinson, Florian Fainelli, Dave Stevenson,
Andrea della Porta
Typically non critical IP in a SoC are disabled by
default in the SoC .dtsi and enabled on board specific
configs. There are usecases, such as some CM5 carrier
boards, where display output may not be desired or
connected. So disable them on the SoC .dtsi and enable
them on the RPi5 board.
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Cc: Florian Fainelli <florian.fainelli@broadcom.com>
Cc: Dave Stevenson <dave.stevenson@raspberrypi.com>
Cc: Andrea della Porta <andrea.porta@suse.com>
Fixes: 25d77bdd7df2 ("arm64: dts: broadcom: Add display pipeline support to BCM2712")
---
v2: rebase to align with upstream changes
.../dts/broadcom/bcm2712-rpi-5-b-base.dtsi | 31 +++++++++++++++++++
arch/arm64/boot/dts/broadcom/bcm2712.dtsi | 11 +++++++
2 files changed, 42 insertions(+)
diff --git a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b-base.dtsi b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b-base.dtsi
index b7a6bc34ae1ab..51c8533f31812 100644
--- a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b-base.dtsi
+++ b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b-base.dtsi
@@ -104,6 +104,18 @@ wl_on_reg: wl-on-reg {
};
};
+&ddc0 {
+ status = "okay";
+};
+
+&ddc1 {
+ status = "okay";
+};
+
+&disp_intr {
+ status = "okay";
+};
+
&pinctrl {
bt_shutdown_default: bt-shutdown-default-state {
function = "gpio";
@@ -230,16 +242,27 @@ bluetooth: bluetooth {
&hvs {
clocks = <&firmware_clocks 4>, <&firmware_clocks 16>;
clock-names = "core", "disp";
+ status = "okay";
};
&hdmi0 {
clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 0>, <&clk_27MHz>;
clock-names = "hdmi", "bvb", "audio", "cec";
+ status = "okay";
};
&hdmi1 {
clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 1>, <&clk_27MHz>;
clock-names = "hdmi", "bvb", "audio", "cec";
+ status = "okay";
+};
+
+&mop {
+ status = "okay";
+};
+
+&moplet {
+ status = "okay";
};
&pcie1 {
@@ -250,6 +273,14 @@ &pcie2 {
status = "okay";
};
+&pixelvalve0 {
+ status = "okay";
+};
+
+&pixelvalve1 {
+ status = "okay";
+};
+
&v3d {
clocks = <&firmware_clocks 5>;
};
diff --git a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi
index 761c59d90ffc9..9b36ecd7bba54 100644
--- a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi
+++ b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi
@@ -359,12 +359,14 @@ pixelvalve0: pixelvalve@7c410000 {
compatible = "brcm,bcm2712-pixelvalve0";
reg = <0x7c410000 0x100>;
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
};
pixelvalve1: pixelvalve@7c411000 {
compatible = "brcm,bcm2712-pixelvalve1";
reg = <0x7c411000 0x100>;
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
};
mop: mop@7c500000 {
@@ -372,6 +374,7 @@ mop: mop@7c500000 {
reg = <0x7c500000 0x28>;
interrupt-parent = <&disp_intr>;
interrupts = <1>;
+ status = "disabled";
};
moplet: moplet@7c501000 {
@@ -379,6 +382,7 @@ moplet: moplet@7c501000 {
reg = <0x7c501000 0x20>;
interrupt-parent = <&disp_intr>;
interrupts = <0>;
+ status = "disabled";
};
disp_intr: interrupt-controller@7c502000 {
@@ -387,6 +391,7 @@ disp_intr: interrupt-controller@7c502000 {
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <1>;
+ status = "disabled";
};
dvp: clock@7c700000 {
@@ -405,6 +410,7 @@ ddc0: i2c@7d508200 {
clock-frequency = <97500>;
#address-cells = <1>;
#size-cells = <0>;
+ status = "disabled";
};
ddc1: i2c@7d508280 {
@@ -415,6 +421,7 @@ ddc1: i2c@7d508280 {
clock-frequency = <97500>;
#address-cells = <1>;
#size-cells = <0>;
+ status = "disabled";
};
bsc_irq: interrupt-controller@7d508380 {
@@ -460,6 +467,7 @@ hdmi0: hdmi@7c701400 {
interrupt-names = "cec-tx", "cec-rx", "cec-low",
"hpd-connected", "hpd-removed";
ddc = <&ddc0>;
+ status = "disabled";
};
hdmi1: hdmi@7c706400 {
@@ -489,6 +497,7 @@ hdmi1: hdmi@7c706400 {
interrupt-names = "cec-tx", "cec-rx", "cec-low",
"hpd-connected", "hpd-removed";
ddc = <&ddc1>;
+ status = "disabled";
};
};
@@ -667,6 +676,7 @@ v3d: gpu@1002000000 {
vc4: gpu {
compatible = "brcm,bcm2712-vc6";
+ status = "disabled";
};
timer {
@@ -703,5 +713,6 @@ hvs: hvs@107c580000 {
interrupt-parent = <&disp_intr>;
interrupts = <2>, <9>, <16>;
interrupt-names = "ch0-eof", "ch1-eof", "ch2-eof";
+ status = "disabled";
};
};
--
2.55.0
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH v2] arm64: dts: broadcom: bcm2712: adjust display status
2026-08-01 10:19 [PATCH v2] arm64: dts: broadcom: bcm2712: adjust display status Peter Robinson
@ 2026-08-01 10:30 ` sashiko-bot
0 siblings, 0 replies; 2+ messages in thread
From: sashiko-bot @ 2026-08-01 10:30 UTC (permalink / raw)
To: Peter Robinson; +Cc: devicetree, robh, conor+dt
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] The top-level `vc4` DRM master node is disabled in the SoC `.dtsi` but not re-enabled in the Raspberry Pi 5 board `.dtsi`, completely breaking the display pipeline.
--
--- Patch [1]: [PATCH v2] arm64: dts: broadcom: bcm2712: adjust display status ---
commit b39f5cc8783fb43e147088a4ba5ca6fbab8b9d6c
Author: Peter Robinson <pbrobinson@gmail.com>
arm64: dts: broadcom: bcm2712: adjust display status
This commit disables the display IP by default in the BCM2712 SoC device
tree. It then re-enables the required display components in the Raspberry
Pi 5 board configuration to allow display output when desired.
> diff --git a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b-base.dtsi b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b-base.dtsi
> index b7a6bc34ae1ab..51c8533f31812 100644
> --- a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b-base.dtsi
> +++ b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b-base.dtsi
[ ... ]
> @@ -250,6 +273,14 @@ &pcie2 {
> status = "okay";
> };
>
> +&pixelvalve0 {
> + status = "okay";
> +};
> +
> +&pixelvalve1 {
> + status = "okay";
> +};
> +
> &v3d {
> clocks = <&firmware_clocks 5>;
> };
> diff --git a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi
> index 761c59d90ffc9..9b36ecd7bba54 100644
> --- a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi
> +++ b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi
[ ... ]
> @@ -667,6 +676,7 @@ v3d: gpu@1002000000 {
>
> vc4: gpu {
> compatible = "brcm,bcm2712-vc6";
> + status = "disabled";
> };
[Severity: High]
This disables the top-level vc4 DRM master node at the SoC level, but looking
at the overrides in bcm2712-rpi-5-b-base.dtsi, the corresponding &vc4
enablement seems to be missing.
Since the other display subcomponents are being re-enabled, does the missing
status = "okay" for the vc4 node completely prevent the display pipeline from
probing on the Raspberry Pi 5?
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260801102000.551644-1-pbrobinson@gmail.com?part=1
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