[PATCH v5 00/17] Add thermal management support for sama7d65

[PATCH v5 00/17] Add thermal management support for sama7d65

[Varshini Rajendran]

Thermal management system of sama7d65 includes:

- Temperature sensor as a part of ADC channel
- Temperature calibration data retrieved from the OTP memory for
  improved accuracy of the readings
- DVFS implementation
- Thermal system with DVFS as cooling cell.

This patch series adds support for the following:

- Tag-based packet lookup for the NVMEM OTPC driver while preserving
  backward compatibility with existing ID-based access
- Temperature calibration layout handling in the ADC driver to support
  different SoC-specific calibration data formats
- ADC driver adaptation for sama7d65
- DT nodes for OTP, ADC, temperature sensor, and thermal zones for
  sama7d65

Changes in v5:
	- Placed the DEFINE_FREE helper in the header file and added it as a
	  new commit
	- Added IS_ERR_OR_NULL(_T) condition to the DEFINE_FREE of nvmem_cell_put
	- Reorder signing tags alphabetically in Patch 1
	- Kept the changes minimal by retaining ret variable
	- Collected the Rb tags

Link to v4: https://lore.kernel.org/lkml/20260727122633.117435-1-varshini.rajendran@microchip.com/

Changes in v4:
	- Reworked cleanup.h usage: define and assign __free() variables at point
	  of use after early returns, add DEFINE_FREE(nvmem_cell_put, ...) for
	  nvmem_cell cleanup
	- Split patch 3/13 into two: refactoring (layout struct) and tag validation
	- Used struct u32_fract for p1 scaling factors
	- Return -ENODEV instead of -EINVAL when layout is missing
	- New precursor patch to remove unnecessary casts in of_device_id
	- Removed trailing comma from single-line initializer array
	- Moved emulation mode validation into a separate patch
	- Added FourCC validation for packet tags; invalid tags fall back to ID-only
	  access
	- Mentioned FourCC in commit message and comments
	- Used intermediate variable for off % 4
	- Rename tmp → mr_val, val→ tag
	- Addressed style issues: Removed comment blocks, put functions in
	  one line
	- Remove blank line after compatible in regulator node
	- Reorder properties.

Link to v3: https://lore.kernel.org/lkml/20260630093603.38663-1-varshini.rajendran@microchip.com/

Changes in v3:
    - Updated the commit message with reasoning for a new compatible
      without a fallback (sama7d65-adc)
    - Split patch 2/12 into two patches: a patch with cleanup.h changes only
      and the rework patch
    - Added comment explaining the TAG ACST
    - Fixed the holes identified in the at91_adc_platform struct by
      pahole tool
    - Dropped labels in the dt document example
    - Added temp variable in mchp_otpc_resolve_packet() to avoid % and /
      operations in the same instruction (avoiding compiler optimization)
    - Added the SoC details in the ADC driver Kconfig help section
    - Maintained reverse xmas ordering in declarations
    - Fixed node ordering (alphabetically) in the board dts file

Link to v2: https://lore.kernel.org/lkml/20260623105944.128840-1-varshini.rajendran@microchip.com/

Changes in v2:
    - Preserved backward compatibility with ID-based packet lookup to
      avoid breaking existing users
    - Removed sama7g5 DTS changes (not needed with backward compatible
      driver - will be sent later to update to the new access method)
    - Preserved the packet data structure returned not to break the
      consumers
    - Reworked ADC driver to use a calibration layout structure instead of
      hardcoded indexes, for scalability
    - Fixed kernel-doc Return section
    - Removed stray blank line in mchp_otpc_read()
    - Removed unnecessary UL suffix in writel_relaxed()
    - Dropped unused packet types
    - Fixed stray spaces before exclamation marks in error messages
    - Added ASCII representation to TAG macro definition
    - Removed odd MAX enum with trailing comma and refactored
    - Moved DTS patches to the end of series
    - Used cleanup.h helpers for NVMEM data buffer handling in ADC driver
    - Combined multiple v1 patches into logical units
    - Used correct subject prefixes for dt-bindings patches
    - Used fixed-layout NVMEM syntax for sama7d65 DTS and binding
      instead of deprecated syntax
    - Added cpu-supply linkage for proper DVFS voltage scaling
    - Updated stale stride=4 comment in dt-bindings header

Link to v1: https://lore.kernel.org/linux-arm-kernel/20250804100219.63325-1-varshini.rajendran@microchip.com/

Varshini Rajendran (17):
  dt-bindings: iio: adc: at91-sama5d2: document sama7d65
  nvmem: add DEFINE_FREE for nvmem_cell_put cleanup
  iio: adc: at91-sama5d2_adc: use cleanup.h for NVMEM buffer
  iio: adc: at91-sama5d2_adc: rework temp calibration layout handling
  iio: adc: at91-sama5d2_adc: add condition to validate calibration data
  iio: adc: at91-sama5d2_adc: remove unnecessary casts in of_device_id
  iio: adc: at91-sama5d2_adc: adapt the driver for sama7d65
  dt-bindings: nvmem: microchip,sama7g5-otpc: add sama7d65 and dt node
    example
  nvmem: microchip-otpc: nvmem: microchip-otpc: add tag-based packet
    lookup
  nvmem: microchip-otpc: nvmem: add emulation mode and OTP access
    validation
  ARM: dts: microchip: sama7d65: add cpu opps
  ARM: dts: microchip: sama7d65: Add ADC node
  ARM: dts: microchip: sama7d65_curiosity: Enable ADC, DVFS
  ARM: dts: microchip: sama7d65: add otpc node
  ARM: dts: microchip: sama7d65: add cells for temperature calibration
  ARM: dts: microchip: sama7d65: add temperature sensor
  ARM: dts: microchip: sama7d65: add thermal zones node

 .../bindings/iio/adc/atmel,sama5d2-adc.yaml   |   1 +
 .../nvmem/microchip,sama7g5-otpc.yaml         |  28 +++-
 .../dts/microchip/at91-sama7d65_curiosity.dts |  27 ++++
 arch/arm/boot/dts/microchip/sama7d65.dtsi     | 131 +++++++++++++++++
 drivers/iio/adc/Kconfig                       |   2 +-
 drivers/iio/adc/at91-sama5d2_adc.c            | 124 +++++++++++-----
 drivers/nvmem/microchip-otpc.c                | 133 ++++++++++++++++--
 .../nvmem/microchip,sama7g5-otpc.h            |   4 +-
 include/linux/nvmem-consumer.h                |   4 +
 9 files changed, 404 insertions(+), 50 deletions(-)

-- 
2.34.1

[PATCH v5 01/17] dt-bindings: iio: adc: at91-sama5d2: document sama7d65

[Varshini Rajendran]

Add dt-binding documentation for sama7d65 ADC.

sama7d65 requires an individual compatible to address the differences
from its predecessor sama7g5. The main difference is the temperature
calibration layout and its handling.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
---
 Documentation/devicetree/bindings/iio/adc/atmel,sama5d2-adc.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/iio/adc/atmel,sama5d2-adc.yaml b/Documentation/devicetree/bindings/iio/adc/atmel,sama5d2-adc.yaml
index 4817b840977a..e8a65fdcd018 100644
--- a/Documentation/devicetree/bindings/iio/adc/atmel,sama5d2-adc.yaml
+++ b/Documentation/devicetree/bindings/iio/adc/atmel,sama5d2-adc.yaml
@@ -15,6 +15,7 @@ properties:
       - atmel,sama5d2-adc
       - microchip,sam9x60-adc
       - microchip,sama7g5-adc
+      - microchip,sama7d65-adc
 
   reg:
     maxItems: 1
-- 
2.34.1

[PATCH v5 02/17] nvmem: add DEFINE_FREE for nvmem_cell_put cleanup

[Varshini Rajendran]

Add cleanup.h helper for nvmem_cell_put() to enable automatic resource
cleanup using __free(nvmem_cell_put) annotation.

Use IS_ERR_OR_NULL() since nvmem_cell_get() can return error pointers,
and passing an ERR_PTR to nvmem_cell_put() would cause issues.

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
---
 include/linux/nvmem-consumer.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/include/linux/nvmem-consumer.h b/include/linux/nvmem-consumer.h
index 34c0e58dfa26..35a2ea8b8957 100644
--- a/include/linux/nvmem-consumer.h
+++ b/include/linux/nvmem-consumer.h
@@ -9,6 +9,7 @@
 #ifndef _LINUX_NVMEM_CONSUMER_H
 #define _LINUX_NVMEM_CONSUMER_H
 
+#include <linux/cleanup.h>
 #include <linux/err.h>
 #include <linux/errno.h>
 #include <linux/notifier.h>
@@ -54,6 +55,9 @@ struct nvmem_cell *nvmem_cell_get(struct device *dev, const char *id);
 struct nvmem_cell *devm_nvmem_cell_get(struct device *dev, const char *id);
 void nvmem_cell_put(struct nvmem_cell *cell);
 void devm_nvmem_cell_put(struct device *dev, struct nvmem_cell *cell);
+
+DEFINE_FREE(nvmem_cell_put, struct nvmem_cell *, if (!IS_ERR_OR_NULL(_T)) nvmem_cell_put(_T))
+
 void *nvmem_cell_read(struct nvmem_cell *cell, size_t *len);
 int nvmem_cell_write(struct nvmem_cell *cell, void *buf, size_t len);
 int nvmem_cell_read_u8(struct device *dev, const char *cell_id, u8 *val);
-- 
2.34.1

[PATCH v5 03/17] iio: adc: at91-sama5d2_adc: use cleanup.h for NVMEM buffer

[Varshini Rajendran]

Use __free(kfree) and __free(nvmem_cell_put) cleanup helpers in
at91_adc_temp_sensor_init() to simplify error handling paths.

Reviewed-by: Andy Shevchenko <andriy.shevchenko@intel.com>
Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
---
 drivers/iio/adc/at91-sama5d2_adc.c | 25 ++++++++++---------------
 1 file changed, 10 insertions(+), 15 deletions(-)

diff --git a/drivers/iio/adc/at91-sama5d2_adc.c b/drivers/iio/adc/at91-sama5d2_adc.c
index e8a5285bb6d4..09390f082fc4 100644
--- a/drivers/iio/adc/at91-sama5d2_adc.c
+++ b/drivers/iio/adc/at91-sama5d2_adc.c
@@ -2249,8 +2249,6 @@ static int at91_adc_temp_sensor_init(struct at91_adc_state *st,
 				     struct device *dev)
 {
 	struct at91_adc_temp_sensor_clb *clb = &st->soc_info.temp_sensor_clb;
-	struct nvmem_cell *temp_calib;
-	u32 *buf;
 	size_t len;
 	int ret = 0;
 
@@ -2258,7 +2256,8 @@ static int at91_adc_temp_sensor_init(struct at91_adc_state *st,
 		return 0;
 
 	/* Get the calibration data from NVMEM. */
-	temp_calib = nvmem_cell_get(dev, "temperature_calib");
+	struct nvmem_cell *temp_calib __free(nvmem_cell_put) =
+		nvmem_cell_get(dev, "temperature_calib");
 	if (IS_ERR(temp_calib)) {
 		ret = PTR_ERR(temp_calib);
 		if (ret != -ENOENT)
@@ -2266,16 +2265,14 @@ static int at91_adc_temp_sensor_init(struct at91_adc_state *st,
 		return ret;
 	}
 
-	buf = nvmem_cell_read(temp_calib, &len);
-	nvmem_cell_put(temp_calib);
-	if (IS_ERR(buf)) {
-		dev_err(dev, "Failed to read calibration data!\n");
-		return PTR_ERR(buf);
-	}
-	if (len < AT91_ADC_TS_CLB_IDX_MAX * 4) {
+	u32 *buf __free(kfree) = nvmem_cell_read(temp_calib, &len);
+	if (IS_ERR(buf))
+		return dev_err_probe(dev, PTR_ERR(buf),
+				     "Failed to read calibration data!\n");
+
+	if (len < AT91_ADC_TS_CLB_IDX_MAX * sizeof(*buf)) {
 		dev_err(dev, "Invalid calibration data!\n");
-		ret = -EINVAL;
-		goto free_buf;
+		return -EINVAL;
 	}
 
 	/* Store calibration data for later use. */
@@ -2288,9 +2285,7 @@ static int at91_adc_temp_sensor_init(struct at91_adc_state *st,
 	 */
 	clb->p1 = clb->p1 * 1000;
 
-free_buf:
-	kfree(buf);
-	return ret;
+	return 0;
 }
 
 static int at91_adc_probe(struct platform_device *pdev)
-- 
2.34.1

[PATCH v5 04/17] iio: adc: at91-sama5d2_adc: rework temp calibration layout handling

[Varshini Rajendran]

Extend support to handle different temperature calibration layouts.

Add a temperature calibration data layout structure to describe indexes
of the factors P1, P4, P6, tag, minimum length of the packet and the
scaling factors for P1 (p1_scale) which are SoC-specific instead of the
older non scalable id structure. This helps handle the differences in the
same function flow and prepare the calibration data to be applied.

Reviewed-by: Eugen Hristev <ehristev@kernel.org>
Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
---
 drivers/iio/adc/at91-sama5d2_adc.c | 66 ++++++++++++++++++++++--------
 1 file changed, 48 insertions(+), 18 deletions(-)

diff --git a/drivers/iio/adc/at91-sama5d2_adc.c b/drivers/iio/adc/at91-sama5d2_adc.c
index 09390f082fc4..82db8f2f4db0 100644
--- a/drivers/iio/adc/at91-sama5d2_adc.c
+++ b/drivers/iio/adc/at91-sama5d2_adc.c
@@ -16,6 +16,7 @@
 #include <linux/dmaengine.h>
 #include <linux/interrupt.h>
 #include <linux/io.h>
+#include <linux/math.h>
 #include <linux/module.h>
 #include <linux/platform_device.h>
 #include <linux/property.h>
@@ -444,6 +445,27 @@ static const struct at91_adc_reg_layout sama7g5_layout = {
 #define at91_adc_writel(st, reg, val)					\
 	writel_relaxed(val, (st)->base + (st)->soc_info.platform->layout->reg)
 
+/* Temperature calibration tag "ACST" in ASCII */
+#define AT91_TEMP_CALIB_TAG_ACST	0x41435354
+
+/**
+ * struct at91_adc_temp_calib_layout - temperature calibration packet layout
+ * @tag_idx:	index of Packet tag in the NVMEM cell buffer
+ * @p1_idx:	index of FT1_TEMP, equivalent to P1 in the NVMEM cell buffer
+ * @p4_idx:	index of FT1_VPAT, equivalent to P4 in the NVMEM cell buffer
+ * @p6_idx:	index of FT2_VBG, equivalent to P6 in the NVMEM cell buffer
+ * @min_len:	minimum number of u32 words expected in the NVMEM cell buffer
+ * @p1_scale:	scaling factor applied to P1 to convert to millicelcius
+ */
+struct at91_adc_temp_calib_layout {
+	unsigned int tag_idx;
+	unsigned int p1_idx;
+	unsigned int p4_idx;
+	unsigned int p6_idx;
+	unsigned int min_len;
+	struct u32_fract p1_scale;
+};
+
 /**
  * struct at91_adc_platform - at91-sama5d2 platform information struct
  * @layout:		pointer to the reg layout struct
@@ -462,6 +484,7 @@ static const struct at91_adc_reg_layout sama7g5_layout = {
  * @oversampling_avail_no: number of available oversampling values
  * @chan_realbits:	realbits for registered channels
  * @temp_chan:		temperature channel index
+ * @temp_calib_layout:	temperature calibration packet layout
  * @temp_sensor:	temperature sensor supported
  */
 struct at91_adc_platform {
@@ -479,6 +502,7 @@ struct at91_adc_platform {
 	unsigned int				oversampling_avail_no;
 	unsigned int				chan_realbits;
 	unsigned int				temp_chan;
+	const struct at91_adc_temp_calib_layout	*temp_calib_layout;
 	bool					temp_sensor;
 };
 
@@ -495,18 +519,13 @@ struct at91_adc_temp_sensor_clb {
 	u32 p6;
 };
 
-/**
- * enum at91_adc_ts_clb_idx - calibration indexes in NVMEM buffer
- * @AT91_ADC_TS_CLB_IDX_P1: index for P1
- * @AT91_ADC_TS_CLB_IDX_P4: index for P4
- * @AT91_ADC_TS_CLB_IDX_P6: index for P6
- * @AT91_ADC_TS_CLB_IDX_MAX: max index for temperature calibration packet in OTP
- */
-enum at91_adc_ts_clb_idx {
-	AT91_ADC_TS_CLB_IDX_P1 = 2,
-	AT91_ADC_TS_CLB_IDX_P4 = 5,
-	AT91_ADC_TS_CLB_IDX_P6 = 7,
-	AT91_ADC_TS_CLB_IDX_MAX = 19,
+static const struct at91_adc_temp_calib_layout sama7g5_temp_calib = {
+	.tag_idx = 1,
+	.p1_idx = 2,
+	.p4_idx = 5,
+	.p6_idx = 7,
+	.min_len = 19,
+	.p1_scale = { .numerator = 1000, .denominator = 1 },
 };
 
 /* Temperature sensor calibration - Vtemp voltage sensitivity to temperature. */
@@ -744,6 +763,7 @@ static const struct at91_adc_platform sama7g5_platform = {
 	.chan_realbits = 16,
 	.temp_sensor = true,
 	.temp_chan = AT91_SAMA7G5_ADC_TEMP_CHANNEL,
+	.temp_calib_layout = &sama7g5_temp_calib,
 };
 
 static int at91_adc_chan_xlate(struct iio_dev *indio_dev, int chan)
@@ -2249,12 +2269,19 @@ static int at91_adc_temp_sensor_init(struct at91_adc_state *st,
 				     struct device *dev)
 {
 	struct at91_adc_temp_sensor_clb *clb = &st->soc_info.temp_sensor_clb;
+	const struct at91_adc_temp_calib_layout *layout;
 	size_t len;
 	int ret = 0;
 
 	if (!st->soc_info.platform->temp_sensor)
 		return 0;
 
+	layout = st->soc_info.platform->temp_calib_layout;
+	if (!layout)
+		return -ENODEV;
+	if (!layout->p1_scale.denominator)
+		return -EINVAL;
+
 	/* Get the calibration data from NVMEM. */
 	struct nvmem_cell *temp_calib __free(nvmem_cell_put) =
 		nvmem_cell_get(dev, "temperature_calib");
@@ -2270,20 +2297,23 @@ static int at91_adc_temp_sensor_init(struct at91_adc_state *st,
 		return dev_err_probe(dev, PTR_ERR(buf),
 				     "Failed to read calibration data!\n");
 
-	if (len < AT91_ADC_TS_CLB_IDX_MAX * sizeof(*buf)) {
+	if (len < layout->min_len * sizeof(*buf)) {
 		dev_err(dev, "Invalid calibration data!\n");
 		return -EINVAL;
 	}
 
 	/* Store calibration data for later use. */
-	clb->p1 = buf[AT91_ADC_TS_CLB_IDX_P1];
-	clb->p4 = buf[AT91_ADC_TS_CLB_IDX_P4];
-	clb->p6 = buf[AT91_ADC_TS_CLB_IDX_P6];
+	clb->p1 = buf[layout->p1_idx];
+	clb->p4 = buf[layout->p4_idx];
+	clb->p6 = buf[layout->p6_idx];
 
 	/*
-	 * We prepare here the conversion to milli to avoid doing it on hotpath.
+	 * Here we prepare the conversion to milli to avoid doing it on hotpath.
+	 * The p1 value is multiplied and divided with a scaling factor as per
+	 * the SoC storage format described by per-platform calibration layout.
 	 */
-	clb->p1 = clb->p1 * 1000;
+	clb->p1 *= layout->p1_scale.numerator;
+	clb->p1 /= layout->p1_scale.denominator;
 
 	return 0;
 }
-- 
2.34.1

[PATCH v5 05/17] iio: adc: at91-sama5d2_adc: add condition to validate calibration data

[Varshini Rajendran]

Add additional condition to validate the calibration data read from the
NVMEM cell using the TAG of the packet.

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
---
 drivers/iio/adc/at91-sama5d2_adc.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/iio/adc/at91-sama5d2_adc.c b/drivers/iio/adc/at91-sama5d2_adc.c
index 82db8f2f4db0..5b21367cf6b4 100644
--- a/drivers/iio/adc/at91-sama5d2_adc.c
+++ b/drivers/iio/adc/at91-sama5d2_adc.c
@@ -2297,7 +2297,8 @@ static int at91_adc_temp_sensor_init(struct at91_adc_state *st,
 		return dev_err_probe(dev, PTR_ERR(buf),
 				     "Failed to read calibration data!\n");
 
-	if (len < layout->min_len * sizeof(*buf)) {
+	if (len < layout->min_len * sizeof(*buf) ||
+	    buf[layout->tag_idx] != AT91_TEMP_CALIB_TAG_ACST) {
 		dev_err(dev, "Invalid calibration data!\n");
 		return -EINVAL;
 	}
-- 
2.34.1

[PATCH v5 06/17] iio: adc: at91-sama5d2_adc: remove unnecessary casts in of_device_id

[Varshini Rajendran]

The .data field in struct of_device_id is 'const void *', so explicit
casts are unnecessary when assigning addresses of const structs.

Reviewed-by: Eugen Hristev <ehristev@kernel.org>
Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
---
 drivers/iio/adc/at91-sama5d2_adc.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/iio/adc/at91-sama5d2_adc.c b/drivers/iio/adc/at91-sama5d2_adc.c
index 5b21367cf6b4..3e9feb824a66 100644
--- a/drivers/iio/adc/at91-sama5d2_adc.c
+++ b/drivers/iio/adc/at91-sama5d2_adc.c
@@ -2628,10 +2628,10 @@ static const struct dev_pm_ops at91_adc_pm_ops = {
 static const struct of_device_id at91_adc_dt_match[] = {
 	{
 		.compatible = "atmel,sama5d2-adc",
-		.data = (const void *)&sama5d2_platform,
+		.data = &sama5d2_platform,
 	}, {
 		.compatible = "microchip,sama7g5-adc",
-		.data = (const void *)&sama7g5_platform,
+		.data = &sama7g5_platform,
 	}, {
 		/* sentinel */
 	}
-- 
2.34.1

[PATCH v5 07/17] iio: adc: at91-sama5d2_adc: adapt the driver for sama7d65

[Varshini Rajendran]

Add support for sama7d65 ADC. The differences are highlighted with the
compatible. The calibration data layout is the main difference.

Update Kconfig help text to mention SAMA7 SoC family support.

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
---
 drivers/iio/adc/Kconfig            |  2 +-
 drivers/iio/adc/at91-sama5d2_adc.c | 30 ++++++++++++++++++++++++++++++
 2 files changed, 31 insertions(+), 1 deletion(-)

diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
index 3755a81c1efd..85b443853a08 100644
--- a/drivers/iio/adc/Kconfig
+++ b/drivers/iio/adc/Kconfig
@@ -647,7 +647,7 @@ config AT91_SAMA5D2_ADC
 	select IIO_TRIGGERED_BUFFER
 	help
 	  Say yes here to build support for Atmel SAMA5D2 ADC which is
-	  available on SAMA5D2 SoC family.
+	  available on SAMA5D2 and SAMA7 SoC families.
 
 	  To compile this driver as a module, choose M here: the module will be
 	  called at91-sama5d2_adc.
diff --git a/drivers/iio/adc/at91-sama5d2_adc.c b/drivers/iio/adc/at91-sama5d2_adc.c
index 3e9feb824a66..c1e5139a058c 100644
--- a/drivers/iio/adc/at91-sama5d2_adc.c
+++ b/drivers/iio/adc/at91-sama5d2_adc.c
@@ -528,6 +528,15 @@ static const struct at91_adc_temp_calib_layout sama7g5_temp_calib = {
 	.p1_scale = { .numerator = 1000, .denominator = 1 },
 };
 
+static const struct at91_adc_temp_calib_layout sama7d65_temp_calib = {
+	.tag_idx = 1,
+	.p1_idx = 3,
+	.p4_idx = 2,
+	.p6_idx = 5,
+	.min_len = 11,
+	.p1_scale = { .numerator = 1, .denominator = 1000 },
+};
+
 /* Temperature sensor calibration - Vtemp voltage sensitivity to temperature. */
 #define AT91_ADC_TS_VTEMP_DT		(2080U)
 
@@ -766,6 +775,24 @@ static const struct at91_adc_platform sama7g5_platform = {
 	.temp_calib_layout = &sama7g5_temp_calib,
 };
 
+static const struct at91_adc_platform sama7d65_platform = {
+	.layout = &sama7g5_layout,
+	.adc_channels = &at91_sama7g5_adc_channels,
+	.nr_channels = AT91_SAMA7G5_SINGLE_CHAN_CNT +
+		       AT91_SAMA7G5_DIFF_CHAN_CNT +
+		       AT91_SAMA7G5_TEMP_CHAN_CNT,
+	.max_channels = ARRAY_SIZE(at91_sama7g5_adc_channels),
+	.max_index = AT91_SAMA7G5_MAX_CHAN_IDX,
+	.hw_trig_cnt = AT91_SAMA7G5_HW_TRIG_CNT,
+	.osr_mask = GENMASK(18, 16),
+	.oversampling_avail = { 1, 4, 16, 64, 256 },
+	.oversampling_avail_no = 5,
+	.chan_realbits = 16,
+	.temp_sensor = true,
+	.temp_chan = AT91_SAMA7G5_ADC_TEMP_CHANNEL,
+	.temp_calib_layout = &sama7d65_temp_calib,
+};
+
 static int at91_adc_chan_xlate(struct iio_dev *indio_dev, int chan)
 {
 	int i;
@@ -2632,6 +2659,9 @@ static const struct of_device_id at91_adc_dt_match[] = {
 	}, {
 		.compatible = "microchip,sama7g5-adc",
 		.data = &sama7g5_platform,
+	}, {
+		.compatible = "microchip,sama7d65-adc",
+		.data = &sama7d65_platform,
 	}, {
 		/* sentinel */
 	}
-- 
2.34.1

[PATCH v5 08/17] dt-bindings: nvmem: microchip,sama7g5-otpc: add sama7d65 and dt node example

[Varshini Rajendran]

Add support for sama7d65 and a dt node example that shows tag can be used
to reference a packet stored in the OTP memory.

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
---
 .../nvmem/microchip,sama7g5-otpc.yaml         | 28 +++++++++++++++++--
 1 file changed, 25 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/nvmem/microchip,sama7g5-otpc.yaml b/Documentation/devicetree/bindings/nvmem/microchip,sama7g5-otpc.yaml
index cc25f2927682..04b44660554e 100644
--- a/Documentation/devicetree/bindings/nvmem/microchip,sama7g5-otpc.yaml
+++ b/Documentation/devicetree/bindings/nvmem/microchip,sama7g5-otpc.yaml
@@ -20,9 +20,15 @@ allOf:
 
 properties:
   compatible:
-    items:
-      - const: microchip,sama7g5-otpc
-      - const: syscon
+    oneOf:
+      - items:
+          - const: microchip,sama7g5-otpc
+          - const: syscon
+      - items:
+          - enum:
+              - microchip,sama7d65-otpc
+          - const: microchip,sama7g5-otpc
+          - const: syscon
 
   reg:
     maxItems: 1
@@ -48,4 +54,20 @@ examples:
         };
     };
 
+  - |
+    efuse@e8c00000 {
+        compatible = "microchip,sama7d65-otpc", "microchip,sama7g5-otpc", "syscon";
+        reg = <0xe8c00000 0x100>;
+
+        nvmem-layout {
+            compatible = "fixed-layout";
+            #address-cells = <1>;
+            #size-cells = <1>;
+
+            calib@41435354 {
+                reg = <0x41435354 0x2c>;    /* Temp calib data packet TAG */
+            };
+        };
+    };
+
 ...
-- 
2.34.1

[PATCH v5 09/17] nvmem: microchip-otpc: nvmem: microchip-otpc: add tag-based packet lookup

[Varshini Rajendran]

Add support for accessing OTP packets by their tag which is a FourCC
while preserving backward compatibility with the existing ID-based
lookup.

The OTP memory layout can vary across devices and may change over time,
making the packet ID approach unreliable when the memory map is not
known in advance. The packet tag provides a reliable way to identify
and access packets without prior knowledge of the OTP memory layout.

Two offset encodings are now supported:
  1. Legacy ID-based: offset = OTP_PKT(id) = id * 4
     Used in DT as: reg = <OTP_PKT(1) 76>;
  2. TAG-based: offset = 4-byte ASCII packet tag (FourCC)
     Used in DT as: reg = <0x41435354 0x4c>; (tag "ACST")

The driver resolves offsets matching valid legacy selectors (multiples
of 4 within the packet count) through ID lookup, falling back to tag
lookup for other valid values. This ensures existing device trees
continue to work while enabling new tag-based access. During probe,
packet meta data including the tag is read and cached.

The stride of the nvmem memory is set to 1 in order to support tag based
offsets, comment in the header file is updated accordingly.

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
---
 drivers/nvmem/microchip-otpc.c                | 117 ++++++++++++++++--
 .../nvmem/microchip,sama7g5-otpc.h            |   4 +-
 2 files changed, 110 insertions(+), 11 deletions(-)

diff --git a/drivers/nvmem/microchip-otpc.c b/drivers/nvmem/microchip-otpc.c
index df979e8549fd..a17f82afdc37 100644
--- a/drivers/nvmem/microchip-otpc.c
+++ b/drivers/nvmem/microchip-otpc.c
@@ -23,6 +23,8 @@
 #define MCHP_OTPC_SR_READ		BIT(6)
 #define MCHP_OTPC_HR			(0x20)
 #define MCHP_OTPC_HR_SIZE		GENMASK(15, 8)
+#define MCHP_OTPC_HR_PACKET		GENMASK(2, 0)
+#define MCHP_OTPC_HR_PACKET_REGULAR	1
 #define MCHP_OTPC_DR			(0x24)
 
 #define MCHP_OTPC_NAME			"mchp-otpc"
@@ -47,11 +49,13 @@ struct mchp_otpc {
  * @list: list head
  * @id: packet ID
  * @offset: packet offset (in words) in OTP memory
+ * @tag: 4-byte ASCII (FourCC) tag of the packet
  */
 struct mchp_otpc_packet {
 	struct list_head list;
 	u32 id;
 	u32 offset;
+	u32 tag;
 };
 
 static struct mchp_otpc_packet *mchp_otpc_id_to_packet(struct mchp_otpc *otpc,
@@ -70,6 +74,52 @@ static struct mchp_otpc_packet *mchp_otpc_id_to_packet(struct mchp_otpc *otpc,
 	return NULL;
 }
 
+static struct mchp_otpc_packet *mchp_otpc_tag_to_packet(struct mchp_otpc *otpc, u32 tag)
+{
+	struct mchp_otpc_packet *packet;
+
+	list_for_each_entry(packet, &otpc->packets, list) {
+		if (packet->tag == tag)
+			return packet;
+	}
+
+	return NULL;
+}
+
+static bool mchp_otpc_is_valid_fourcc(u32 tag)
+{
+	int i;
+	u8 c;
+
+	for (i = 0; i < 4; i++) {
+		c = (tag >> (i * 8)) & 0xff;
+		if (c < 0x20 || c > 0x7e)
+			return false;
+	}
+
+	return true;
+}
+
+static struct mchp_otpc_packet *mchp_otpc_resolve_packet(struct mchp_otpc *otpc, u32 off)
+{
+	/*
+	 * Legacy id based packet access: offset = id * 4
+	 * Inside the driver we use continuous unsigned integer numbers
+	 * for packet id, thus divide off by 4 before passing it to
+	 * mchp_otpc_id_to_packet().
+	 */
+	u32 remainder = off % 4;
+	u32 id = off / 4;
+
+	if (!remainder && id < otpc->npackets)
+		return mchp_otpc_id_to_packet(otpc, id);
+
+	/*
+	 * TAG-based packet access: offset is a 4-byte ASCII tag (FourCC)
+	 */
+	return mchp_otpc_tag_to_packet(otpc, off);
+}
+
 static int mchp_otpc_prepare_read(struct mchp_otpc *otpc,
 				  unsigned int offset)
 {
@@ -140,8 +190,29 @@ static int mchp_otpc_prepare_read(struct mchp_otpc *otpc,
  * offset returned by hardware.
  *
  * For this, the read function will return the first requested bytes in the
- * packet. The user will have to be aware of the memory footprint before doing
- * the read request.
+ * packet.
+ *
+ * Two offset encodings are supported:
+ *
+ * 1. Legacy ID-based: offset = OTP_PKT(id) = id * 4
+ *    Used in DT as: reg = <OTP_PKT(1) 76>;
+ * 2. TAG-based: offset = 4-byte ASCII packet tag (FourCC)
+ *    Used in DT as: reg = <0x41435354 0x4c>; (tag "ACST")
+ *
+ * To use the legacy ID based packet lookup the user will have to be aware of
+ * the memory footprint before doing the read request.
+ *
+ * But by using the TAG based packet lookup, the user won't have to be aware
+ * of the memory footprint before doing the read request since this driver has
+ * it abstracted and taken care of.
+ *
+ * Practically, there is no way of knowing the mapping of the OTP memory table
+ * in advance for every device. But by using the packet tag - the identifier
+ * ASCII value (FourCC), the packets can be recognized without being aware of the
+ * flashed OTP memory map table and the payload can be acquired reliably.
+ *
+ * While the legacy ID based lookup is still supported, TAG based approach is
+ * recommended.
  */
 static int mchp_otpc_read(void *priv, unsigned int off, void *val,
 			  size_t bytes)
@@ -154,12 +225,11 @@ static int mchp_otpc_read(void *priv, unsigned int off, void *val,
 	int ret, payload_size;
 
 	/*
-	 * We reach this point with off being multiple of stride = 4 to
-	 * be able to cross the subsystem. Inside the driver we use continuous
-	 * unsigned integer numbers for packet id, thus divide off by 4
-	 * before passing it to mchp_otpc_id_to_packet().
+	 * From this point the offset has to be translated into the actual
+	 * packet. For this we traverse the table of contents stored in a list
+	 * "packet" based on the access type - packet id or tag.
 	 */
-	packet = mchp_otpc_id_to_packet(otpc, off / 4);
+	packet = mchp_otpc_resolve_packet(otpc, off);
 	if (!packet)
 		return -EINVAL;
 	offset = packet->offset;
@@ -190,10 +260,25 @@ static int mchp_otpc_read(void *priv, unsigned int off, void *val,
 	return 0;
 }
 
+static int mchp_otpc_read_packet_tag(struct mchp_otpc *otpc, unsigned int offset,
+				     unsigned int *tag)
+{
+	int ret;
+
+	ret = mchp_otpc_prepare_read(otpc, offset);
+	if (ret)
+		return ret;
+
+	writel_relaxed(0, otpc->base + MCHP_OTPC_AR);
+	*tag = readl_relaxed(otpc->base + MCHP_OTPC_DR);
+
+	return 0;
+}
+
 static int mchp_otpc_init_packets_list(struct mchp_otpc *otpc, u32 *size)
 {
 	struct mchp_otpc_packet *packet;
-	u32 word, word_pos = 0, id = 0, npackets = 0, payload_size;
+	u32 word, word_pos = 0, id = 0, npackets = 0, payload_size, type;
 	int ret;
 
 	INIT_LIST_HEAD(&otpc->packets);
@@ -215,6 +300,20 @@ static int mchp_otpc_init_packets_list(struct mchp_otpc *otpc, u32 *size)
 
 		packet->id = id++;
 		packet->offset = word_pos;
+		type = FIELD_GET(MCHP_OTPC_HR_PACKET, word);
+
+		if (type == MCHP_OTPC_HR_PACKET_REGULAR) {
+			ret = mchp_otpc_read_packet_tag(otpc, packet->offset,
+							&packet->tag);
+			if (ret)
+				return ret;
+
+			if (!mchp_otpc_is_valid_fourcc(packet->tag))
+				packet->tag = 0;
+		} else {
+			packet->tag = 0;
+		}
+
 		INIT_LIST_HEAD(&packet->list);
 		list_add_tail(&packet->list, &otpc->packets);
 
@@ -236,7 +335,7 @@ static struct nvmem_config mchp_nvmem_config = {
 	.type = NVMEM_TYPE_OTP,
 	.read_only = true,
 	.word_size = 4,
-	.stride = 4,
+	.stride = 1,
 	.reg_read = mchp_otpc_read,
 };
 
diff --git a/include/dt-bindings/nvmem/microchip,sama7g5-otpc.h b/include/dt-bindings/nvmem/microchip,sama7g5-otpc.h
index f570b23165a2..5f72e75ad091 100644
--- a/include/dt-bindings/nvmem/microchip,sama7g5-otpc.h
+++ b/include/dt-bindings/nvmem/microchip,sama7g5-otpc.h
@@ -4,8 +4,8 @@
 #define _DT_BINDINGS_NVMEM_MICROCHIP_OTPC_H
 
 /*
- * Need to have it as a multiple of 4 as NVMEM memory is registered with
- * stride = 4.
+ * Need to have it as a multiple of 4 for the legacy id based packet
+ * access.
  */
 #define OTP_PKT(id)			((id) * 4)
 
-- 
2.34.1

[PATCH v5 10/17] nvmem: microchip-otpc: nvmem: add emulation mode and OTP access validation

[Varshini Rajendran]

Add validation of OTP memory accessibility and emulation mode status
during probe.

When the boot packet is not configured, emulation mode allows access to
the other packets. When both are not available an informational message
is logged to help with debugging.

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
---
 drivers/nvmem/microchip-otpc.c | 16 +++++++++++++++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/drivers/nvmem/microchip-otpc.c b/drivers/nvmem/microchip-otpc.c
index a17f82afdc37..6b0184423463 100644
--- a/drivers/nvmem/microchip-otpc.c
+++ b/drivers/nvmem/microchip-otpc.c
@@ -18,6 +18,7 @@
 #define MCHP_OTPC_CR_READ		BIT(6)
 #define MCHP_OTPC_MR			(0x4)
 #define MCHP_OTPC_MR_ADDR		GENMASK(31, 16)
+#define MCHP_OTPC_MR_EMUL		BIT(7)
 #define MCHP_OTPC_AR			(0x8)
 #define MCHP_OTPC_SR			(0xc)
 #define MCHP_OTPC_SR_READ		BIT(6)
@@ -343,7 +344,8 @@ static int mchp_otpc_probe(struct platform_device *pdev)
 {
 	struct nvmem_device *nvmem;
 	struct mchp_otpc *otpc;
-	u32 size;
+	bool emul_enable;
+	u32 size, mr_val;
 	int ret;
 
 	otpc = devm_kzalloc(&pdev->dev, sizeof(*otpc), GFP_KERNEL);
@@ -355,10 +357,22 @@ static int mchp_otpc_probe(struct platform_device *pdev)
 		return PTR_ERR(otpc->base);
 
 	otpc->dev = &pdev->dev;
+
+	mr_val = readl_relaxed(otpc->base + MCHP_OTPC_MR);
+	emul_enable = mr_val & MCHP_OTPC_MR_EMUL;
+	if (emul_enable)
+		dev_info(otpc->dev, "Emulation mode enabled\n");
+
 	ret = mchp_otpc_init_packets_list(otpc, &size);
 	if (ret)
 		return ret;
 
+	if (!size) {
+		dev_warn(otpc->dev, "Cannot access OTP memory\n");
+		if (!emul_enable)
+			dev_info(otpc->dev, "Boot packet not programmed and emulation mode disabled\n");
+	}
+
 	mchp_nvmem_config.dev = otpc->dev;
 	mchp_nvmem_config.add_legacy_fixed_of_cells = true;
 	mchp_nvmem_config.size = size;
-- 
2.34.1

[PATCH v5 11/17] ARM: dts: microchip: sama7d65: add cpu opps

[Varshini Rajendran]

Add CPU OPPs table for SAMA7D65.

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
---
 arch/arm/boot/dts/microchip/sama7d65.dtsi | 36 +++++++++++++++++++++++
 1 file changed, 36 insertions(+)

diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/microchip/sama7d65.dtsi
index ec200848c153..dfac17e34e65 100644
--- a/arch/arm/boot/dts/microchip/sama7d65.dtsi
+++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi
@@ -35,6 +35,7 @@ cpu0: cpu@0 {
 			d-cache-size = <0x8000>;	// L1, 32 KB
 			i-cache-size = <0x8000>;	// L1, 32 KB
 			next-level-cache = <&L2>;
+			operating-points-v2 = <&cpu_opp_table>;
 
 			L2: l2-cache {
 				compatible = "cache";
@@ -45,6 +46,41 @@ L2: l2-cache {
 		};
 	};
 
+	cpu_opp_table: opp-table {
+		compatible = "operating-points-v2";
+
+		opp-90000000 {
+			opp-hz = /bits/ 64 <90000000>;
+			opp-microvolt = <1050000 1050000 1225000>;
+			clock-latency-ns = <320000>;
+		};
+
+		opp-250000000 {
+			opp-hz = /bits/ 64 <250000000>;
+			opp-microvolt = <1050000 1050000 1225000>;
+			clock-latency-ns = <320000>;
+		};
+
+		opp-600000000 {
+			opp-hz = /bits/ 64 <600000000>;
+			opp-microvolt = <1050000 1050000 1225000>;
+			clock-latency-ns = <320000>;
+			opp-suspend;
+		};
+
+		opp-800000000 {
+			opp-hz = /bits/ 64 <800000000>;
+			opp-microvolt = <1150000 1125000 1225000>;
+			clock-latency-ns = <320000>;
+		};
+
+		opp-1000000002 {
+			opp-hz = /bits/ 64 <1000000002>;
+			opp-microvolt = <1250000 1225000 1300000>;
+			clock-latency-ns = <320000>;
+		};
+	};
+
 	clocks {
 		main_xtal: clock-mainxtal {
 			compatible = "fixed-clock";
-- 
2.34.1

[PATCH v5 12/17] ARM: dts: microchip: sama7d65: Add ADC node

[Varshini Rajendran]

Add node for the ADC controller in sama7d65 SoC. Add the vddout25 fixed
regulator node which provides the 2.5V reference voltage for the ADC.

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
---
 arch/arm/boot/dts/microchip/sama7d65.dtsi | 28 +++++++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/microchip/sama7d65.dtsi
index dfac17e34e65..c35f27615bc4 100644
--- a/arch/arm/boot/dts/microchip/sama7d65.dtsi
+++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi
@@ -11,6 +11,7 @@
 #include <dt-bindings/clock/at91.h>
 #include <dt-bindings/dma/at91.h>
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/iio/adc/at91-sama5d2_adc.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/mfd/at91-usart.h>
@@ -95,6 +96,15 @@ slow_xtal: clock-slowxtal {
 		};
 	};
 
+	vddout25: fixed-regulator-vddout25 {
+		compatible = "regulator-fixed";
+		regulator-name = "VDDOUT25";
+		regulator-min-microvolt = <2500000>;
+		regulator-max-microvolt = <2500000>;
+		regulator-boot-on;
+		status = "disabled";
+	};
+
 	ns_sram: sram@100000 {
 		compatible = "mmio-sram";
 		reg = <0x100000 0x20000>;
@@ -296,6 +306,24 @@ can4: can@e0838000 {
 			status = "disabled";
 		};
 
+		adc: adc@e1000000 {
+			compatible = "microchip,sama7d65-adc";
+			reg = <0xe1000000 0x200>;
+			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&pmc PMC_TYPE_GCK 25>;
+			clock-names = "adc_clk";
+			assigned-clocks = <&pmc PMC_TYPE_GCK 25>;
+			assigned-clock-rates = <100000000>;
+			dmas = <&dma0 AT91_XDMAC_DT_PERID(0)>;
+			dma-names = "rx";
+			#io-channel-cells = <1>;
+			atmel,min-sample-rate-hz = <200000>;
+			atmel,max-sample-rate-hz = <20000000>;
+			atmel,trigger-edge-type = <IRQ_TYPE_EDGE_RISING>;
+			atmel,startup-time-ms = <4>;
+			status = "disabled";
+		};
+
 		dma2: dma-controller@e1200000 {
 			compatible = "microchip,sama7d65-dma", "microchip,sama7g5-dma";
 			reg = <0xe1200000 0x1000>;
-- 
2.34.1

[PATCH v5 13/17] ARM: dts: microchip: sama7d65_curiosity: Enable ADC, DVFS

[Varshini Rajendran]

Enable ADC and DVFS on SAMA7D65 Curiosity board. Configure the necessary
power supply (vddana, vref) for the ADC, and enable cpu-supply for DVFS.

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
---
 .../dts/microchip/at91-sama7d65_curiosity.dts | 27 +++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts b/arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts
index 927c27260b6c..c2d1e5308170 100644
--- a/arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts
+++ b/arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts
@@ -79,6 +79,14 @@ reg_5v: regulator-5v {
 	};
 };
 
+&adc {
+	vddana-supply = <&vddout25>;
+	vref-supply = <&vddout25>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_adc_default &pinctrl_adtrg_default>;
+	status = "okay";
+};
+
 &can1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_can1_default>;
@@ -97,6 +105,10 @@ &can3 {
 	status = "okay";
 };
 
+&cpu0 {
+	cpu-supply = <&vddcpu>;
+};
+
 &dma0 {
 	status = "okay";
 };
@@ -334,6 +346,16 @@ &main_xtal {
 };
 
 &pioa {
+	pinctrl_adc_default: adc-default {
+		pinmux = <PIN_PC5__GPIO>;
+		bias-disable;
+	};
+
+	pinctrl_adtrg_default: adtrg-default {
+		pinmux = <PIN_PB7__ADTRG>;
+		bias-pull-up;
+	};
+
 	pinctrl_can1_default: can1-default {
 		pinmux = <PIN_PD10__CANTX1>,
 			 <PIN_PD11__CANRX1>;
@@ -457,3 +479,8 @@ input@0 {
 &slow_xtal {
 	clock-frequency = <32768>;
 };
+
+&vddout25 {
+	vin-supply = <&vdd_3v3>;
+	status = "okay";
+};
-- 
2.34.1

[PATCH v5 14/17] ARM: dts: microchip: sama7d65: add otpc node

[Varshini Rajendran]

Add OTPC node along with temperature calibration cell.

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
---
 arch/arm/boot/dts/microchip/sama7d65.dtsi | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/microchip/sama7d65.dtsi
index c35f27615bc4..aac2e22d96cb 100644
--- a/arch/arm/boot/dts/microchip/sama7d65.dtsi
+++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi
@@ -15,6 +15,7 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/mfd/at91-usart.h>
+#include <dt-bindings/nvmem/microchip,sama7g5-otpc.h>
 
 / {
 	model = "Microchip SAMA7D65 family SoC";
@@ -1111,6 +1112,21 @@ ddr3phy: ddr3phy@e3804000 {
 			reg = <0xe3804000 0x1000>;
 		};
 
+		otpc: efuse@e8c00000 {
+			compatible = "microchip,sama7d65-otpc", "microchip,sama7g5-otpc", "syscon";
+			reg = <0xe8c00000 0x100>;
+
+			nvmem-layout {
+				compatible = "fixed-layout";
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				temperature_calib: calib@41435354 {
+					reg = <0x41435354 0x2c>;	/* Temp calib data packet TAG */
+				};
+			};
+		};
+
 		gic: interrupt-controller@e8c11000 {
 			compatible = "arm,cortex-a7-gic";
 			reg = <0xe8c11000 0x1000>,
-- 
2.34.1

[PATCH v5 15/17] ARM: dts: microchip: sama7d65: add cells for temperature calibration

[Varshini Rajendran]

Add nvmem-cells for temperature calibration data to the ADC node.
The calibration data is read from the OTPC.

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
---
 arch/arm/boot/dts/microchip/sama7d65.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/microchip/sama7d65.dtsi
index aac2e22d96cb..a8b18ad0ef7f 100644
--- a/arch/arm/boot/dts/microchip/sama7d65.dtsi
+++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi
@@ -318,6 +318,8 @@ adc: adc@e1000000 {
 			dmas = <&dma0 AT91_XDMAC_DT_PERID(0)>;
 			dma-names = "rx";
 			#io-channel-cells = <1>;
+			nvmem-cells = <&temperature_calib>;
+			nvmem-cell-names = "temperature_calib";
 			atmel,min-sample-rate-hz = <200000>;
 			atmel,max-sample-rate-hz = <20000000>;
 			atmel,trigger-edge-type = <IRQ_TYPE_EDGE_RISING>;
-- 
2.34.1

[PATCH v5 16/17] ARM: dts: microchip: sama7d65: add temperature sensor

[Varshini Rajendran]

Add the generic-adc-thermal temperature sensor node for SAMA7D65.

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
---
 arch/arm/boot/dts/microchip/sama7d65.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/microchip/sama7d65.dtsi
index a8b18ad0ef7f..3aba73983c79 100644
--- a/arch/arm/boot/dts/microchip/sama7d65.dtsi
+++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi
@@ -119,6 +119,13 @@ pmu {
 		interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 	};
 
+	thermal_sensor: thermal-sensor {
+		compatible = "generic-adc-thermal";
+		#thermal-sensor-cells = <0>;
+		io-channels = <&adc AT91_SAMA7G5_ADC_TEMP_CHANNEL>;
+		io-channel-names = "sensor-channel";
+	};
+
 	soc {
 		compatible = "simple-bus";
 		ranges;
-- 
2.34.1

[PATCH v5 17/17] ARM: dts: microchip: sama7d65: add thermal zones node

[Varshini Rajendran]

Add thermal zones node for SAMA7D65 with trip points for passive
cooling and critical shutdown.

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
---
 arch/arm/boot/dts/microchip/sama7d65.dtsi | 42 +++++++++++++++++++++++
 1 file changed, 42 insertions(+)

diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/microchip/sama7d65.dtsi
index 3aba73983c79..7743f9e8f692 100644
--- a/arch/arm/boot/dts/microchip/sama7d65.dtsi
+++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi
@@ -16,6 +16,7 @@
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/mfd/at91-usart.h>
 #include <dt-bindings/nvmem/microchip,sama7g5-otpc.h>
+#include <dt-bindings/thermal/thermal.h>
 
 / {
 	model = "Microchip SAMA7D65 family SoC";
@@ -38,6 +39,7 @@ cpu0: cpu@0 {
 			i-cache-size = <0x8000>;	// L1, 32 KB
 			next-level-cache = <&L2>;
 			operating-points-v2 = <&cpu_opp_table>;
+			#cooling-cells = <2>; /* min followed by max */
 
 			L2: l2-cache {
 				compatible = "cache";
@@ -126,6 +128,46 @@ thermal_sensor: thermal-sensor {
 		io-channel-names = "sensor-channel";
 	};
 
+	thermal-zones {
+		cpu_thermal: cpu-thermal {
+			polling-delay-passive = <1000>;
+			polling-delay = <5000>;
+			thermal-sensors = <&thermal_sensor>;
+
+			trips {
+				cpu_normal: cpu-alert0 {
+					temperature = <90000>;
+					hysteresis = <0>;
+					type = "passive";
+				};
+
+				cpu_hot: cpu-alert1 {
+					temperature = <95000>;
+					hysteresis = <0>;
+					type = "passive";
+				};
+
+				cpu_critical: cpu-critical {
+					temperature = <100000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+
+			cooling-maps {
+				map0 {
+					trip = <&cpu_normal>;
+					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+
+				map1 {
+					trip = <&cpu_hot>;
+					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+		};
+	};
+
 	soc {
 		compatible = "simple-bus";
 		ranges;
-- 
2.34.1

Re: [PATCH v5 02/17] nvmem: add DEFINE_FREE for nvmem_cell_put cleanup

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] The `DEFINE_FREE(nvmem_cell_put, ...)` macro is missing from the `CONFIG_NVMEM=n` fallback block, causing compilation failures for drivers using it without NVMEM enabled.
--

--- Patch [2]: [PATCH v5 02/17] nvmem: add DEFINE_FREE for nvmem_cell_put cleanup ---
commit 2ebca04f3e1ae39d3b1c1039e736c5e4b6555c85
Author: Varshini Rajendran <varshini.rajendran@microchip.com>

nvmem: add DEFINE_FREE for nvmem_cell_put cleanup

Add cleanup.h helper for nvmem_cell_put() to enable automatic resource
cleanup using __free(nvmem_cell_put) annotation.

> diff --git a/include/linux/nvmem-consumer.h b/include/linux/nvmem-consumer.h
> index 34c0e58dfa266..35a2ea8b8957b 100644
> --- a/include/linux/nvmem-consumer.h
> +++ b/include/linux/nvmem-consumer.h
[ ... ]
> @@ -54,6 +55,9 @@ struct nvmem_cell *nvmem_cell_get(struct device *dev, const char *id);
>  struct nvmem_cell *devm_nvmem_cell_get(struct device *dev, const char *id);
>  void nvmem_cell_put(struct nvmem_cell *cell);
>  void devm_nvmem_cell_put(struct device *dev, struct nvmem_cell *cell);
> +
> +DEFINE_FREE(nvmem_cell_put, struct nvmem_cell *, if (!IS_ERR_OR_NULL(_T)) nvmem_cell_put(_T))
> +

[Severity: Low]
Will this cause compilation failures for drivers using the cleanup when
CONFIG_NVMEM is disabled?

Since this macro is defined exclusively inside the #if IS_ENABLED(CONFIG_NVMEM)
block, it appears to be missing from the fallback #else block. Moving it
outside the #if / #else blocks would make it universally available and prevent
build issues when drivers use __free(nvmem_cell_put) without NVMEM enabled.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260804113338.261782-1-varshini.rajendran@microchip.com?part=2

Re: [PATCH v5 05/17] iio: adc: at91-sama5d2_adc: add condition to validate calibration data

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:

Pre-existing issues:
- [High] Missing cancel_work_sync() in at91_adc_probe() error paths causes a Use-After-Free if the probe fails after an interrupt schedules the work.
--

--- Patch [5]: [PATCH v5 05/17] iio: adc: at91-sama5d2_adc: add condition to validate calibration data ---
commit 380f9b2fd1800d246c63262001982d55d2628987
Author: Varshini Rajendran <varshini.rajendran@microchip.com>

iio: adc: at91-sama5d2_adc: add condition to validate calibration data

This commit adds an additional condition to validate the calibration data
read from the nvmem cell. It checks the tag of the packet to ensure the
data is valid before proceeding.

> diff --git a/drivers/iio/adc/at91-sama5d2_adc.c b/drivers/iio/adc/at91-sama5d2_adc.c
> index 82db8f2f4db03..5b21367cf6b40 100644
> --- a/drivers/iio/adc/at91-sama5d2_adc.c
> +++ b/drivers/iio/adc/at91-sama5d2_adc.c
> @@ -2297,7 +2297,8 @@ static int at91_adc_temp_sensor_init(struct at91_adc_state *st,
>  		return dev_err_probe(dev, PTR_ERR(buf),
>  				     "Failed to read calibration data!\n");
>  
> -	if (len < layout->min_len * sizeof(*buf)) {
> +	if (len < layout->min_len * sizeof(*buf) ||
> +	    buf[layout->tag_idx] != AT91_TEMP_CALIB_TAG_ACST) {

[Severity: High]
This isn't a bug introduced by this patch, but missing cancel_work_sync() in
the error paths of at91_adc_probe() can cause a use-after-free.

If the hardware interrupt is left asserted by a prior boot stage,
devm_request_irq() unmasks it before the device is reset in
at91_adc_hw_init().

The interrupt handler at91_adc_interrupt() can then run, hit the touch sense
condition, and call schedule_work().

If a subsequent initialization step in probe() fails, the probe aborts:

drivers/iio/adc/at91-sama5d2_adc.c:at91_adc_probe() {
    ...
	ret = clk_prepare_enable(st->per_clk);
	if (ret)
		goto vref_disable;
    ...
vref_disable:
	regulator_disable(st->vref);
reg_disable:
	regulator_disable(st->reg);
	return ret;
}

This implicitly frees devres allocated memory without canceling the pending
work, allowing the work to execute after st is freed.

Should there be a call to cancel_work_sync() to clear the pending work in the
error paths here?

>  		dev_err(dev, "Invalid calibration data!\n");
>  		return -EINVAL;
>  	}

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260804113338.261782-1-varshini.rajendran@microchip.com?part=5

Re: [PATCH v5 04/17] iio: adc: at91-sama5d2_adc: rework temp calibration layout handling

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The calibration data tag is defined and its layout index is configured, but it is never checked against the NVMEM data.
--

--- Patch [4]: [PATCH v5 04/17] iio: adc: at91-sama5d2_adc: rework temp calibration layout handling ---
commit 49b1bddcd8cc36f48960bba2752d5b3937516cd8
Author: Varshini Rajendran <varshini.rajendran@microchip.com>

iio: adc: at91-sama5d2_adc: rework temp calibration layout handling

Extend support to handle different temperature calibration layouts. Add a
temperature calibration data layout structure to describe indexes of the
factors P1, P4, P6, tag, minimum length of the packet and the scaling
factors for P1 (p1_scale) which are SoC-specific instead of the older non
scalable id structure.

> diff --git a/drivers/iio/adc/at91-sama5d2_adc.c b/drivers/iio/adc/at91-sama5d2_adc.c
> index 09390f082fc48..82db8f2f4db03 100644
> --- a/drivers/iio/adc/at91-sama5d2_adc.c
> +++ b/drivers/iio/adc/at91-sama5d2_adc.c
[ ... ]
> @@ -444,6 +445,27 @@ static const struct at91_adc_reg_layout sama7g5_layout = {
>  #define at91_adc_writel(st, reg, val)					\
>  	writel_relaxed(val, (st)->base + (st)->soc_info.platform->layout->reg)
>  
> +/* Temperature calibration tag "ACST" in ASCII */
> +#define AT91_TEMP_CALIB_TAG_ACST	0x41435354
> +
> +/**
> + * struct at91_adc_temp_calib_layout - temperature calibration packet layout
> + * @tag_idx:	index of Packet tag in the NVMEM cell buffer
> + * @p1_idx:	index of FT1_TEMP, equivalent to P1 in the NVMEM cell buffer
> + * @p4_idx:	index of FT1_VPAT, equivalent to P4 in the NVMEM cell buffer
> + * @p6_idx:	index of FT2_VBG, equivalent to P6 in the NVMEM cell buffer
> + * @min_len:	minimum number of u32 words expected in the NVMEM cell buffer
> + * @p1_scale:	scaling factor applied to P1 to convert to millicelcius
> + */
> +struct at91_adc_temp_calib_layout {
> +	unsigned int tag_idx;
> +	unsigned int p1_idx;
> +	unsigned int p4_idx;
> +	unsigned int p6_idx;
> +	unsigned int min_len;
> +	struct u32_fract p1_scale;
> +};
> +
[ ... ]
> @@ -2270,20 +2297,23 @@ static int at91_adc_temp_sensor_init(struct at91_adc_state *st,
>  		return dev_err_probe(dev, PTR_ERR(buf),
>  				     "Failed to read calibration data!\n");
>  
> -	if (len < AT91_ADC_TS_CLB_IDX_MAX * sizeof(*buf)) {
> +	if (len < layout->min_len * sizeof(*buf)) {

[Severity: Medium]
Should there be a check here to validate the packet tag?

The commit defines AT91_TEMP_CALIB_TAG_ACST and adds tag_idx to the layout
struct, but they do not appear to be used to validate the NVMEM buffer
content before it is parsed.

>  		dev_err(dev, "Invalid calibration data!\n");
>  		return -EINVAL;
>  	}

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260804113338.261782-1-varshini.rajendran@microchip.com?part=4

Re: [PATCH v5 07/17] iio: adc: at91-sama5d2_adc: adapt the driver for sama7d65

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Incorrect scaling factor `p1_scale` for sama7d65 temperature calibration data, likely due to swapped numerator and denominator.
--

--- Patch [7]: [PATCH v5 07/17] iio: adc: at91-sama5d2_adc: adapt the driver for sama7d65 ---
commit ea05a7089eb84578f2d6135b1c963b5c2be91fdd
Author: Varshini Rajendran <varshini.rajendran@microchip.com>

iio: adc: at91-sama5d2_adc: adapt the driver for sama7d65

Add support for sama7d65 ADC. The differences are highlighted with the
compatible. The calibration data layout is the main difference.

Update Kconfig help text to mention SAMA7 SoC family support.

> diff --git a/drivers/iio/adc/at91-sama5d2_adc.c b/drivers/iio/adc/at91-sama5d2_adc.c
> --- a/drivers/iio/adc/at91-sama5d2_adc.c
> +++ b/drivers/iio/adc/at91-sama5d2_adc.c

[ ... ]

> @@ -528,6 +528,15 @@ static const struct at91_adc_temp_calib_layout sama7g5_temp_calib = {
>  	.p1_scale = { .numerator = 1000, .denominator = 1 },
>  };
>  
> +static const struct at91_adc_temp_calib_layout sama7d65_temp_calib = {
> +	.tag_idx = 1,
> +	.p1_idx = 3,
> +	.p4_idx = 2,
> +	.p6_idx = 5,
> +	.min_len = 11,
> +	.p1_scale = { .numerator = 1, .denominator = 1000 },
> +};

[Severity: High]
Is this scale correct for the p1 value?

In at91_adc_temp_sensor_init(), the calibration value is scaled like this:

clb->p1 /= layout->p1_scale.denominator;

With a denominator of 1000, the raw NVMEM calibration value will be divided
by 1000. Later in at91_adc_read_temp(), this scaled p1 value is added
directly to a milli-Celsius delta.

If the NVMEM stores p1 in Celsius (like it does for SAMA7G5), dividing by
1000 yields 0 due to integer truncation. If it is already in milli-Celsius,
dividing by 1000 converts it back to Celsius. In either case, adding Celsius
or 0 to a milli-Celsius delta results in an incorrect temperature reading.

Could the numerator and denominator have been accidentally swapped here?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260804113338.261782-1-varshini.rajendran@microchip.com?part=7

Re: [PATCH v5 08/17] dt-bindings: nvmem: microchip,sama7g5-otpc: add sama7d65 and dt node example

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The device tree node example incorrectly uses a 32-bit TAG (0x41435354) as the `reg` offset in a `fixed-layout`, which violates the static byte offset semantics of `fixed-layout` and will cause immediate runtime driver failures if copied.
--

--- Patch [8]: [PATCH v5 08/17] dt-bindings: nvmem: microchip,sama7g5-otpc: add sama7d65 and dt node example ---
commit f1d25062b84ac824ea90292adfefcc0c472e00d6
Author: Varshini Rajendran <varshini.rajendran@microchip.com>

dt-bindings: nvmem: microchip,sama7g5-otpc: add sama7d65 and dt node example

This commit adds support for the sama7d65 variant and includes a device tree
node example demonstrating how a tag can be used to reference a packet stored
in the OTP memory.

> diff --git a/Documentation/devicetree/bindings/nvmem/microchip,sama7g5-otpc.yaml b/Documentation/devicetree/bindings/nvmem/microchip,sama7g5-otpc.yaml
> --- a/Documentation/devicetree/bindings/nvmem/microchip,sama7g5-otpc.yaml
> +++ b/Documentation/devicetree/bindings/nvmem/microchip,sama7g5-otpc.yaml
[ ... ]
> @@ -48,4 +54,20 @@ examples:
>          };
>      };
>  
> +  - |
> +    efuse@e8c00000 {
> +        compatible = "microchip,sama7d65-otpc", "microchip,sama7g5-otpc", "syscon";
> +        reg = <0xe8c00000 0x100>;
> +
> +        nvmem-layout {
> +            compatible = "fixed-layout";
> +            #address-cells = <1>;
> +            #size-cells = <1>;
> +
> +            calib@41435354 {
> +                reg = <0x41435354 0x2c>;    /* Temp calib data packet TAG */

[Severity: Medium]
Will this configuration cause a regression where drivers fail to initialize at
runtime if downstream developers follow the example?

The generic fixed-layout binding strictly interprets the reg property as a
static physical byte offset, rather than a tag.

If a consumer attempts to read this cell at runtime, the NVMEM generic parser
will pass 0x41435354 as the physical byte offset. When mchp_otpc_read()
calculates the packet ID using offset / 4, it results in an out-of-bounds ID
of 273732821. This exceeds the controller's maximum packet count, causing the
bounds check to fail and immediately reject the read with -EINVAL.

Is there a different layout compatible string intended for tag-based lookups?

> +            };
> +        };
> +    };
>  
>  ...

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260804113338.261782-1-varshini.rajendran@microchip.com?part=8

Re: [PATCH v5 10/17] nvmem: microchip-otpc: nvmem: add emulation mode and OTP access validation

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:

Pre-existing issues:
- [High] Missing locking in NVMEM read operations.
--

--- Patch [10]: [PATCH v5 10/17] nvmem: microchip-otpc: nvmem: add emulation mode and OTP access validation ---
commit ff3ee8b6ff65c931c28481b3cf9aabc752c44762
Author: Varshini Rajendran <varshini.rajendran@microchip.com>

nvmem: microchip-otpc: nvmem: add emulation mode and OTP access validation

This commit adds validation of OTP memory accessibility and emulation mode
status during driver probe. It allows access to other packets when the boot
packet is not configured, and logs an informational message if neither is
available to assist with debugging.

> diff --git a/drivers/nvmem/microchip-otpc.c b/drivers/nvmem/microchip-otpc.c
> index a17f82afdc37d..6b0184423463e 100644
> --- a/drivers/nvmem/microchip-otpc.c
> +++ b/drivers/nvmem/microchip-otpc.c
> @@ -18,6 +18,7 @@
>  #define MCHP_OTPC_CR_READ		BIT(6)
>  #define MCHP_OTPC_MR			(0x4)
>  #define MCHP_OTPC_MR_ADDR		GENMASK(31, 16)
> +#define MCHP_OTPC_MR_EMUL		BIT(7)

[Severity: High]
This is a pre-existing issue, but does mchp_otpc_read() need serialization
to prevent concurrent hardware accesses from corrupting the read address?

Since this sysfs nvmem attribute defaults to world-readable, multiple
unprivileged userspace processes can read from the device concurrently.

If they do, they can race in mchp_otpc_prepare_read() when modifying the
Memory Register and Control Register:

mchp_otpc_read() {
        ...
        ret = mchp_otpc_prepare_read(otpc, offset);
        ...
}

mchp_otpc_prepare_read() {
        ...
        /* Set address. */
        tmp = readl_relaxed(otpc->base + MCHP_OTPC_MR);
        tmp &= ~MCHP_OTPC_MR_ADDR;
        tmp |= FIELD_PREP(MCHP_OTPC_MR_ADDR, offset);
        writel_relaxed(tmp, otpc->base + MCHP_OTPC_MR);
        ...
}

Could concurrent reads overwrite each other's requested addresses, leading
to incorrect OTP data being read or stalling the controller?

[ ... ]

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260804113338.261782-1-varshini.rajendran@microchip.com?part=10

Re: [PATCH v5 09/17] nvmem: microchip-otpc: nvmem: microchip-otpc: add tag-based packet lookup

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 6 potential issue(s) to consider:

New issues:
- [Medium] TAG-based packet reads fail to bound the requested bytes to the actual packet length, leaking adjacent OTP packets.

Pre-existing issues:
- [High] Concurrent OTP reads cause a hardware race condition on OTP registers without locking.
- [High] Using `readl_relaxed()` for a FIFO data stream causes data corruption on big-endian systems.
- [High] Global static struct `mchp_nvmem_config` is dynamically modified in probe, causing a data race if multiple devices are probed.
- [High] Mismatch between logical size tracking and physical offset causes out-of-bounds hardware reads during probe.
- [High] Incorrect arguments passed to read_poll_timeout(), with sleep_us significantly larger than timeout_us.
--

--- Patch [9]: [PATCH v5 09/17] nvmem: microchip-otpc: nvmem: microchip-otpc: add tag-based packet lookup ---
commit e6e6046319784f7ce1cf86169392921f7f8bb397
Author: Varshini Rajendran <varshini.rajendran@microchip.com>

nvmem: microchip-otpc: nvmem: microchip-otpc: add tag-based packet lookup

This commit adds support for accessing OTP packets by their FourCC tag,
preserving backward compatibility with ID-based lookup. The driver supports
both legacy ID-based offsets and TAG-based offsets by reading and caching
packet metadata during probe. The nvmem stride is also set to 1 to enable
tag-based access.

> diff --git a/drivers/nvmem/microchip-otpc.c b/drivers/nvmem/microchip-otpc.c
> index df979e8549fdb..a17f82afdc37d 100644
> --- a/drivers/nvmem/microchip-otpc.c
> +++ b/drivers/nvmem/microchip-otpc.c
[ ... ]
> @@ -140,8 +190,29 @@ static int mchp_otpc_prepare_read(struct mchp_otpc *otpc,
>   * offset returned by hardware.
>   *
>   * For this, the read function will return the first requested bytes in the
> - * packet. The user will have to be aware of the memory footprint before doing
> - * the read request.

[Severity: High]
This is a pre-existing issue, but are the arguments passed to
read_poll_timeout() in mchp_otpc_prepare_read() correct?

	return read_poll_timeout(readl_relaxed, tmp, !(tmp & MCHP_OTPC_SR_READ),
				 10000, 2000, false, otpc->base + MCHP_OTPC_SR);

The sleep_us parameter is set to 10000 (10ms) while timeout_us is set to 2000
(2ms). Since the sleep time is 5x larger than the total timeout, won't this
instantly return a timeout error on the first sleep cycle if the hardware isn't
immediately ready?

> + * packet.
[ ... ]
> @@ -154,12 +225,11 @@ static int mchp_otpc_read(void *priv, unsigned int off, void *val,
>  	int ret, payload_size;
>  
>  	/*
> -	 * We reach this point with off being multiple of stride = 4 to
> -	 * be able to cross the subsystem. Inside the driver we use continuous
> -	 * unsigned integer numbers for packet id, thus divide off by 4
> -	 * before passing it to mchp_otpc_id_to_packet().
> +	 * From this point the offset has to be translated into the actual
> +	 * packet. For this we traverse the table of contents stored in a list
> +	 * "packet" based on the access type - packet id or tag.
>  	 */
> -	packet = mchp_otpc_id_to_packet(otpc, off / 4);
> +	packet = mchp_otpc_resolve_packet(otpc, off);
>  	if (!packet)
>  		return -EINVAL;
>  	offset = packet->offset;

[Severity: High]
This is a pre-existing issue, but can concurrent OTP reads cause a hardware race
condition?

Looking at mchp_otpc_read(), there is an outer loop that accesses the hardware:

	while (len < bytes) {
		ret = mchp_otpc_prepare_read(otpc, offset);

When multiple consumers call nvmem_device_read() concurrently,
mchp_otpc_prepare_read() modifies global hardware registers without locking:

	writel_relaxed(tmp, otpc->base + MCHP_OTPC_MR);
	...
	writel_relaxed(tmp, otpc->base + MCHP_OTPC_CR);

Could this clobber the hardware state machine and lead to unpredictable
behavior?


[Severity: High]
This is a pre-existing issue, but does using readl_relaxed() for the FIFO data
stream cause data corruption on big-endian systems?

When reading the payload content in mchp_otpc_read():

		do {
			*buf++ = readl_relaxed(otpc->base + MCHP_OTPC_DR);
			len += sizeof(*buf);
			offset++;
			payload_size--;
		} while (payload_size >= 0 && len < bytes);

The readl_relaxed() macro performs an implicit CPU-to-little-endian byte swap
on big-endian architectures. Should a stream accessor be used instead to
preserve the byte order between the device and memory?


[Severity: Medium]
Does TAG-based packet reading fail to bound the requested bytes to the actual
packet length, leading to a leak of adjacent OTP packets?

If a client requests a read size larger than the actual packet payload, the
inner loop in mchp_otpc_read() exits when the payload size is exhausted:

		do {
			*buf++ = readl_relaxed(otpc->base + MCHP_OTPC_DR);
			len += sizeof(*buf);
			offset++;
			payload_size--;
		} while (payload_size >= 0 && len < bytes);

However, if len is still less than bytes, the outer while (len < bytes) loop
will continue and issue new hardware reads for the next sequential packet.
Could this undermine the packet-based access abstraction by returning adjacent
packet data?

[ ... ]
> @@ -215,6 +300,20 @@ static int mchp_otpc_init_packets_list(struct mchp_otpc *otpc, u32 *size)
>  
>  		packet->id = id++;
>  		packet->offset = word_pos;
> +		type = FIELD_GET(MCHP_OTPC_HR_PACKET, word);
> +
> +		if (type == MCHP_OTPC_HR_PACKET_REGULAR) {
> +			ret = mchp_otpc_read_packet_tag(otpc, packet->offset,
> +							&packet->tag);
> +			if (ret)
> +				return ret;
> +
> +			if (!mchp_otpc_is_valid_fourcc(packet->tag))
> +				packet->tag = 0;
> +		} else {
> +			packet->tag = 0;
> +		}
> +

[Severity: High]
This is a pre-existing issue, but does a mismatch between the logical size
tracking and the physical offset cause out-of-bounds hardware reads during
probe?

In mchp_otpc_init_packets_list(), the loop increments the size and word_pos:

		/* Count size by adding header and paload sizes. */
		*size += 4 * (payload_size + 1);
		/* Next word: this packet (header, payload) position + 1. */
		word_pos += payload_size + 2;

The size pointer increments by 4 * (payload_size + 1) bytes, while word_pos
increments by payload_size + 2 words (which is 4 * (payload_size + 2) bytes).
Because word_pos grows faster than size, could word_pos exceed the hardware
limits before size reaches MCHP_OTPC_SIZE, causing mchp_otpc_prepare_read() to
poll invalid hardware offsets?

[ ... ]
> @@ -236,7 +335,7 @@ static struct nvmem_config mchp_nvmem_config = {
>  	.type = NVMEM_TYPE_OTP,
>  	.read_only = true,
>  	.word_size = 4,
> -	.stride = 4,
> +	.stride = 1,
>  	.reg_read = mchp_otpc_read,
>  };

[Severity: High]
This isn't a bug introduced by this patch, but does modifying the global static
mchp_nvmem_config struct during probe cause a data race?

In mchp_otpc_probe(), the shared global struct is dynamically modified:

	mchp_nvmem_config.dev = otpc->dev;
	mchp_nvmem_config.add_legacy_fixed_of_cells = true;
	mchp_nvmem_config.size = size;
	mchp_nvmem_config.priv = otpc;

If multiple instances of the mchp-otpc driver are probed concurrently, could
this result in invalid private data pointers being registered with the nvmem
core?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260804113338.261782-1-varshini.rajendran@microchip.com?part=9

Re: [PATCH v5 12/17] ARM: dts: microchip: sama7d65: Add ADC node

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] The `vddout25` regulator node uses a deprecated node name pattern (`fixed-regulator-vddout25`) that violates devicetree standards.
--

--- Patch [12]: [PATCH v5 12/17] ARM: dts: microchip: sama7d65: Add ADC node ---
commit 1acc23759ae718683d0ee0863abd37a91d3f243a
Author: Varshini Rajendran <varshini.rajendran@microchip.com>

ARM: dts: microchip: sama7d65: Add ADC node

Add node for the ADC controller in sama7d65 SoC. Add the vddout25 fixed
regulator node which provides the 2.5V reference voltage for the ADC.

> diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/microchip/sama7d65.dtsi
> index dfac17e34e651..c35f27615bc49 100644
> --- a/arch/arm/boot/dts/microchip/sama7d65.dtsi
> +++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi

[ ... ]

> @@ -95,6 +96,15 @@ slow_xtal: clock-slowxtal {
>  		};
>  	};
>  
> +	vddout25: fixed-regulator-vddout25 {

[Severity: Low]
Does this node name trigger dtbs_check warnings? The naming pattern
fixed-regulator-* falls under the deprecated path in fixed-regulator.yaml,
which prefers names matching ^regulator(-[0-9]+v[0-9]+|-[0-9a-z-]+)?$.

> +		compatible = "regulator-fixed";
> +		regulator-name = "VDDOUT25";
> +		regulator-min-microvolt = <2500000>;
> +		regulator-max-microvolt = <2500000>;
> +		regulator-boot-on;
> +		status = "disabled";
> +	};

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260804113338.261782-1-varshini.rajendran@microchip.com?part=12

Re: [PATCH v5 11/17] ARM: dts: microchip: sama7d65: add cpu opps

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Missing `cpu-supply` property in the board device tree leads to CPU undervolting and system crash.
--

--- Patch [11]: [PATCH v5 11/17] ARM: dts: microchip: sama7d65: add cpu opps ---
commit fc836a1a8220dc67fbc068b60857dc5200abf5d0
Author: Varshini Rajendran <varshini.rajendran@microchip.com>

ARM: dts: microchip: sama7d65: add cpu opps

This commit adds the CPU operating performance points (OPP) table for the
SAMA7D65 SoC. It links the OPP table to the cpu0 node, enabling dynamic
frequency scaling for the CPU.

> diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/microchip/sama7d65.dtsi
> index ec200848c153f..dfac17e34e651 100644
> --- a/arch/arm/boot/dts/microchip/sama7d65.dtsi
> +++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi
> @@ -35,6 +35,7 @@ cpu0: cpu@0 {
>  			d-cache-size = <0x8000>;	// L1, 32 KB
>  			i-cache-size = <0x8000>;	// L1, 32 KB
>  			next-level-cache = <&L2>;
> +			operating-points-v2 = <&cpu_opp_table>;

[Severity: High]
Will this cause the system to crash due to CPU undervolting during frequency
scaling?

Adding the operating-points-v2 property activates the cpufreq-dt driver.
However, the board device tree (at91-sama7d65_curiosity.dts) appears to be
missing a cpu-supply property for the cpu0 node to link it with the PMIC
regulator.

The cpufreq-dt driver gracefully tolerates missing regulators and will
proceed to dynamically scale the CPU frequency based on load. When the
frequency is raised (for example, to 1GHz, which requires 1.25V), the PMIC
voltage will remain at its default boot value.

Does the cpu0 node in the board file need to be updated with cpu-supply
to ensure the voltage scales safely alongside the frequency?

[ ... ]

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260804113338.261782-1-varshini.rajendran@microchip.com?part=11

Re: [PATCH v5 15/17] ARM: dts: microchip: sama7d65: add cells for temperature calibration

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:

New issues:
- [Low] The 'nvmem-cells' and 'nvmem-cell-names' properties are used in the ADC device tree node, but are not declared in the corresponding DT bindings schema.

Pre-existing issues:
- [High] The ADC driver silently swallows -EPROBE_DEFER from nvmem_cell_get(), which permanently drops the temperature sensor if the OTP controller probes later.
--

--- Patch [15]: [PATCH v5 15/17] ARM: dts: microchip: sama7d65: add cells for temperature calibration ---
commit a38951f8e3bfd0ea10718735901a2bfeb4e17375
Author: Varshini Rajendran <varshini.rajendran@microchip.com>

ARM: dts: microchip: sama7d65: add cells for temperature calibration

This commit adds nvmem-cells for temperature calibration data to the ADC
node. The calibration data is read from the OTPC.

> diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/microchip/sama7d65.dtsi
> index aac2e22d96cb3..a8b18ad0ef7f7 100644
> --- a/arch/arm/boot/dts/microchip/sama7d65.dtsi
> +++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi
> @@ -318,6 +318,8 @@ adc: adc@e1000000 {
>  			dmas = <&dma0 AT91_XDMAC_DT_PERID(0)>;
>  			dma-names = "rx";
>  			#io-channel-cells = <1>;
> +			nvmem-cells = <&temperature_calib>;
> +			nvmem-cell-names = "temperature_calib";

[Severity: Low]
Will this cause dtbs_check validation to fail? The atmel,sama5d2-adc.yaml
bindings specify additionalProperties: false, but the nvmem-cells and
nvmem-cell-names properties don't appear to be declared in the schema.

[Severity: High]
This is a pre-existing issue, but won't adding these DT properties expose a
probe deferral race condition in the driver?

If the OTP controller hasn't probed yet, nvmem_cell_get() returns
-EPROBE_DEFER, which gets swallowed here in at91_adc_probe():

drivers/iio/adc/at91-sama5d2_adc.c:at91_adc_probe() {
    ...
    ret = at91_adc_temp_sensor_init(st, &pdev->dev);
    /* Don't register temperature channel if initialization failed. */
    if (ret)
        num_channels = st->soc_info.platform->max_channels - 1;
    else
        num_channels = st->soc_info.platform->max_channels;
    ...
}

Does this mean the temperature sensor hardware feature could be permanently
lost on boots where the ADC driver is probed before the OTP controller?

>  			atmel,min-sample-rate-hz = <200000>;
>  			atmel,max-sample-rate-hz = <20000000>;
>  			atmel,trigger-edge-type = <IRQ_TYPE_EDGE_RISING>;

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260804113338.261782-1-varshini.rajendran@microchip.com?part=15

Re: [PATCH v5 14/17] ARM: dts: microchip: sama7d65: add otpc node

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] Unused dt-bindings header included in sama7d65.dtsi
--

--- Patch [14]: [PATCH v5 14/17] ARM: dts: microchip: sama7d65: add otpc node ---
commit 2c133d1669c4d7c5ae4cff5a6ba5a348f2ab2163
Author: Varshini Rajendran <varshini.rajendran@microchip.com>

ARM: dts: microchip: sama7d65: add otpc node
    
Add OTPC node along with temperature calibration cell.

> diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/microchip/sama7d65.dtsi
> index c35f27615bc49..aac2e22d96cb3 100644
> --- a/arch/arm/boot/dts/microchip/sama7d65.dtsi
> +++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi
> @@ -15,6 +15,7 @@
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
>  #include <dt-bindings/interrupt-controller/irq.h>
>  #include <dt-bindings/mfd/at91-usart.h>
> +#include <dt-bindings/nvmem/microchip,sama7g5-otpc.h>

[Severity: Low]
This isn't a bug, but is this include necessary? It looks like the temperature
calibration data node uses a direct FourCC TAG address instead of any macros
that might be provided by this header.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260804113338.261782-1-varshini.rajendran@microchip.com?part=14

Re: [PATCH v5 16/17] ARM: dts: microchip: sama7d65: add temperature sensor

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] The newly added generic-adc-thermal sensor node lacks a corresponding `thermal-zones` node, causing a guaranteed probe failure on boot.
--

--- Patch [16]: [PATCH v5 16/17] ARM: dts: microchip: sama7d65: add temperature sensor ---
commit 1087474b952d46f446e7e1f6bb9fb653933e7ada
Author: Varshini Rajendran <varshini.rajendran@microchip.com>

ARM: dts: microchip: sama7d65: add temperature sensor

This commit adds a generic-adc-thermal temperature sensor node to the
SAMA7D65 device tree.

> diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/microchip/sama7d65.dtsi
> --- a/arch/arm/boot/dts/microchip/sama7d65.dtsi
> +++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi

[ ... ]

> @@ -119,6 +119,13 @@ pmu {
>  		interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
>  	};
>  
> +	thermal_sensor: thermal-sensor {
> +		compatible = "generic-adc-thermal";
> +		#thermal-sensor-cells = <0>;
> +		io-channels = <&adc AT91_SAMA7G5_ADC_TEMP_CHANNEL>;
> +		io-channel-names = "sensor-channel";
> +	};

[Severity: High]
Will this generic-adc-thermal node fail to probe during boot because a
corresponding thermal-zones node is missing from the device tree?

When gadc_thermal_probe() runs, it calls devm_thermal_of_zone_register(),
which relies on of_thermal_zone_find() to parse the device tree for a
thermal-zones node. 

Since this commit adds the sensor but omits the thermal-zones definition,
does this cause the lookup to unconditionally return -ENODEV and abort the
probe with a Thermal zone sensor register failed: -19 error log?

> +
>  	soc {
>  		compatible = "simple-bus";
>  		ranges;

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260804113338.261782-1-varshini.rajendran@microchip.com?part=16

Re: [PATCH v5 02/17] nvmem: add DEFINE_FREE for nvmem_cell_put cleanup

[Jonathan Cameron]

On Tue, 4 Aug 2026 17:03:23 +0530
Varshini Rajendran <varshini.rajendran@microchip.com> wrote:

> Add cleanup.h helper for nvmem_cell_put() to enable automatic resource
> cleanup using __free(nvmem_cell_put) annotation.
> 
> Use IS_ERR_OR_NULL() since nvmem_cell_get() can return error pointers,
> and passing an ERR_PTR to nvmem_cell_put() would cause issues.
> 
> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
https://sashiko.dev/#/patchset/20260804113338.261782-1-varshini.rajendran%40microchip.com
Has a question about whether this should be available when
!CONFIG_NVMEM

Seems like a reasonable suggestion to me given nvmem_cell_put() is stubbed
out.

Jonathan

> ---
>  include/linux/nvmem-consumer.h | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/include/linux/nvmem-consumer.h b/include/linux/nvmem-consumer.h
> index 34c0e58dfa26..35a2ea8b8957 100644
> --- a/include/linux/nvmem-consumer.h
> +++ b/include/linux/nvmem-consumer.h
> @@ -9,6 +9,7 @@
>  #ifndef _LINUX_NVMEM_CONSUMER_H
>  #define _LINUX_NVMEM_CONSUMER_H
>  
> +#include <linux/cleanup.h>
>  #include <linux/err.h>
>  #include <linux/errno.h>
>  #include <linux/notifier.h>
> @@ -54,6 +55,9 @@ struct nvmem_cell *nvmem_cell_get(struct device *dev, const char *id);
>  struct nvmem_cell *devm_nvmem_cell_get(struct device *dev, const char *id);
>  void nvmem_cell_put(struct nvmem_cell *cell);
>  void devm_nvmem_cell_put(struct device *dev, struct nvmem_cell *cell);
> +
> +DEFINE_FREE(nvmem_cell_put, struct nvmem_cell *, if (!IS_ERR_OR_NULL(_T)) nvmem_cell_put(_T))
> +
>  void *nvmem_cell_read(struct nvmem_cell *cell, size_t *len);
>  int nvmem_cell_write(struct nvmem_cell *cell, void *buf, size_t len);
>  int nvmem_cell_read_u8(struct device *dev, const char *cell_id, u8 *val);

Re: [PATCH v5 00/17] Add thermal management support for sama7d65

[Jonathan Cameron]

On Tue, 4 Aug 2026 17:03:21 +0530
Varshini Rajendran <varshini.rajendran@microchip.com> wrote:

> Thermal management system of sama7d65 includes:
> 
> - Temperature sensor as a part of ADC channel
> - Temperature calibration data retrieved from the OTP memory for
>   improved accuracy of the readings
> - DVFS implementation
> - Thermal system with DVFS as cooling cell.

Whilst to me this looks nearly ready to go upstream, I'm sorry to say
we are very late in the cycle, so chances are now pretty low.
If all seems fine I'll queue it up early next cycle though and so it
shouldn't be too long before you see it in linux next.

Jonathan

> 
> This patch series adds support for the following:
> 
> - Tag-based packet lookup for the NVMEM OTPC driver while preserving
>   backward compatibility with existing ID-based access
> - Temperature calibration layout handling in the ADC driver to support
>   different SoC-specific calibration data formats
> - ADC driver adaptation for sama7d65
> - DT nodes for OTP, ADC, temperature sensor, and thermal zones for
>   sama7d65
> 
> Changes in v5:
> 	- Placed the DEFINE_FREE helper in the header file and added it as a
> 	  new commit
> 	- Added IS_ERR_OR_NULL(_T) condition to the DEFINE_FREE of nvmem_cell_put
> 	- Reorder signing tags alphabetically in Patch 1
> 	- Kept the changes minimal by retaining ret variable
> 	- Collected the Rb tags
> 
> Link to v4: https://lore.kernel.org/lkml/20260727122633.117435-1-varshini.rajendran@microchip.com/
> 
> Changes in v4:
> 	- Reworked cleanup.h usage: define and assign __free() variables at point
> 	  of use after early returns, add DEFINE_FREE(nvmem_cell_put, ...) for
> 	  nvmem_cell cleanup
> 	- Split patch 3/13 into two: refactoring (layout struct) and tag validation
> 	- Used struct u32_fract for p1 scaling factors
> 	- Return -ENODEV instead of -EINVAL when layout is missing
> 	- New precursor patch to remove unnecessary casts in of_device_id
> 	- Removed trailing comma from single-line initializer array
> 	- Moved emulation mode validation into a separate patch
> 	- Added FourCC validation for packet tags; invalid tags fall back to ID-only
> 	  access
> 	- Mentioned FourCC in commit message and comments
> 	- Used intermediate variable for off % 4
> 	- Rename tmp → mr_val, val→ tag
> 	- Addressed style issues: Removed comment blocks, put functions in
> 	  one line
> 	- Remove blank line after compatible in regulator node
> 	- Reorder properties.
> 
> Link to v3: https://lore.kernel.org/lkml/20260630093603.38663-1-varshini.rajendran@microchip.com/
> 
> Changes in v3:
>     - Updated the commit message with reasoning for a new compatible
>       without a fallback (sama7d65-adc)
>     - Split patch 2/12 into two patches: a patch with cleanup.h changes only
>       and the rework patch
>     - Added comment explaining the TAG ACST
>     - Fixed the holes identified in the at91_adc_platform struct by
>       pahole tool
>     - Dropped labels in the dt document example
>     - Added temp variable in mchp_otpc_resolve_packet() to avoid % and /
>       operations in the same instruction (avoiding compiler optimization)
>     - Added the SoC details in the ADC driver Kconfig help section
>     - Maintained reverse xmas ordering in declarations
>     - Fixed node ordering (alphabetically) in the board dts file
> 
> Link to v2: https://lore.kernel.org/lkml/20260623105944.128840-1-varshini.rajendran@microchip.com/
> 
> Changes in v2:
>     - Preserved backward compatibility with ID-based packet lookup to
>       avoid breaking existing users
>     - Removed sama7g5 DTS changes (not needed with backward compatible
>       driver - will be sent later to update to the new access method)
>     - Preserved the packet data structure returned not to break the
>       consumers
>     - Reworked ADC driver to use a calibration layout structure instead of
>       hardcoded indexes, for scalability
>     - Fixed kernel-doc Return section
>     - Removed stray blank line in mchp_otpc_read()
>     - Removed unnecessary UL suffix in writel_relaxed()
>     - Dropped unused packet types
>     - Fixed stray spaces before exclamation marks in error messages
>     - Added ASCII representation to TAG macro definition
>     - Removed odd MAX enum with trailing comma and refactored
>     - Moved DTS patches to the end of series
>     - Used cleanup.h helpers for NVMEM data buffer handling in ADC driver
>     - Combined multiple v1 patches into logical units
>     - Used correct subject prefixes for dt-bindings patches
>     - Used fixed-layout NVMEM syntax for sama7d65 DTS and binding
>       instead of deprecated syntax
>     - Added cpu-supply linkage for proper DVFS voltage scaling
>     - Updated stale stride=4 comment in dt-bindings header
> 
> Link to v1: https://lore.kernel.org/linux-arm-kernel/20250804100219.63325-1-varshini.rajendran@microchip.com/
> 
> Varshini Rajendran (17):
>   dt-bindings: iio: adc: at91-sama5d2: document sama7d65
>   nvmem: add DEFINE_FREE for nvmem_cell_put cleanup
>   iio: adc: at91-sama5d2_adc: use cleanup.h for NVMEM buffer
>   iio: adc: at91-sama5d2_adc: rework temp calibration layout handling
>   iio: adc: at91-sama5d2_adc: add condition to validate calibration data
>   iio: adc: at91-sama5d2_adc: remove unnecessary casts in of_device_id
>   iio: adc: at91-sama5d2_adc: adapt the driver for sama7d65
>   dt-bindings: nvmem: microchip,sama7g5-otpc: add sama7d65 and dt node
>     example
>   nvmem: microchip-otpc: nvmem: microchip-otpc: add tag-based packet
>     lookup
>   nvmem: microchip-otpc: nvmem: add emulation mode and OTP access
>     validation
>   ARM: dts: microchip: sama7d65: add cpu opps
>   ARM: dts: microchip: sama7d65: Add ADC node
>   ARM: dts: microchip: sama7d65_curiosity: Enable ADC, DVFS
>   ARM: dts: microchip: sama7d65: add otpc node
>   ARM: dts: microchip: sama7d65: add cells for temperature calibration
>   ARM: dts: microchip: sama7d65: add temperature sensor
>   ARM: dts: microchip: sama7d65: add thermal zones node
> 
>  .../bindings/iio/adc/atmel,sama5d2-adc.yaml   |   1 +
>  .../nvmem/microchip,sama7g5-otpc.yaml         |  28 +++-
>  .../dts/microchip/at91-sama7d65_curiosity.dts |  27 ++++
>  arch/arm/boot/dts/microchip/sama7d65.dtsi     | 131 +++++++++++++++++
>  drivers/iio/adc/Kconfig                       |   2 +-
>  drivers/iio/adc/at91-sama5d2_adc.c            | 124 +++++++++++-----
>  drivers/nvmem/microchip-otpc.c                | 133 ++++++++++++++++--
>  .../nvmem/microchip,sama7g5-otpc.h            |   4 +-
>  include/linux/nvmem-consumer.h                |   4 +
>  9 files changed, 404 insertions(+), 50 deletions(-)
>