[PATCH 0/2] iio: accel: adxl367: add INT2 interrupt pin support

[PATCH 0/2] iio: accel: adxl367: add INT2 interrupt pin support

[Antoniu Miclaus]

The ADXL367 has two independent interrupt output pins, INT1 and INT2,
either of which may be wired to the host. So far the driver hardcoded
INT1 for all interrupt mappings, so a board that routes only INT2 could
never receive activity, inactivity or FIFO watermark interrupts.

This series adds an optional interrupt-names device tree property to
describe which pin ("INT1" and/or "INT2") is connected, and teaches the
driver to route its interrupt mappings to the matching register
(INTMAP1_LOWER or INTMAP2_LOWER). When no interrupt-names are present,
the driver defaults to INT1 to preserve the existing behaviour.

Antoniu Miclaus (2):
  dt-bindings: iio: accel: adi,adxl367: add interrupt-names
  iio: accel: adxl367: add support for INT2 interrupt pin

 .../bindings/iio/accel/adi,adxl367.yaml       | 11 ++++++-
 drivers/iio/accel/adxl367.c                   | 33 +++++++++++++++++--
 2 files changed, 40 insertions(+), 4 deletions(-)

-- 
2.43.0

[PATCH 1/2] dt-bindings: iio: accel: adi,adxl367: add interrupt-names

[Antoniu Miclaus]

The ADXL367 has two independent interrupt output pins, INT1 and INT2,
either of which may be wired to the host. Allow the interrupt line that
is connected to be described by adding an optional interrupt-names
property accepting "INT1" and/or "INT2", and permit a second interrupt
entry. interrupt-names is kept optional so existing device trees that
only specify a bare interrupts property remain valid.

Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com>
---
 .../devicetree/bindings/iio/accel/adi,adxl367.yaml    | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/iio/accel/adi,adxl367.yaml b/Documentation/devicetree/bindings/iio/accel/adi,adxl367.yaml
index f10d98d34cb8..c8df234e493f 100644
--- a/Documentation/devicetree/bindings/iio/accel/adi,adxl367.yaml
+++ b/Documentation/devicetree/bindings/iio/accel/adi,adxl367.yaml
@@ -33,7 +33,14 @@ properties:
     maxItems: 1
 
   interrupts:
-    maxItems: 1
+    minItems: 1
+    maxItems: 2
+
+  interrupt-names:
+    minItems: 1
+    items:
+      - enum: [INT1, INT2]
+      - const: INT2
 
   vdd-supply: true
   vddio-supply: true
@@ -61,6 +68,7 @@ examples:
         reg = <0x53>;
         interrupt-parent = <&gpio>;
         interrupts = <25 IRQ_TYPE_EDGE_RISING>;
+        interrupt-names = "INT1";
       };
     };
   - |
@@ -76,5 +84,6 @@ examples:
         spi-max-frequency = <1000000>;
         interrupt-parent = <&gpio>;
         interrupts = <25 IRQ_TYPE_EDGE_RISING>;
+        interrupt-names = "INT1";
       };
     };
-- 
2.43.0

[PATCH 2/2] iio: accel: adxl367: add support for INT2 interrupt pin

[Antoniu Miclaus]

The ADXL367 provides two independent interrupt output pins, INT1 and
INT2, each with its own event mapping register (INTMAP1_LOWER at 0x2A
and INTMAP2_LOWER at 0x2B) sharing an identical bit layout. Until now
the driver hardcoded INT1 for all interrupt mappings, so a board that
routes only INT2 to the host could never receive activity, inactivity
or FIFO watermark interrupts.

Determine the connected pin from the interrupt-names device tree
property using fwnode_irq_get_byname(), and route the interrupt
mappings to the matching register. When no interrupt-names are present,
default to INT1 to preserve the existing behaviour.

Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com>
---
 drivers/iio/accel/adxl367.c | 33 ++++++++++++++++++++++++++++++---
 1 file changed, 30 insertions(+), 3 deletions(-)

diff --git a/drivers/iio/accel/adxl367.c b/drivers/iio/accel/adxl367.c
index 8c3de11a10a3..229974478d10 100644
--- a/drivers/iio/accel/adxl367.c
+++ b/drivers/iio/accel/adxl367.c
@@ -13,6 +13,7 @@
 #include <linux/iio/sysfs.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
+#include <linux/property.h>
 #include <linux/regmap.h>
 #include <linux/regulator/consumer.h>
 #include <linux/unaligned.h>
@@ -81,6 +82,7 @@
 #define ADXL367_SAMPLES_L_MASK		GENMASK(7, 0)
 
 #define ADXL367_REG_INT1_MAP		0x2A
+#define ADXL367_REG_INT2_MAP		0x2B
 #define ADXL367_INT_INACT_MASK		BIT(5)
 #define ADXL367_INT_ACT_MASK		BIT(4)
 #define ADXL367_INT_FIFO_WATERMARK_MASK	BIT(2)
@@ -168,6 +170,8 @@ struct adxl367_state {
 	enum adxl367_odr	odr;
 	enum adxl367_range	range;
 
+	u8		int_map_reg;
+
 	unsigned int	act_threshold;
 	unsigned int	act_time_ms;
 	unsigned int	inact_threshold;
@@ -366,7 +370,7 @@ static int adxl367_set_act_interrupt_en(struct adxl367_state *st,
 {
 	unsigned int mask = adxl367_act_int_mask_tbl[act];
 
-	return regmap_update_bits(st->regmap, ADXL367_REG_INT1_MAP,
+	return regmap_update_bits(st->regmap, st->int_map_reg,
 				  mask, en ? mask : 0);
 }
 
@@ -378,7 +382,7 @@ static int adxl367_get_act_interrupt_en(struct adxl367_state *st,
 	unsigned int val;
 	int ret;
 
-	ret = regmap_read(st->regmap, ADXL367_REG_INT1_MAP, &val);
+	ret = regmap_read(st->regmap, st->int_map_reg, &val);
 	if (ret)
 		return ret;
 
@@ -401,7 +405,7 @@ static int adxl367_set_act_en(struct adxl367_state *st,
 static int adxl367_set_fifo_watermark_interrupt_en(struct adxl367_state *st,
 						   bool en)
 {
-	return regmap_update_bits(st->regmap, ADXL367_REG_INT1_MAP,
+	return regmap_update_bits(st->regmap, st->int_map_reg,
 				  ADXL367_INT_FIFO_WATERMARK_MASK,
 				  en ? ADXL367_INT_FIFO_WATERMARK_MASK : 0);
 }
@@ -1426,6 +1430,27 @@ static int adxl367_setup(struct adxl367_state *st)
 	return adxl367_set_measure_en(st, true);
 }
 
+static int adxl367_get_int_line(struct adxl367_state *st, int irq)
+{
+	int int_irq;
+
+	int_irq = fwnode_irq_get_byname(dev_fwnode(st->dev), "INT1");
+	if (int_irq > 0) {
+		st->int_map_reg = ADXL367_REG_INT1_MAP;
+		return int_irq;
+	}
+
+	int_irq = fwnode_irq_get_byname(dev_fwnode(st->dev), "INT2");
+	if (int_irq > 0) {
+		st->int_map_reg = ADXL367_REG_INT2_MAP;
+		return int_irq;
+	}
+
+	/* No interrupt-names: default to INT1 for backwards compatibility. */
+	st->int_map_reg = ADXL367_REG_INT1_MAP;
+	return irq;
+}
+
 int adxl367_probe(struct device *dev, const struct adxl367_ops *ops,
 		  void *context, struct regmap *regmap, int irq)
 {
@@ -1482,6 +1507,8 @@ int adxl367_probe(struct device *dev, const struct adxl367_ops *ops,
 	if (ret)
 		return ret;
 
+	irq = adxl367_get_int_line(st, irq);
+
 	ret = devm_request_threaded_irq(st->dev, irq, NULL,
 					adxl367_irq_handler, IRQF_ONESHOT,
 					indio_dev->name, indio_dev);
-- 
2.43.0

Re: [PATCH 2/2] iio: accel: adxl367: add support for INT2 interrupt pin

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:

New issues:
- [High] The driver swallows -EPROBE_DEFER and other negative error codes from fwnode_irq_get_byname(), breaking probe deferral.

Pre-existing issues:
- [High] Out-of-bounds write in adxl367_push_fifo_data due to missing bounds check on fifo_entries.
- [High] Kernel panic due to a modulo-by-zero operation in adxl367_push_fifo_data when fifo_set_size is uninitialized.
--

--- Patch [2]: [PATCH 2/2] iio: accel: adxl367: add support for INT2 interrupt pin ---
commit 726b611b27f821c71f931174d7f0a134dabcdb00
Author: Antoniu Miclaus <antoniu.miclaus@analog.com>

iio: accel: adxl367: add support for INT2 interrupt pin

The ADXL367 provides two independent interrupt output pins, INT1 and
INT2, each with its own event mapping register sharing an identical bit
layout. This commit determines the connected pin from the
interrupt-names device tree property and routes the interrupt mappings
to the matching register, defaulting to INT1 if no interrupt-names are
present.

> diff --git a/drivers/iio/accel/adxl367.c b/drivers/iio/accel/adxl367.c
> index 8c3de11a10a37..229974478d10b 100644
> --- a/drivers/iio/accel/adxl367.c
> +++ b/drivers/iio/accel/adxl367.c
[ ... ]
> @@ -1426,6 +1430,27 @@ static int adxl367_setup(struct adxl367_state *st)
>  	return adxl367_set_measure_en(st, true);
>  }
>  
> +static int adxl367_get_int_line(struct adxl367_state *st, int irq)
> +{
> +	int int_irq;
> +
> +	int_irq = fwnode_irq_get_byname(dev_fwnode(st->dev), "INT1");
> +	if (int_irq > 0) {

[Severity: High]
Could this condition inadvertently swallow negative error codes like
-EPROBE_DEFER? If fwnode_irq_get_byname() returns -EPROBE_DEFER because the
interrupt controller is not yet ready, this check treats it as a missing
property instead of properly deferring the probe. This can cause the driver
to fall back to trying INT2 or returning the default irq. If the default irq
is 0, devm_request_threaded_irq() will subsequently fail with -EINVAL.

> +		st->int_map_reg = ADXL367_REG_INT1_MAP;
> +		return int_irq;
> +	}
> +
> +	int_irq = fwnode_irq_get_byname(dev_fwnode(st->dev), "INT2");
> +	if (int_irq > 0) {

[Severity: High]
Does this check suffer from the same -EPROBE_DEFER issue as above?

> +		st->int_map_reg = ADXL367_REG_INT2_MAP;
> +		return int_irq;
> +	}
> +
> +	/* No interrupt-names: default to INT1 for backwards compatibility. */
> +	st->int_map_reg = ADXL367_REG_INT1_MAP;
> +	return irq;
> +}

[Severity: High]
This is a pre-existing issue, but I noticed a potential out-of-bounds write
in adxl367_push_fifo_data():

drivers/iio/accel/adxl367.c:adxl367_push_fifo_data()
    ret = st->ops->read_fifo(st->context, st->fifo_buf, fifo_entries);

Is it possible to overflow st->fifo_buf here? The fifo_entries value is read
from the hardware as a 10-bit value (up to 1023), but st->fifo_buf is fixed
at 512 elements. If the hardware returns a value greater than 512, this
would cause an out-of-bounds write.

[Severity: High]
This is also a pre-existing issue, but there appears to be a potential
modulo-by-zero panic in the same function:

drivers/iio/accel/adxl367.c:adxl367_push_fifo_data()
    fifo_entries -= fifo_entries % st->fifo_set_size;

Can this cause a kernel panic? If an interrupt triggers before the IIO
buffer is enabled (where st->fifo_set_size is populated), st->fifo_set_size
will be zero. If the ADXL367_STATUS_FIFO_FULL_MASK bit happens to be set,
this division by zero will crash the kernel.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260805115952.33894-1-antoniu.miclaus@analog.com?part=2

Re: [PATCH 0/2] iio: accel: adxl367: add INT2 interrupt pin support

[Nuno Sá]

On Wed, 05 Aug 2026 14:59:50 +0300, Antoniu Miclaus <antoniu.miclaus@analog.com> wrote:
> [...]
> 
>  .../bindings/iio/accel/adi,adxl367.yaml       | 11 ++++++-
>  drivers/iio/accel/adxl367.c                   | 33 +++++++++++++++++--
>  2 files changed, 40 insertions(+), 4 deletions(-)
> 
> --

Given that you touching this driver, maybe it's a good opportunity to
update MAINTAINERS given that Cosmin's email does not exist anymore.
If you want to take it, add yourself. Otherwise use ADI list
<linux@analog.com>

-- 
Nuno Sá <nuno.sa@analog.com>

Re: [PATCH 2/2] iio: accel: adxl367: add support for INT2 interrupt pin

[Nuno Sá]

On Wed, 05 Aug 2026 14:59:52 +0300, Antoniu Miclaus <antoniu.miclaus@analog.com> wrote:
> diff --git a/drivers/iio/accel/adxl367.c b/drivers/iio/accel/adxl367.c
> index 8c3de11a10a3..229974478d10 100644
> --- a/drivers/iio/accel/adxl367.c
> +++ b/drivers/iio/accel/adxl367.c
> @@ -1482,6 +1507,8 @@ int adxl367_probe(struct device *dev, const struct adxl367_ops *ops,
>  	if (ret)
>  		return ret;
>  
> +	irq = adxl367_get_int_line(st, irq);

On top of Sashiko's points (which do make sense), I'm not sure why we
return irq in adxl367_get_int_line() which seems to be just the same we
passed to it?

-- 
Nuno Sá <nuno.sa@analog.com>