Re: [PATCH net-next v2 5/8] dt-bindings: net: x-powers: add AC300 EPHY control

[Rob Herring <robh@kernel.org>]

On Tue, Aug 04, 2026 at 08:27:03PM -0600, James Hilliard wrote:
> The AC300 exposes its Fast Ethernet PHY control registers through a
> separate non-PHY Clause 22 address. The manual defines that address as
> the link PHY address plus 16, giving control addresses 16 through 23 and
> link addresses 0 through 7.

That's not a separate device, but just a second address range. You 
should make 'reg' have 2 entries.

> 
> Describe the control endpoint, its required VCC1 supply, its 24, 25 or
> 27 MHz input clock and its SoC SID calibration cell. The actual PHY
> remains a separate ethernet-phy node and supplies the MAC-selected
> interface mode at runtime.
> 
> Signed-off-by: James Hilliard <james.hilliard1@gmail.com>
> ---
>  .../bindings/net/x-powers,ac300-ephy-ctl.yaml      | 70 ++++++++++++++++++++++
>  1 file changed, 70 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/net/x-powers,ac300-ephy-ctl.yaml b/Documentation/devicetree/bindings/net/x-powers,ac300-ephy-ctl.yaml
> new file mode 100644
> index 000000000000..8a616ff3e89f
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/net/x-powers,ac300-ephy-ctl.yaml
> @@ -0,0 +1,70 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/net/x-powers,ac300-ephy-ctl.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: X-Powers AC300 Ethernet PHY control interface
> +
> +maintainers:
> +  - James Hilliard <james.hilliard1@gmail.com>
> +
> +description:
> +  The AC300 Fast Ethernet PHY has a separate control interface accessed as a
> +  non-PHY Clause 22 device. Its address is 16 plus the address of the link PHY.
> +
> +properties:
> +  compatible:
> +    const: x-powers,ac300-ephy-ctl
> +
> +  reg:
> +    minimum: 16
> +    maximum: 23
> +
> +  clocks:
> +    maxItems: 1
> +    description:
> +      AC300 input clock. Its configured rate must be 24, 25, or 27 MHz and
> +      determines the corresponding EPHY_CLK_SEL value.
> +
> +  vcc1-supply:
> +    description:
> +      3.3 V supply for the AC300 I/O, bandgap, Ethernet PHY analog front end,
> +      and internal digital LDO

Sounds like this supply and clock would need to be enabled before 
accessing the "link PHY address"? If so, then 2 nodes is really a 
problem.

Rob