[PATCH v3 0/5] Initial device tree support for StarFive JHB100 SoC

[PATCH v3 0/5] Initial device tree support for StarFive JHB100 SoC

[Changhuang Liang]

StarFive JHB100 SoC consists of 4 RISC-V low power Cores (Dubhe-70). It
also features various interfaces such as I2C, SPI, CAN, USB, MMC, Uart,
etc.

This patch series introduces initial SoC DTSI support for the StarFive
JHB100 SoC. The relevant dt-binding documentation has been updated
accordingly. Below is the list of IP blocks added in the initial SoC DTSI.

- StarFive Dubhe-70 CPU
- PMU
- PLIC
- CLINT
- UART
- INTC

changes since v2:
- Add a new patch 4

patch 5:
- Remove the 'riscv,isa' property.
- Add 'starfive,jhb100-uart' to the UART node.
- Update bus node name.
- Remove the interrupts-extended property in riscv,pmu

v2: https://lore.kernel.org/all/20260506085937.754808-1-changhuang.liang@starfivetech.com/
v1: https://lore.kernel.org/all/20260402084019.440708-1-changhuang.liang@starfivetech.com/

Changhuang Liang (1):
  dt-bindings: serial: snps-dw-apb-uart: Add StarFive JHB100 UART
    compatible

Ji Sheng Teoh (1):
  dt-bindings: riscv: Add StarFive Dubhe-70 compatibles

Ley Foon Tan (3):
  dt-bindings: interrupt-controller: Add StarFive JHB100 plic
  dt-bindings: riscv: Add StarFive JHB100 SoC
  riscv: dts: starfive: jhb100: Add JHB100 base DT

 .../sifive,plic-1.0.0.yaml                    |   1 +
 .../devicetree/bindings/riscv/cpus.yaml       |   1 +
 .../devicetree/bindings/riscv/starfive.yaml   |   5 +
 .../bindings/serial/snps-dw-apb-uart.yaml     |   1 +
 MAINTAINERS                                   |   6 +
 arch/riscv/boot/dts/starfive/Makefile         |   2 +
 arch/riscv/boot/dts/starfive/jhb100-evb1.dts  |  32 ++
 arch/riscv/boot/dts/starfive/jhb100.dtsi      | 331 ++++++++++++++++++
 8 files changed, 379 insertions(+)
 create mode 100644 arch/riscv/boot/dts/starfive/jhb100-evb1.dts
 create mode 100644 arch/riscv/boot/dts/starfive/jhb100.dtsi

--
2.25.1

[PATCH v3 1/5] dt-bindings: riscv: Add StarFive Dubhe-70 compatibles

[Changhuang Liang]

From: Ji Sheng Teoh <jisheng.teoh@starfivetech.com>

Add new compatible string for Dubhe-70.
Dubhe-70 is a low power RISC-V cpu core from StarFive Technology.

Signed-off-by: Ji Sheng Teoh <jisheng.teoh@starfivetech.com>
Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
---
 Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index 5feeb2203050..e7eda7a9c345 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -63,6 +63,7 @@ properties:
               - sifive,u74-mc
               - spacemit,x100
               - spacemit,x60
+              - starfive,dubhe-70
               - thead,c906
               - thead,c908
               - thead,c910
-- 
2.25.1

[PATCH v3 2/5] dt-bindings: interrupt-controller: Add StarFive JHB100 plic

[Changhuang Liang]

From: Ley Foon Tan <leyfoon.tan@starfivetech.com>

Add compatible string for StarFive JHB100 plic.

Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
---
 .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml         | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
index 78d8cd77b4ec..cde4bb691897 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
@@ -66,6 +66,7 @@ properties:
               - spacemit,k1-plic
               - starfive,jh7100-plic
               - starfive,jh7110-plic
+              - starfive,jhb100-plic
               - tenstorrent,blackhole-plic
           - const: sifive,plic-1.0.0
       - items:
-- 
2.25.1

[PATCH v3 3/5] dt-bindings: riscv: Add StarFive JHB100 SoC

[Changhuang Liang]

From: Ley Foon Tan <leyfoon.tan@starfivetech.com>

Add device tree bindings for the StarFive JHB100 RISC-V SoC.

Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
---
 Documentation/devicetree/bindings/riscv/starfive.yaml | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/Documentation/devicetree/bindings/riscv/starfive.yaml b/Documentation/devicetree/bindings/riscv/starfive.yaml
index 8ba0e10b529a..277618efff6e 100644
--- a/Documentation/devicetree/bindings/riscv/starfive.yaml
+++ b/Documentation/devicetree/bindings/riscv/starfive.yaml
@@ -43,6 +43,11 @@ properties:
           - const: starfive,jh7110s
           - const: starfive,jh7110
 
+      - items:
+          - enum:
+              - starfive,jhb100-evb1
+          - const: starfive,jhb100
+
 additionalProperties: true
 
 ...
-- 
2.25.1

[PATCH v3 4/5] dt-bindings: serial: snps-dw-apb-uart: Add StarFive JHB100 UART compatible

[Changhuang Liang]

Add "starfive,jhb100-uart" compatible string, with "snps,dw-apb-uart"
as the fallback.

Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
 Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml
index c0d0524458c1..f90ba8f3d4f6 100644
--- a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml
+++ b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml
@@ -79,6 +79,7 @@ properties:
               - starfive,jh7100-hsuart
               - starfive,jh7100-uart
               - starfive,jh7110-uart
+              - starfive,jhb100-uart
               - ultrarisc,dp1000-uart
           - const: snps,dw-apb-uart
       - const: snps,dw-apb-uart
-- 
2.25.1

Re: [PATCH v3 4/5] dt-bindings: serial: snps-dw-apb-uart: Add StarFive JHB100 UART compatible

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] Missing Compatible String in Conditional Block
--

--- Patch [4]: [PATCH v3 4/5] dt-bindings: serial: snps-dw-apb-uart: Add StarFive JHB100 UART compatible ---
commit 58551d4cd9febd373c92800fceea07e37197bb0a
Author: Changhuang Liang <changhuang.liang@starfivetech.com>

dt-bindings: serial: snps-dw-apb-uart: Add StarFive JHB100 UART compatible

Add "starfive,jhb100-uart" compatible string, with "snps,dw-apb-uart"
as the fallback.

> diff --git a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml
> index 49f51b0028795..bca297c22fda5 100644
> --- a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml
> +++ b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml
> @@ -78,6 +78,7 @@ properties:
>                - starfive,jh7100-hsuart
>                - starfive,jh7100-uart
>                - starfive,jh7110-uart
> +              - starfive,jhb100-uart

[Severity: Medium]
Does the starfive,jhb100-uart hardware also require 2 resets like the
jh7110-uart?

If so, should it be added to the conditional block earlier in this file?
Without it, device trees specifying 2 resets for jhb100-uart will fail
schema validation because they will fall into the else block which limits
resets to a maxItems of 1:

allOf:
[ ... ]
  - if:
      properties:
        compatible:
          contains:
            const: starfive,jh7110-uart
    then:
      properties:
        resets:
          minItems: 2
    else:
      properties:
        resets:
          maxItems: 1

>                - ultrarisc,dp1000-uart
>            - const: snps,dw-apb-uart

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260806122553.182449-1-changhuang.liang@starfivetech.com?part=4

Re: [PATCH v3 4/5] dt-bindings: serial: snps-dw-apb-uart: Add StarFive JHB100 UART compatible

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 75 bytes --]

Acked-by: Conor Dooley <conor.dooley@microchip.com>
pw-bot: not-applicable

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

[PATCH v3 5/5] riscv: dts: starfive: jhb100: Add JHB100 base DT

[Changhuang Liang]

From: Ley Foon Tan <leyfoon.tan@starfivetech.com>

Add JHB100 base dtsi and dts. Consist of 4 Dubhe-70 cores, CLINT, PLIC,
PMU, UART, INTC and 1GB DDR.

Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
 MAINTAINERS                                  |   6 +
 arch/riscv/boot/dts/starfive/Makefile        |   2 +
 arch/riscv/boot/dts/starfive/jhb100-evb1.dts |  32 ++
 arch/riscv/boot/dts/starfive/jhb100.dtsi     | 331 +++++++++++++++++++
 4 files changed, 371 insertions(+)
 create mode 100644 arch/riscv/boot/dts/starfive/jhb100-evb1.dts
 create mode 100644 arch/riscv/boot/dts/starfive/jhb100.dtsi

diff --git a/MAINTAINERS b/MAINTAINERS
index 56b337a06447..ce97de46e610 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -26069,6 +26069,12 @@ F:	Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml
 F:	drivers/phy/starfive/phy-jh7110-pcie.c
 F:	drivers/phy/starfive/phy-jh7110-usb.c
 
+STARFIVE JHB100 DEVICETREES
+M:	Changhuang Liang <changhuang.liang@starfivetech.com>
+L:	linux-riscv@lists.infradead.org
+S:	Supported
+F:	arch/riscv/boot/dts/starfive/jhb100*
+
 STARFIVE JHB100 EXTERNAL INTERRUPT CONTROLLER DRIVER
 M:	Changhuang Liang <changhuang.liang@starfivetech.com>
 S:	Supported
diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile
index 3dd1f05283f7..42841942fe54 100644
--- a/arch/riscv/boot/dts/starfive/Makefile
+++ b/arch/riscv/boot/dts/starfive/Makefile
@@ -18,3 +18,5 @@ dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-lite.dtb
 dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-lite-emmc.dtb
 dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.2a.dtb
 dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.3b.dtb
+
+dtb-$(CONFIG_ARCH_STARFIVE) += jhb100-evb1.dtb
diff --git a/arch/riscv/boot/dts/starfive/jhb100-evb1.dts b/arch/riscv/boot/dts/starfive/jhb100-evb1.dts
new file mode 100644
index 000000000000..462b6fb7953b
--- /dev/null
+++ b/arch/riscv/boot/dts/starfive/jhb100-evb1.dts
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (c) 2024-2026 StarFive Technology Co., Ltd.
+ */
+
+#include "jhb100.dtsi"
+
+/ {
+	model = "StarFive JHB100 EVB-1";
+	compatible = "starfive,jhb100-evb1", "starfive,jhb100";
+
+	aliases {
+		serial6 = &uart6;
+	};
+
+	chosen {
+		stdout-path = "serial6:115200n8";
+	};
+
+	cpus {
+		timebase-frequency = <5000000>;
+	};
+
+	memory@40000000 {
+		device_type = "memory";
+		reg = <0x0 0x40000000 0x0 0x40000000>;	/* 1GB */
+	};
+};
+
+&uart6 {
+	status = "okay";
+};
diff --git a/arch/riscv/boot/dts/starfive/jhb100.dtsi b/arch/riscv/boot/dts/starfive/jhb100.dtsi
new file mode 100644
index 000000000000..14ab83ed4482
--- /dev/null
+++ b/arch/riscv/boot/dts/starfive/jhb100.dtsi
@@ -0,0 +1,331 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (c) 2024-2026 StarFive Technology Co., Ltd.
+ */
+
+/dts-v1/;
+
+/ {
+	compatible = "starfive,jhb100";
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			compatible = "starfive,dubhe-70", "riscv";
+			reg = <0x0>;
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h", "zba", "zbb",
+					       "zbc", "zbs", "zicbom", "zicbop", "zicboz", "zicntr",
+					       "zicond", "zicsr", "zifencei", "zihintpause",
+					       "zihpm", "svinval", "svnapot", "sscofpmf";
+			riscv,cbom-block-size = <64>;
+			riscv,cbop-block-size = <64>;
+			riscv,cboz-block-size = <64>;
+			d-cache-block-size = <64>;
+			d-cache-sets = <512>;
+			d-cache-size = <32768>;
+			d-tlb-sets = <1>;
+			d-tlb-size = <16>;
+			device_type = "cpu";
+			i-cache-block-size = <64>;
+			i-cache-sets = <512>;
+			i-cache-size = <32768>;
+			i-tlb-sets = <1>;
+			i-tlb-size = <24>;
+			mmu-type = "riscv,sv48";
+			next-level-cache = <&l2c0>;
+			tlb-split;
+
+			cpu0_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu1: cpu@1 {
+			compatible = "starfive,dubhe-70", "riscv";
+			reg = <0x1>;
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h", "zba", "zbb",
+					       "zbc", "zbs", "zicbom", "zicbop", "zicboz", "zicntr",
+					       "zicond", "zicsr", "zifencei", "zihintpause",
+					       "zihpm", "svinval", "svnapot", "sscofpmf";
+			riscv,cbom-block-size = <64>;
+			riscv,cbop-block-size = <64>;
+			riscv,cboz-block-size = <64>;
+			d-cache-block-size = <64>;
+			d-cache-sets = <512>;
+			d-cache-size = <32768>;
+			d-tlb-sets = <1>;
+			d-tlb-size = <16>;
+			device_type = "cpu";
+			i-cache-block-size = <64>;
+			i-cache-sets = <512>;
+			i-cache-size = <32768>;
+			i-tlb-sets = <1>;
+			i-tlb-size = <24>;
+			mmu-type = "riscv,sv48";
+			next-level-cache = <&l2c1>;
+			tlb-split;
+
+			cpu1_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu2: cpu@2 {
+			compatible = "starfive,dubhe-70", "riscv";
+			reg = <0x2>;
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h", "zba", "zbb",
+					       "zbc", "zbs", "zicbom", "zicbop", "zicboz", "zicntr",
+					       "zicond", "zicsr", "zifencei", "zihintpause",
+					       "zihpm", "svinval", "svnapot", "sscofpmf";
+			riscv,cbom-block-size = <64>;
+			riscv,cbop-block-size = <64>;
+			riscv,cboz-block-size = <64>;
+			d-cache-block-size = <64>;
+			d-cache-sets = <512>;
+			d-cache-size = <32768>;
+			d-tlb-sets = <1>;
+			d-tlb-size = <16>;
+			device_type = "cpu";
+			i-cache-block-size = <64>;
+			i-cache-sets = <512>;
+			i-cache-size = <32768>;
+			i-tlb-sets = <1>;
+			i-tlb-size = <24>;
+			mmu-type = "riscv,sv48";
+			next-level-cache = <&l2c2>;
+			tlb-split;
+
+			cpu2_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu3: cpu@3 {
+			compatible = "starfive,dubhe-70", "riscv";
+			reg = <0x3>;
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h", "zba", "zbb",
+					       "zbc", "zbs", "zicbom", "zicbop", "zicboz", "zicntr",
+					       "zicond", "zicsr", "zifencei", "zihintpause",
+					       "zihpm", "svinval", "svnapot", "sscofpmf";
+			riscv,cbom-block-size = <64>;
+			riscv,cbop-block-size = <64>;
+			riscv,cboz-block-size = <64>;
+			d-cache-block-size = <64>;
+			d-cache-sets = <512>;
+			d-cache-size = <32768>;
+			d-tlb-sets = <1>;
+			d-tlb-size = <16>;
+			device_type = "cpu";
+			i-cache-block-size = <64>;
+			i-cache-sets = <512>;
+			i-cache-size = <32768>;
+			i-tlb-sets = <1>;
+			i-tlb-size = <24>;
+			mmu-type = "riscv,sv48";
+			next-level-cache = <&l2c3>;
+			tlb-split;
+
+			cpu3_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&cpu0>;
+				};
+			};
+
+			cluster1 {
+				core0 {
+					cpu = <&cpu1>;
+				};
+			};
+
+			cluster2 {
+				core0 {
+					cpu = <&cpu2>;
+				};
+			};
+
+			cluster3 {
+				core0 {
+					cpu = <&cpu3>;
+				};
+			};
+		};
+
+		l2c0: cache-controller-0 {
+			compatible = "cache";
+			cache-block-size = <64>;
+			cache-level = <2>;
+			cache-sets = <2048>;
+			cache-size = <0x20000>;
+			cache-unified;
+			next-level-cache = <&l3_cache>;
+		};
+
+		l2c1: cache-controller-1 {
+			compatible = "cache";
+			cache-block-size = <64>;
+			cache-level = <2>;
+			cache-sets = <2048>;
+			cache-size = <0x20000>;
+			cache-unified;
+			next-level-cache = <&l3_cache>;
+		};
+
+		l2c2: cache-controller-2 {
+			compatible = "cache";
+			cache-block-size = <64>;
+			cache-level = <2>;
+			cache-sets = <2048>;
+			cache-size = <0x20000>;
+			cache-unified;
+			next-level-cache = <&l3_cache>;
+		};
+
+		l2c3: cache-controller-3 {
+			compatible = "cache";
+			cache-block-size = <64>;
+			cache-level = <2>;
+			cache-sets = <2048>;
+			cache-size = <0x20000>;
+			cache-unified;
+			next-level-cache = <&l3_cache>;
+		};
+
+		l3_cache: cache-controller-4 {
+			compatible = "cache";
+			cache-block-size = <64>;
+			cache-level = <3>;
+			cache-sets = <1024>;
+			cache-size = <0x20000>;
+			cache-unified;
+		};
+	};
+
+	pmu {
+		compatible = "riscv,pmu";
+
+		riscv,event-to-mhpmevent = <0x00005 0x0000 0xA>,
+					   <0x00006 0x0000 0xB>,
+					   <0x00008 0x0000 0x10>,
+					   <0x00009 0x0000 0xF>,
+					   <0x10000 0x0000 0x19>,
+					   <0x10001 0x0000 0x1A>,
+					   <0x10002 0x0000 0x1B>,
+					   <0x10003 0x0000 0x1C>,
+					   <0x10008 0x0000 0x8>,
+					   <0x10009 0x0000 0x9>,
+					   <0x1000C 0x0000 0x9E>,
+					   <0x1000D 0x0000 0x9F>,
+					   <0x10010 0x0000 0x1D>,
+					   <0x10011 0x0000 0x1E>,
+					   <0x10012 0x0000 0x1F>,
+					   <0x10013 0x0000 0x20>,
+					   <0x10014 0x0000 0x21>,
+					   <0x10018 0x0000 0x17>,
+					   <0x10019 0x0000 0x18>,
+					   <0x10020 0x0000 0x8>,
+					   <0x10021 0x0000 0x7>;
+
+		riscv,event-to-mhpmcounters = <0x00005 0x00006 0x00007FF8>,
+					      <0x00008 0x00009 0x00007FF8>,
+					      <0x10000 0x10003 0x00007FF8>,
+					      <0x10008 0x10009 0x00007FF8>,
+					      <0x1000C 0x1000D 0x00007FF8>,
+					      <0x10010 0x10014 0x00007FF8>,
+					      <0x10018 0x10019 0x00007FF8>,
+					      <0x10020 0x10021 0x00007FF8>;
+
+		riscv,raw-event-to-mhpmcounters =
+			<0x00 0x00 0xFFFFFFFF 0xFFFFFFE0 0x00007FF8>,	/* Event ID 1-31 */
+			<0x00 0x20 0xFFFFFFFF 0xFFFFFFFE 0x00007FF8>,	/* Event ID 32-33 */
+			<0x00 0x22 0xFFFFFFFF 0xFFFFFF22 0x00007FF8>;	/* Event ID 34 */
+	};
+
+	clk_uart: clock-uart {
+		compatible = "fixed-clock"; /* Initial clock handler for UART */
+		#clock-cells = <0>;
+		clock-frequency = <25000000>;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		interrupt-parent = <&plic>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		dma-ranges;
+		ranges;
+
+		clint: timer@2000000 {
+			compatible = "starfive,jhb100-clint", "sifive,clint0";
+			reg = <0x0 0x02000000 0x0 0x10000>;
+			interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
+					      <&cpu1_intc 3>, <&cpu1_intc 7>,
+					      <&cpu2_intc 3>, <&cpu2_intc 7>,
+					      <&cpu3_intc 3>, <&cpu3_intc 7>;
+		};
+
+		plic: interrupt-controller@c000000 {
+			compatible = "starfive,jhb100-plic", "sifive,plic-1.0.0";
+			reg = <0x0 0x0c000000 0x0 0x4000000>;
+			riscv,ndev = <400>;
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			#address-cells = <0>;
+			interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
+					      <&cpu1_intc 11>, <&cpu1_intc 9>,
+					      <&cpu2_intc 11>, <&cpu2_intc 9>,
+					      <&cpu3_intc 11>, <&cpu3_intc 9>;
+		};
+
+		bus_nioc: bus {
+			compatible = "simple-bus";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			dma-noncoherent;
+			dma-ranges = <0x4 0x00000000 0x0 0x40000000 0x2 0x0>,
+				     <0x4 0x00000000 0x4 0x00000000 0x2 0x0>;
+			ranges;
+
+			uart6: serial@11982000 {
+				compatible = "starfive,jhb100-uart", "snps,dw-apb-uart";
+				reg = <0x0 0x11982000 0x0 0x400>;
+				clocks = <&clk_uart>, <&clk_uart>;
+				clock-names = "baudclk", "apb_pclk";
+				interrupt-parent = <&intc>;
+				interrupts = <26>;
+				reg-io-width = <4>;
+				reg-shift = <2>;
+				status = "disabled";
+			};
+
+			intc: interrupt-controller@13220000 {
+				compatible = "starfive,jhb100-intc";
+				reg = <0x0 0x13220000 0x0 0x80>;
+				interrupts = <1>;
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+	};
+};
-- 
2.25.1

Re: [PATCH v3 5/5] riscv: dts: starfive: jhb100: Add JHB100 base DT

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] Overlapping child address ranges in the `dma-ranges` property of `bus_nioc`.
- [Medium] Incorrect variant bitmask for PMU Event ID 34 in `riscv,raw-event-to-mhpmcounters`.
--

--- Patch [5]: [PATCH v3 5/5] riscv: dts: starfive: jhb100: Add JHB100 base DT ---
commit 6747fd56a0417ce034668e51d45ea97227861dc1
Author: Ley Foon Tan <leyfoon.tan@starfivetech.com>

riscv: dts: starfive: jhb100: Add JHB100 base DT

This commit adds the base device tree sources for the StarFive JHB100
SoC and the corresponding EVB-1 board. It introduces support for 4 
Dubhe-70 cores, along with basic peripherals including PMU, CLINT,
PLIC, and UART.

> diff --git a/arch/riscv/boot/dts/starfive/jhb100.dtsi b/arch/riscv/boot/dts/starfive/jhb100.dtsi
> new file mode 100644
> index 0000000000000..14ab83ed4482a
> --- /dev/null
> +++ b/arch/riscv/boot/dts/starfive/jhb100.dtsi
> @@ -0,0 +1,331 @@

[ ... ]

> +	pmu {
> +		compatible = "riscv,pmu";

[ ... ]

> +		riscv,raw-event-to-mhpmcounters =
> +			<0x00 0x00 0xFFFFFFFF 0xFFFFFFE0 0x00007FF8>,	/* Event ID 1-31 */
> +			<0x00 0x20 0xFFFFFFFF 0xFFFFFFFE 0x00007FF8>,	/* Event ID 32-33 */
> +			<0x00 0x22 0xFFFFFFFF 0xFFFFFF22 0x00007FF8>;	/* Event ID 34 */

[Severity: Medium]
Is the variant mask 0xFFFFFF22 correct for Event ID 34?

This mask appears to allow several bits (7, 6, 4, 3, 2, and 0) to vary,
which could cause other hardware PMU events to incorrectly match this rule
and route to the counters designated for Event 34.

> +	};

[ ... ]

> +		bus_nioc: bus {
> +			compatible = "simple-bus";
> +			#address-cells = <2>;
> +			#size-cells = <2>;
> +			dma-noncoherent;
> +			dma-ranges = <0x4 0x00000000 0x0 0x40000000 0x2 0x0>,
> +				     <0x4 0x00000000 0x4 0x00000000 0x2 0x0>;

[Severity: High]
Does this dma-ranges property incorrectly define overlapping child addresses?

Both entries define the exact same child DMA address space (<0x4 0x00000000>
with a size of <0x2 0x0>).

When parsed, standard OF translation matches the first entry, which entirely
shadows the second entry and could make its parent physical memory range
unreachable for DMA from this bus.

> +			ranges;

[ ... ]

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260806122553.182449-1-changhuang.liang@starfivetech.com?part=5

Re: [PATCH v3 5/5] riscv: dts: starfive: jhb100: Add JHB100 base DT

[Conor Dooley]

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On Thu, Aug 06, 2026 at 05:25:53AM -0700, Changhuang Liang wrote:
> +
> +	clk_uart: clock-uart {
> +		compatible = "fixed-clock"; /* Initial clock handler for UART */
> +		#clock-cells = <0>;
> +		clock-frequency = <25000000>;
> +	};

I can pick this series up on a provisional basis for you to work on top
of, but I won't be sending a PR for anything that contains temporary
fixed clocks.

Cheers,
Conor.

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Re: [PATCH v3 5/5] riscv: dts: starfive: jhb100: Add JHB100 base DT

[Changhuang Liang]

Hi, Conor

Thanks for the review.

> On Thu, Aug 06, 2026 at 05:25:53AM -0700, Changhuang Liang wrote:
> > +
> > +	clk_uart: clock-uart {
> > +		compatible = "fixed-clock"; /* Initial clock handler for UART */
> > +		#clock-cells = <0>;
> > +		clock-frequency = <25000000>;
> > +	};
> 
> I can pick this series up on a provisional basis for you to work on top of, but I
> won't be sending a PR for anything that contains temporary fixed clocks.

That's great.

Once my other two series are also ready:

Add basic clocks and resets for JHB100 SoC
Add StarFive JHB100 syscon modules

I can squash these three device tree into a single patch and send it out, so there won't be 
any temporarily used clk_uart and PLL nodes.

Best Regards,
Changhuang