[PATCH v2 0/3] Enable quad SPI mode for SPI-NAND on IPQ RDP boards

[PATCH v2 0/3] Enable quad SPI mode for SPI-NAND on IPQ RDP boards

[Md Sadre Alam]

Several Qualcomm IPQ RDP platforms support quad (x4) SPI transfers
between the QPIC SPI-NAND controller and the attached SPI-NAND device.
However, the corresponding device trees do not currently describe the
bus width capabilities of the flash device, causing transfers to fall
back to the default single-bit (x1) mode.

This series enables quad SPI operation on supported IPQ reference
design platforms by adding spi-rx-bus-width and spi-tx-bus-width
properties to the SPI-NAND device nodes.

The series updates the IPQ9574, IPQ5424 and IPQ5332 based RDPs.

Signed-off-by: Md Sadre Alam <md.alam@oss.qualcomm.com>
---
Changes in v2:
- No code changes
- Pick R-b tags
- rebased on top of tree
- updated the dependecies
- Depends-on : https://lore.kernel.org/linux-arm-msm/20260807-quad-v2-0-8ec821e2f22b@oss.qualcomm.com/
- Link to v1: https://lore.kernel.org/r/20260716-quad_dts-v1-0-74d86792944a@oss.qualcomm.com

---
Md Sadre Alam (3):
      arm64: dts: qcom: ipq9574-rdp-common: Enable quad SPI mode for SPI-NAND
      arm64: dts: qcom: ipq5424-rdp466: Enable quad SPI mode for SPI-NAND
      arm64: dts: qcom: ipq5332-rdp-common: Enable quad SPI mode for SPI-NAND

 arch/arm64/boot/dts/qcom/ipq5332-rdp-common.dtsi | 2 ++
 arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts      | 2 ++
 arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi | 2 ++
 3 files changed, 6 insertions(+)
---
base-commit: d56fa0b2bd2d9b2fddc10e8f5bdd42d56676935c
change-id: 20260716-quad_dts-6bac0484c08c
prerequisite-message-id : 20260807-quad-v2-0-8ec821e2f22b@oss.qualcomm.com
prerequisite-patch-id: 912ede01168ddf0476ba69ab0db786186073f817
prerequisite-patch-id: ab86c050f49d3180b10e61ec20bdcc6272c8100c
prerequisite-patch-id: 932ca3dc3893df6de25928b24c7c24550907088d

Best regards,
-- 
Md Sadre Alam <md.alam@oss.qualcomm.com>

[PATCH v2 1/3] arm64: dts: qcom: ipq9574-rdp-common: Enable quad SPI mode for SPI-NAND

[Md Sadre Alam]

Set the SPI-NAND device node to use 4-bit transmit and receive bus widths.

The board supports quad SPI transfers, but the device tree currently does
not describe the wider bus. Add spi-tx-bus-width and spi-rx-bus-width so
the controller and flash can use quad mode instead of single-bit transfers.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Md Sadre Alam <md.alam@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi
index 62877b46f9b3..86138529ba77 100644
--- a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi
@@ -249,6 +249,8 @@ flash@0 {
 		nand-ecc-engine = <&qpic_nand>;
 		nand-ecc-strength = <4>;
 		nand-ecc-step-size = <512>;
+		spi-rx-bus-width = <4>;
+		spi-tx-bus-width = <4>;
 	};
 };
 

-- 
2.34.1

Re: [PATCH v2 1/3] arm64: dts: qcom: ipq9574-rdp-common: Enable quad SPI mode for SPI-NAND

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Adding spi-tx-bus-width = <4> breaks SPI NAND writes because the spi-qpic-snand driver explicitly rejects Quad Program Load opcodes.
--

--- Patch [1]: [PATCH v2 1/3] arm64: dts: qcom: ipq9574-rdp-common: Enable quad SPI mode for SPI-NAND ---
commit bae8660983c8ddf15356080523eb2d131962463a
Author: Md Sadre Alam <md.alam@oss.qualcomm.com>

arm64: dts: qcom: ipq9574-rdp-common: Enable quad SPI mode for SPI-NAND

This commit sets the SPI-NAND device node to use 4-bit transmit and receive
bus widths. This allows the controller and flash to use quad mode instead of
single-bit transfers.

> diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi
> --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi
[ ... ]
> @@ -249,6 +249,8 @@ flash@0 {
>  		nand-ecc-engine = <&qpic_nand>;
>  		nand-ecc-strength = <4>;
>  		nand-ecc-step-size = <512>;
> +		spi-rx-bus-width = <4>;
> +		spi-tx-bus-width = <4>;

[Severity: High]
Does enabling a 4-bit transmit bus width break SPI NAND writes on this board?

When spi-tx-bus-width is set to 4, the spi-nand core will probe for Quad
Program Load operations (e.g., opcode 0x32) and select it as the default page
write operation.

However, the spi-qpic-snand driver only appears to support single-bit program
load opcodes:

drivers/spi/spi-qpic-snand.c:qcom_spi_cmd_mapping() {
	...
	case SPINAND_PROGRAM_LOAD:
		*cmd = SPINAND_PROGRAM_LOAD;
		break;
	default:
		dev_err(snandc->dev, "Opcode not supported: %u\n", opcode);
		return -EOPNOTSUPP;
}

Because the driver rejects the Quad Program Load opcodes, writes will fail
with -EOPNOTSUPP.

Additionally, even if the mapping were updated, it looks like the driver
ignores the data buffer for any opcode other than SPINAND_PROGRAM_LOAD:

drivers/spi/spi-qpic-snand.c:qcom_spi_write_page() {
	...
	if (op->cmd.opcode == SPINAND_PROGRAM_LOAD)
		snandc->qspi->data_buf = (u8 *)op->data.buf.out;
	...
}

Should the spi-tx-bus-width addition be omitted until the spi-qpic-snand
driver is updated to support Quad Program Load operations?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260807-quad_dts-v2-0-6f578d4152b7@oss.qualcomm.com?part=1

[PATCH v2 2/3] arm64: dts: qcom: ipq5424-rdp466: Enable quad SPI mode for SPI-NAND

[Md Sadre Alam]

Enable quad SPI transfers for the SPI-NAND device by setting both spi-rx-
bus-width and spi-tx-bus-width to 4.

Without these properties, the device uses the default single-bit bus width.
Configure the board to use 4-bit read and write transfers so the controller
and flash can operate in quad SPI mode.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Md Sadre Alam <md.alam@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts
index be8657239c46..793afc3ee82e 100644
--- a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts
+++ b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts
@@ -261,6 +261,8 @@ flash@0 {
 		nand-ecc-engine = <&qpic_nand>;
 		nand-ecc-strength = <4>;
 		nand-ecc-step-size = <512>;
+		spi-rx-bus-width = <4>;
+		spi-tx-bus-width = <4>;
 	};
 };
 

-- 
2.34.1

Re: [PATCH v2 2/3] arm64: dts: qcom: ipq5424-rdp466: Enable quad SPI mode for SPI-NAND

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Enabling quad SPI transfers breaks SPI-NAND page writes because the underlying qcom_snand controller driver does not support quad write opcodes.
--

--- Patch [2]: [PATCH v2 2/3] arm64: dts: qcom: ipq5424-rdp466: Enable quad SPI mode for SPI-NAND ---
commit 1fa4c052f14795bba0cdda5777b6df317a26eaf8
Author: Md Sadre Alam <md.alam@oss.qualcomm.com>

arm64: dts: qcom: ipq5424-rdp466: Enable quad SPI mode for SPI-NAND

Enable quad SPI transfers for the SPI-NAND device by setting both spi-rx-
bus-width and spi-tx-bus-width to 4.

> diff --git a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts
> --- a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts
> +++ b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts
> @@ -257,6 +257,8 @@ flash@0 {
>  		nand-ecc-engine = <&qpic_nand>;
>  		nand-ecc-strength = <4>;
>  		nand-ecc-step-size = <512>;
> +		spi-rx-bus-width = <4>;
> +		spi-tx-bus-width = <4>;

[Severity: High]
Will enabling a 4-bit tx bus width break page writes to this flash?

When the SPI-NAND core negotiates a 4-bit write variant (such as Quad
Program Load, opcode 0x32), the operation appears to be rejected by the
controller driver during the actual write:

drivers/spi/spi-qpic-snand.c:qcom_spi_cmd_mapping() {
	...
	case SPINAND_PROGRAM_LOAD:
		*cmd = SPINAND_PROGRAM_LOAD;
		break;
	default:
		dev_err(snandc->dev, "Opcode not supported: %u\n", opcode);
		return -EOPNOTSUPP;
}

Since qcom_spi_cmd_mapping() only maps the single-bit SPINAND_PROGRAM_LOAD
(0x84) opcode, won't the 4-bit opcodes hit the default case and return
-EOPNOTSUPP, causing all writes to fail?

>  	};
>  };

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260807-quad_dts-v2-0-6f578d4152b7@oss.qualcomm.com?part=2

[PATCH v2 3/3] arm64: dts: qcom: ipq5332-rdp-common: Enable quad SPI mode for SPI-NAND

[Md Sadre Alam]

The SPI-NAND device on the IPQ5332 RDP supports 4-bit data transfers, but
the device tree does not describe the bus width, so transfers use the
default single-bit mode.

Set spi-rx-bus-width and spi-tx-bus-width to 4 to enable quad read and
write transfers and improve SPI-NAND throughput.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Md Sadre Alam <md.alam@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/ipq5332-rdp-common.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/ipq5332-rdp-common.dtsi b/arch/arm64/boot/dts/qcom/ipq5332-rdp-common.dtsi
index 3bbf748f2e5c..6f5b193a204b 100644
--- a/arch/arm64/boot/dts/qcom/ipq5332-rdp-common.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5332-rdp-common.dtsi
@@ -141,5 +141,7 @@ flash@0 {
 		nand-ecc-engine = <&qpic_nand>;
 		nand-ecc-strength = <4>;
 		nand-ecc-step-size = <512>;
+		spi-rx-bus-width = <4>;
+		spi-tx-bus-width = <4>;
 	};
 };

-- 
2.34.1