[PATCH 0/2] watchdog: Add Exynos5515 watchdog timer support

[PATCH 0/2] watchdog: Add Exynos5515 watchdog timer support

[Aiden Isik via B4 Relay]

Hi there,

This patchset adds support for the Exynos5515 SoC's watchdog timer
to the S3C2410 watchdog timer driver.

There is one checkpatch warning for this patchset:

> -------------------------------------------------------------------------
> Commit 8f4ec3a9b89b ("watchdog: s3c2410_wdt: Add exynos5515-wdt compatibl
> -------------------------------------------------------------------------
> WARNING: Avoid unnecessary line continuations
> #26: FILE: drivers/watchdog/s3c2410_wdt.c:240:
> +       .quirks = QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_MASK_RESET | \

Which seems to be erroneous: this line continuation is necessary
(and is done by every other existing entry).

Kind regards,
- Aiden Isik

Signed-off-by: Aiden Isik <aidenisik+git@member.fsf.org>
---
Aiden Isik (2):
      dt-bindings: watchdog: samsung-wdt: Add exynos5515-wdt compatible
      watchdog: s3c2410_wdt: Add exynos5515-wdt compatible data

 .../devicetree/bindings/watchdog/samsung-wdt.yaml  | 22 +++++++++++++++++++++-
 drivers/watchdog/s3c2410_wdt.c                     | 12 ++++++++++++
 2 files changed, 33 insertions(+), 1 deletion(-)
---
base-commit: acde40ba506aae78633e080b5704d33cf4bc13c6
change-id: 20260815-for-next-lucky7-watchdog-32bfb51191f1

Best regards,
--  
Aiden Isik <aidenisik@member.fsf.org>

[PATCH 1/2] dt-bindings: watchdog: samsung-wdt: Add exynos5515-wdt compatible

[Aiden Isik via B4 Relay]

From: Aiden Isik <aidenisik@member.fsf.org>

Add a dt-binding compatible for the Exynos5515 watchdog timer.

This watchdog requires a syscon phandle, and the cluster index should
*not* be specified, as that does not make sense on the Exynos5515 SoC
(due to it only having a single core cluster).

Signed-off-by: Aiden Isik <aidenisik+git@member.fsf.org>
---
 .../devicetree/bindings/watchdog/samsung-wdt.yaml  | 22 +++++++++++++++++++++-
 1 file changed, 21 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml b/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml
index 41aee1655b0c..9e754404848b 100644
--- a/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml
+++ b/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml
@@ -22,6 +22,7 @@ properties:
           - samsung,s3c6410-wdt                   # for S3C6410, S5PV210 and Exynos4
           - samsung,exynos5250-wdt                # for Exynos5250
           - samsung,exynos5420-wdt                # for Exynos5420
+          - samsung,exynos5515-wdt                # for Exynos5515
           - samsung,exynos7-wdt                   # for Exynos7
           - samsung,exynos850-wdt                 # for Exynos850
           - samsung,exynos990-wdt                 # for Exynos990
@@ -57,7 +58,7 @@ properties:
     $ref: /schemas/types.yaml#/definitions/phandle
     description:
       Phandle to the PMU system controller node (in case of Exynos5250,
-      Exynos5420, Exynos7, Exynos850, Exynos990 and gs101).
+      Exynos5420, Exynos5515, Exynos7, Exynos850, Exynos990 and gs101).
 
 required:
   - compatible
@@ -93,6 +94,25 @@ allOf:
         - samsung,cluster-index
         - samsung,syscon-phandle
 
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - samsung,exynos5515-wdt
+    then:
+      properties:
+        clocks:
+          items:
+            - description: Bus clock, used for register interface
+            - description: Source clock (driving watchdog counter)
+        clock-names:
+          items:
+            - const: watchdog
+            - const: watchdog_src
+      required:
+        - samsung,syscon-phandle
+
   - if:
       properties:
         compatible:

-- 
2.54.0

Re: [PATCH 1/2] dt-bindings: watchdog: samsung-wdt: Add exynos5515-wdt compatible

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The dt-binding fails to explicitly forbid the `samsung,cluster-index` property for `samsung,exynos5515-wdt`, contradicting the commit message.
--

--- Patch [1]: [PATCH 1/2] dt-bindings: watchdog: samsung-wdt: Add exynos5515-wdt compatible ---
commit 63eda32b0d2c9ec15d915ccf3b6c34aae569838f
Author: Aiden Isik <aidenisik@member.fsf.org>

dt-bindings: watchdog: samsung-wdt: Add exynos5515-wdt compatible

This commit adds a device tree binding compatible string for the Exynos5515
watchdog timer. It requires a syscon phandle and specifies that the cluster
index should not be used since the SoC has a single core cluster.

> diff --git a/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml b/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml
> index 41aee1655b0c2..9e754404848b9 100644
> --- a/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml
> +++ b/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml
[ ... ]
> @@ -93,6 +94,25 @@ allOf:
>          - samsung,cluster-index
>          - samsung,syscon-phandle
>  
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            enum:
> +              - samsung,exynos5515-wdt
> +    then:
> +      properties:
> +        clocks:
> +          items:
> +            - description: Bus clock, used for register interface
> +            - description: Source clock (driving watchdog counter)
> +        clock-names:
> +          items:
> +            - const: watchdog
> +            - const: watchdog_src
> +      required:
> +        - samsung,syscon-phandle

[Severity: Medium]
The commit message mentions that the cluster index should not be specified
for this SoC. In the allOf conditional block for samsung,exynos5515-wdt,
does this need to explicitly forbid the property by adding
samsung,cluster-index: false under the properties section?

Without this constraint, will dt_binding_check silently allow device trees
for Exynos5515 that erroneously include the samsung,cluster-index property,
since it is defined in the top-level properties block and thus valid under
unevaluatedProperties: false?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260817-for-next-lucky7-watchdog-v1-0-a14370e20b92@member.fsf.org?part=1

Re: [PATCH 1/2] dt-bindings: watchdog: samsung-wdt: Add exynos5515-wdt compatible

[Aiden Isik]

> Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
> - [Medium] The dt-binding fails to explicitly forbid the `samsung,cluster-index` property for `samsung,exynos5515-wdt`, contradicting the commit message.
> --
> 
> --- Patch [1]: [PATCH 1/2] dt-bindings: watchdog: samsung-wdt: Add exynos5515-wdt compatible ---
> commit 63eda32b0d2c9ec15d915ccf3b6c34aae569838f
> Author: Aiden Isik <aidenisik@member.fsf.org>
> 
> dt-bindings: watchdog: samsung-wdt: Add exynos5515-wdt compatible
> 
> This commit adds a device tree binding compatible string for the Exynos5515
> watchdog timer. It requires a syscon phandle and specifies that the cluster
> index should not be used since the SoC has a single core cluster.
> 
> > diff --git a/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml b/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml
> > index 41aee1655b0c2..9e754404848b9 100644
> > --- a/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml
> > +++ b/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml
> [ ... ]
> > @@ -93,6 +94,25 @@ allOf:
> >          - samsung,cluster-index
> >          - samsung,syscon-phandle
> >
> > +  - if:
> > +      properties:
> > +        compatible:
> > +          contains:
> > +            enum:
> > +              - samsung,exynos5515-wdt
> > +    then:
> > +      properties:
> > +        clocks:
> > +          items:
> > +            - description: Bus clock, used for register interface
> > +            - description: Source clock (driving watchdog counter)
> > +        clock-names:
> > +          items:
> > +            - const: watchdog
> > +            - const: watchdog_src
> > +      required:
> > +        - samsung,syscon-phandle
> 
> [Severity: Medium]
> The commit message mentions that the cluster index should not be specified
> for this SoC. In the allOf conditional block for samsung,exynos5515-wdt,
> does this need to explicitly forbid the property by adding
> samsung,cluster-index: false under the properties section?
> 
> Without this constraint, will dt_binding_check silently allow device trees
> for Exynos5515 that erroneously include the samsung,cluster-index property,
> since it is defined in the top-level properties block and thus valid under
> unevaluatedProperties: false?
> 
> --

Will fix in v2.

> Sashiko AI review · https://sashiko.dev/#/patchset/20260817-for-next-lucky7-watchdog-v1-0-a14370e20b92@member.fsf.org?part=1
>

[PATCH 2/2] watchdog: s3c2410_wdt: Add exynos5515-wdt compatible data

[Aiden Isik via B4 Relay]

From: Aiden Isik <aidenisik@member.fsf.org>

Add driver data for the Exynos5515 SoC's watchdog timer.

Signed-off-by: Aiden Isik <aidenisik+git@member.fsf.org>
---
 drivers/watchdog/s3c2410_wdt.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c
index e31f93db0509..7299dfdb0c09 100644
--- a/drivers/watchdog/s3c2410_wdt.c
+++ b/drivers/watchdog/s3c2410_wdt.c
@@ -232,6 +232,16 @@ static const struct s3c2410_wdt_variant drv_data_exynos5420 = {
 		  QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_AUTO_DISABLE,
 };
 
+static const struct s3c2410_wdt_variant drv_data_exynos5515 = {
+	.mask_reset_reg = EXYNOSAUTOV920_CLUSTER0_NONCPU_INT_EN,
+	.mask_bit = 2,
+	.rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET,
+	.rst_stat_bit = 24,
+	.quirks = QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_MASK_RESET | \
+		  QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_AUTO_DISABLE | \
+		  QUIRK_HAS_DBGACK_BIT,
+};
+
 static const struct s3c2410_wdt_variant drv_data_exynos7 = {
 	.disable_reg = EXYNOS5_WDT_DISABLE_REG_OFFSET,
 	.mask_reset_reg = EXYNOS5_WDT_MASK_RESET_REG_OFFSET,
@@ -379,6 +389,8 @@ static const struct of_device_id s3c2410_wdt_match[] = {
 	  .data = &drv_data_exynos5250 },
 	{ .compatible = "samsung,exynos5420-wdt",
 	  .data = &drv_data_exynos5420 },
+	{ .compatible = "samsung,exynos5515-wdt",
+	  .data = &drv_data_exynos5515 },
 	{ .compatible = "samsung,exynos7-wdt",
 	  .data = &drv_data_exynos7 },
 	{ .compatible = "samsung,exynos850-wdt",

-- 
2.54.0

Re: [PATCH 2/2] watchdog: s3c2410_wdt: Add exynos5515-wdt compatible data

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
- [High] The `drv_data_exynos5515` variant declares `QUIRK_HAS_PMU_AUTO_DISABLE` but fails to initialize `.disable_reg`, causing unintentional writes to PMU offset 0x0000.
- [High] The `drv_data_exynos5515` variant uses an 'INT_EN' register for masking watchdog reset, but omits the `.mask_reset_inv = true` flag, inverting the WDT reset mask logic.
- [Medium] Incorrect use of an Exynos Auto v920 register macro (`EXYNOSAUTOV920_CLUSTER0_NONCPU_INT_EN`) in an Exynos 5515 variant.
--

--- Patch [2]: [PATCH 2/2] watchdog: s3c2410_wdt: Add exynos5515-wdt compatible data ---
commit dcaab4881777bc5f5ce1a532adad7c17046164a8
Author: Aiden Isik <aidenisik@member.fsf.org>

watchdog: s3c2410_wdt: Add exynos5515-wdt compatible data

This commit adds driver data and a compatible string for the Exynos5515
SoC's watchdog timer.

> diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c
> index e31f93db05096..7299dfdb0c099 100644
> --- a/drivers/watchdog/s3c2410_wdt.c
> +++ b/drivers/watchdog/s3c2410_wdt.c

[ ... ]

> @@ -232,6 +232,16 @@ static const struct s3c2410_wdt_variant drv_data_exynos5420 = {
>  		  QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_AUTO_DISABLE,
>  };
>  
> +static const struct s3c2410_wdt_variant drv_data_exynos5515 = {
> +	.mask_reset_reg = EXYNOSAUTOV920_CLUSTER0_NONCPU_INT_EN,

[Severity: Medium]
Is this intentionally using an Exynos Auto v920 register macro for an
Exynos 5515 variant, or could this be a copy-paste error?

[Severity: High]
Since this variant uses an INT_EN register for masking the reset, should
the .mask_reset_inv = true flag be set here?

Without the inversion flag, the bitwise masking logic in
s3c2410wdt_mask_wdt_reset() evaluates to (mask ^ false). For INT_EN
registers, this typically writes 1 when intending to mask the reset, and 0
when intending to unmask it, effectively inverting the logic.

> +	.mask_bit = 2,
> +	.rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET,
> +	.rst_stat_bit = 24,
> +	.quirks = QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_MASK_RESET | \
> +		  QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_AUTO_DISABLE | \
> +		  QUIRK_HAS_DBGACK_BIT,
> +};

[Severity: High]
Will this cause unintentional writes to offset 0x0000 of the PMU regmap?

This variant declares QUIRK_HAS_PMU_AUTO_DISABLE but omits .disable_reg.
Since struct fields default to zero, when s3c2410wdt_enable() checks for
this quirk and calls s3c2410wdt_disable_wdt_reset() during driver probe:

s3c2410wdt_disable_wdt_reset()
    regmap_update_bits(wdt->pmureg, wdt->drv_data->disable_reg, mask_val, val);

regmap_update_bits() will blindly write to offset 0x0000.

[ ... ]

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260817-for-next-lucky7-watchdog-v1-0-a14370e20b92@member.fsf.org?part=2

Re: [PATCH 2/2] watchdog: s3c2410_wdt: Add exynos5515-wdt compatible data

[Aiden Isik]

> Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
> - [High] The `drv_data_exynos5515` variant declares `QUIRK_HAS_PMU_AUTO_DISABLE` but fails to initialize `.disable_reg`, causing unintentional writes to PMU offset 0x0000.
> - [High] The `drv_data_exynos5515` variant uses an 'INT_EN' register for masking watchdog reset, but omits the `.mask_reset_inv = true` flag, inverting the WDT reset mask logic.
> - [Medium] Incorrect use of an Exynos Auto v920 register macro (`EXYNOSAUTOV920_CLUSTER0_NONCPU_INT_EN`) in an Exynos 5515 variant.
> --
> 
> --- Patch [2]: [PATCH 2/2] watchdog: s3c2410_wdt: Add exynos5515-wdt compatible data ---
> commit dcaab4881777bc5f5ce1a532adad7c17046164a8
> Author: Aiden Isik <aidenisik@member.fsf.org>
> 
> watchdog: s3c2410_wdt: Add exynos5515-wdt compatible data
> 
> This commit adds driver data and a compatible string for the Exynos5515
> SoC's watchdog timer.
> 
> > diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c
> > index e31f93db05096..7299dfdb0c099 100644
> > --- a/drivers/watchdog/s3c2410_wdt.c
> > +++ b/drivers/watchdog/s3c2410_wdt.c
> 
> [ ... ]
> 
> > @@ -232,6 +232,16 @@ static const struct s3c2410_wdt_variant drv_data_exynos5420 = {
> >  		  QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_AUTO_DISABLE,
> >  };
> >
> > +static const struct s3c2410_wdt_variant drv_data_exynos5515 = {
> > +	.mask_reset_reg = EXYNOSAUTOV920_CLUSTER0_NONCPU_INT_EN,
> 
> [Severity: Medium]
> Is this intentionally using an Exynos Auto v920 register macro for an
> Exynos 5515 variant, or could this be a copy-paste error?
> 

This is intentional.

> [Severity: High]
> Since this variant uses an INT_EN register for masking the reset, should
> the .mask_reset_inv = true flag be set here?
> 
> Without the inversion flag, the bitwise masking logic in
> s3c2410wdt_mask_wdt_reset() evaluates to (mask ^ false). For INT_EN
> registers, this typically writes 1 when intending to mask the reset, and 0
> when intending to unmask it, effectively inverting the logic.
> 
> > +	.mask_bit = 2,
> > +	.rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET,
> > +	.rst_stat_bit = 24,
> > +	.quirks = QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_MASK_RESET | \
> > +		  QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_AUTO_DISABLE | \
> > +		  QUIRK_HAS_DBGACK_BIT,
> > +};
> 

Possibly, will wait for maintainer input.

> [Severity: High]
> Will this cause unintentional writes to offset 0x0000 of the PMU regmap?
> 
> This variant declares QUIRK_HAS_PMU_AUTO_DISABLE but omits .disable_reg.
> Since struct fields default to zero, when s3c2410wdt_enable() checks for
> this quirk and calls s3c2410wdt_disable_wdt_reset() during driver probe:
> 
> s3c2410wdt_disable_wdt_reset()
>     regmap_update_bits(wdt->pmureg, wdt->drv_data->disable_reg, mask_val, val);
> 
> regmap_update_bits() will blindly write to offset 0x0000.
> 
> [ ... ]
> 
> --

Again, will wait for maintainer input.

> Sashiko AI review · https://sashiko.dev/#/patchset/20260817-for-next-lucky7-watchdog-v1-0-a14370e20b92@member.fsf.org?part=2
>