Re: [PATCH 1/4] dt-bindings: usb: Document ST UCPD

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Low] Missing array bounds constraint for `vconn-gpios` property
- [Low] Invalid 2-cell `interrupts` property in the GIC example
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--- Patch [1]: [PATCH 1/4] dt-bindings: usb: Document ST UCPD ---
commit aa08ea31b02f8625de21d6b8fefbebccc2a9ddcf
Author: Marek Vasut <marex@nabladev.com>

dt-bindings: usb: Document ST UCPD

This commit introduces the device tree binding documentation for the ST
UCPD Type-C controller on STM32MP25. It describes the physical layer of
Power Delivery, CC signaling, and required external Vbus/Vconn controls.

> diff --git a/Documentation/devicetree/bindings/usb/st,stm32mp25-ucpd.yaml b/Documentation/devicetree/bindings/usb/st,stm32mp25-ucpd.yaml
> new file mode 100644
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/usb/st,stm32mp25-ucpd.yaml
[ ... ]
> +  resets:
> +    maxItems: 1
> +
> +  reset-names:
> +    const: phy
> +
> +  vconn-gpios:
> +    description: GPIOs used to control CC1 and CC2 Vconn

[Severity: Low]
Should this property have a constraint like maxItems: 2?

Since the description specifies it controls CC1 and CC2 Vconn, adding an
explicit array bounds constraint would prevent device tree validation from
silently accepting an arbitrary number of GPIOs.

> +
> +  vdd33-supply:
> +    description: Regulator that supplies the CC lines driver
[ ... ]
> +examples:
> +  - |
> +    #include <dt-bindings/clock/st,stm32mp25-rcc.h>
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +    #include <dt-bindings/reset/st,stm32mp25-rcc.h>
> +
> +    ucpd: phy@480a0000 {
> +        compatible = "st,stm32mp25-ucpd";
> +        reg = <0x480a0000 0x1000>;
> +        access-controllers = <&rifsc 69>;
> +        clocks = <&rcc CK_BUS_USBTC>, <&rcc CK_KER_USBTC>;
> +        clock-names = "apb", "ker";
> +        interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;

[Severity: Low]
Is this interrupt definition missing a cell?

The example includes arm-gic.h, which expects a 3-cell interrupt definition
such as <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>. 

Using a 2-cell definition here might cause the dtbs_check validation to 
complain about standard interrupt controllers, or it might lead developers 
to copy an invalid configuration into their device trees.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260819163410.119755-1-marex@nabladev.com?part=1