[PATCH v1 0/3] arm64: dts: imx9x: Fix PCIe memory window overlap with System RAM

[PATCH v1 0/3] arm64: dts: imx9x: Fix PCIe memory window overlap with System RAM

[hongxing.zhu]

This patch series fixes PCIe non-prefetchable memory window overlap with
system DRAM on i.MX9 series SoCs (imx95, imx94, and imx943).

The current CPU address 0xe0000000 conflicts with DRAM regions. Sashiko
reports the similar potential issue in below review:
https://lore.kernel.org/imx/20260524151347.BD92A1F000E9@smtp.kernel.org/

The fix relocates the CPU address to 0x10000000, a reserved and safe range.
The PCI bus address and window size remain unchanged.

Richard Zhu (3):
  arm64: dts: imx95: Avoid 32-bit PCIe window System RAM overlap
  arm64: dts: imx94: Avoid 32-bit pcie window system ram overlap
  arm64: dts: imx943: Avoid 32-bit PCIe window System RAM overlap

[PATCH v1 1/3] arm64: dts: imx95: Avoid 32-bit PCIe window System RAM
[PATCH v1 2/3] arm64: dts: imx94: Avoid 32-bit pcie window system ram
[PATCH v1 3/3] arm64: dts: imx943: Avoid 32-bit PCIe window System

arch/arm64/boot/dts/freescale/imx94.dtsi  | 2 +-
arch/arm64/boot/dts/freescale/imx943.dtsi | 2 +-
arch/arm64/boot/dts/freescale/imx95.dtsi  | 4 ++--
3 files changed, 4 insertions(+), 4 deletions(-)

[PATCH v1 1/3] arm64: dts: imx95: Avoid 32-bit PCIe window System RAM overlap

[hongxing.zhu]

From: Richard Zhu <hongxing.zhu@nxp.com>

Move the PCIe non-prefetchable memory CPU address from 0xe0000000
to 0x10000000 to avoid overlap with DRAM. The 0x10000000 range is
reserved and safe to use.

Fixes: dbecf38e60d4e ("arm64: dts: imx95: Correct PCIe outbound address space configuration")
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx95.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi
index 38fc47024841f..0f03b85aaec17 100644
--- a/arch/arm64/boot/dts/freescale/imx95.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx95.dtsi
@@ -1948,7 +1948,7 @@ pcie0: pcie@4c300000 {
 			      <0 0x4c340000 0 0x4000>;
 			reg-names = "dbi", "config", "atu", "app";
 			ranges = <0x43000000 0x9 0x00000000 0x9 0x00000000 0x0 0xe0000000>,
-				 <0x82000000 0x0 0xe0000000 0x9 0xe0000000 0x0 0x10000000>,
+				 <0x82000000 0x0 0x10000000 0x9 0xe0000000 0x0 0x10000000>,
 				 <0x81000000 0x0 0x00000000 0x9 0xf0000000 0x0 0x00100000>;
 			#address-cells = <3>;
 			#size-cells = <2>;
@@ -2039,7 +2039,7 @@ pcie1: pcie@4c380000 {
 			      <0 0x4c3c0000 0 0x4000>;
 			reg-names = "dbi", "config", "atu", "app";
 			ranges = <0x43000000 0xa 0x00000000 0xa 0x00000000 0x0 0xe0000000>,
-				 <0x82000000 0x0 0xe0000000 0xa 0xe0000000 0x0 0x10000000>,
+				 <0x82000000 0x0 0x10000000 0xa 0xe0000000 0x0 0x10000000>,
 				 <0x81000000 0x0 0x00000000 0xa 0xf0000000 0x0 0x00100000>;
 			#address-cells = <3>;
 			#size-cells = <2>;

base-commit: eba4724641990bd9975ca10ababe726b6143f0b6
-- 
2.34.1

Re: [PATCH v1 1/3] arm64: dts: imx95: Avoid 32-bit PCIe window System RAM overlap

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The commit message inaccurately claims to change the 'CPU address', but the patch actually changes the 'PCI address'.
--

--- Patch [1]: [PATCH v1 1/3] arm64: dts: imx95: Avoid 32-bit PCIe window System RAM overlap ---
commit 1e55a58df93bb33b1e5b78cb2403b958366907f0
Author: Richard Zhu <hongxing.zhu@nxp.com>

arm64: dts: imx95: Avoid 32-bit PCIe window System RAM overlap

This commit updates the device tree configuration for the PCIe controllers
on the imx95 platform. It adjusts the ranges property to prevent memory
window overlaps.

> Move the PCIe non-prefetchable memory CPU address from 0xe0000000
> to 0x10000000 to avoid overlap with DRAM.

[Severity: Medium]
Is this description of the change accurate?

The device tree ranges property uses the format:
<PCI_HI PCI_MID PCI_LO CPU_HI CPU_LO SIZE_HI SIZE_LO>

> diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi
> --- a/arch/arm64/boot/dts/freescale/imx95.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi
> @@ -1948,7 +1948,7 @@ pcie0: pcie@4c300000 {
[ ... ]
>  			reg-names = "dbi", "config", "atu", "app";
>  			ranges = <0x43000000 0x9 0x00000000 0x9 0x00000000 0x0 0xe0000000>,
> -				 <0x82000000 0x0 0xe0000000 0x9 0xe0000000 0x0 0x10000000>,
> +				 <0x82000000 0x0 0x10000000 0x9 0xe0000000 0x0 0x10000000>,

Looking at the modification to pcie0, the CPU (parent) bus address is
represented by the 4th and 5th cells (0x9 0xe0000000). These cells remain
unchanged in this patch.

The cell that is updated from 0xe0000000 to 0x10000000 is the 3rd cell,
which corresponds to the lower 32 bits of the PCI (child) bus address.

Could the commit message be clarified to state that the PCI address is
being changed, or was the intent to actually update the CPU address in
the 5th cell?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260820083620.877251-1-hongxing.zhu@oss.nxp.com?part=1

Re: [PATCH v1 1/3] arm64: dts: imx95: Avoid 32-bit PCIe window System RAM overlap

[Frank Li]

On Thu, Aug 20, 2026 at 08:42:07AM +0000, sashiko-bot@kernel.org wrote:
> Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
> - [Medium] The commit message inaccurately claims to change the 'CPU address', but the patch actually changes the 'PCI address'.
> --
>
> --- Patch [1]: [PATCH v1 1/3] arm64: dts: imx95: Avoid 32-bit PCIe window System RAM overlap ---
> commit 1e55a58df93bb33b1e5b78cb2403b958366907f0
> Author: Richard Zhu <hongxing.zhu@nxp.com>
>
> arm64: dts: imx95: Avoid 32-bit PCIe window System RAM overlap
>
> This commit updates the device tree configuration for the PCIe controllers
> on the imx95 platform. It adjusts the ranges property to prevent memory
> window overlaps.
>
> > Move the PCIe non-prefetchable memory CPU address from 0xe0000000
> > to 0x10000000 to avoid overlap with DRAM.
>
> [Severity: Medium]
> Is this description of the change accurate?
>
> The device tree ranges property uses the format:
> <PCI_HI PCI_MID PCI_LO CPU_HI CPU_LO SIZE_HI SIZE_LO>
>
> > diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi
> > --- a/arch/arm64/boot/dts/freescale/imx95.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi
> > @@ -1948,7 +1948,7 @@ pcie0: pcie@4c300000 {
> [ ... ]
> >  			reg-names = "dbi", "config", "atu", "app";
> >  			ranges = <0x43000000 0x9 0x00000000 0x9 0x00000000 0x0 0xe0000000>,
> > -				 <0x82000000 0x0 0xe0000000 0x9 0xe0000000 0x0 0x10000000>,
> > +				 <0x82000000 0x0 0x10000000 0x9 0xe0000000 0x0 0x10000000>,
>
> Looking at the modification to pcie0, the CPU (parent) bus address is
> represented by the 4th and 5th cells (0x9 0xe0000000). These cells remain
> unchanged in this patch.
>
> The cell that is updated from 0xe0000000 to 0x10000000 is the 3rd cell,
> which corresponds to the lower 32 bits of the PCI (child) bus address.
>
> Could the commit message be clarified to state that the PCI address is
> being changed, or was the intent to actually update the CPU address in
> the 5th cell?

Sashiko is correct, update your commit message, it is not "cpu address"

it is "PCI bus address", you'd better refer to old sashio thread or
prevous discuss link.

Frank

>
> --
> Sashiko AI review · https://sashiko.dev/#/patchset/20260820083620.877251-1-hongxing.zhu@oss.nxp.com?part=1

[PATCH v1 2/3] arm64: dts: imx94: Avoid 32-bit pcie window system ram overlap

[hongxing.zhu]

From: Richard Zhu <hongxing.zhu@nxp.com>

Move the PCIe non-prefetchable memory CPU address from 0xe0000000
to 0x10000000 to avoid overlap with DRAM. The 0x10000000 range is
reserved and safe to use.

Fixes: ffccbd6804e88 ("arm64: dts: imx94: Correct PCIe outbound address space configuration")
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx94.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/freescale/imx94.dtsi b/arch/arm64/boot/dts/freescale/imx94.dtsi
index 34833e62bd796..afaaf70417d23 100644
--- a/arch/arm64/boot/dts/freescale/imx94.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx94.dtsi
@@ -1379,7 +1379,7 @@ pcie0: pcie@4c300000 {
 			      <0 0x4c340000 0 0x4000>;
 			reg-names = "dbi", "config", "atu", "app";
 			ranges = <0x43000000 0x9 0x00000000 0x9 0x00000000 0x0 0xe0000000>,
-				 <0x82000000 0x0 0xe0000000 0x9 0xe0000000 0x0 0x10000000>,
+				 <0x82000000 0x0 0x10000000 0x9 0xe0000000 0x0 0x10000000>,
 				 <0x81000000 0x0 0x00000000 0x9 0xf0000000 0x0 0x00100000>;
 			#address-cells = <3>;
 			#size-cells = <2>;
-- 
2.34.1

Re: [PATCH v1 2/3] arm64: dts: imx94: Avoid 32-bit pcie window system ram overlap

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The commit message inaccurately claims to modify the 'CPU address', but the code actually modifies the PCIe bus address.
--

--- Patch [2]: [PATCH v1 2/3] arm64: dts: imx94: Avoid 32-bit pcie window system ram overlap ---
commit e35c73490a85a542f882f45cf6fb1b821101d403
Author: Richard Zhu <hongxing.zhu@nxp.com>

arm64: dts: imx94: Avoid 32-bit pcie window system ram overlap

This commit addresses a memory overlap issue between the PCIe non-prefetchable
memory and system RAM. It adjusts the address space configuration in the imx94
device tree to use a reserved, safe range.

> diff --git a/arch/arm64/boot/dts/freescale/imx94.dtsi b/arch/arm64/boot/dts/freescale/imx94.dtsi
> --- a/arch/arm64/boot/dts/freescale/imx94.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx94.dtsi
> @@ -1379,7 +1379,7 @@ pcie0: pcie@4c300000 {
>  			      <0 0x4c340000 0 0x4000>;
>  			reg-names = "dbi", "config", "atu", "app";
>  			ranges = <0x43000000 0x9 0x00000000 0x9 0x00000000 0x0 0xe0000000>,
> -				 <0x82000000 0x0 0xe0000000 0x9 0xe0000000 0x0 0x10000000>,
> +				 <0x82000000 0x0 0x10000000 0x9 0xe0000000 0x0 0x10000000>,

[Severity: Medium]
The commit message states "Move the PCIe non-prefetchable memory CPU address
from 0xe0000000 to 0x10000000". Is this description accurate?

Looking at the Device Tree ranges property format:
<child-bus-address> <parent-bus-address> <length>

The 4th and 5th cells representing the parent (CPU) address (0x9 0xe0000000)
remain unchanged here. The third cell (the low 32 bits of the PCIe bus
address) is being modified from 0xe0000000 to 0x10000000.

Could the commit message be updated to correctly reflect that the PCIe bus
address is being changed rather than the CPU address?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260820083620.877251-1-hongxing.zhu@oss.nxp.com?part=2

[PATCH v1 3/3] arm64: dts: imx943: Avoid 32-bit PCIe window System RAM overlap

[hongxing.zhu]

From: Richard Zhu <hongxing.zhu@nxp.com>

Move the PCIe non-prefetchable memory CPU address from 0xe0000000
to 0x10000000 to avoid overlap with DRAM. The 0x10000000 range is
reserved and safe to use.

Fixes: 6de3a7d7a4f65 ("arm64: dts: imx943: Correct PCIe outbound address space configuration")
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx943.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/freescale/imx943.dtsi b/arch/arm64/boot/dts/freescale/imx943.dtsi
index 01152fd0efa5e..a564488d9cd7d 100644
--- a/arch/arm64/boot/dts/freescale/imx943.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx943.dtsi
@@ -219,7 +219,7 @@ pcie1: pcie@4c380000 {
 			      <0 0x4c3c0000 0 0x4000>;
 			reg-names = "dbi", "config", "atu", "app";
 			ranges = <0x43000000 0xa 0x00000000 0xa 0x00000000 0x0 0xe0000000>,
-				 <0x82000000 0x0 0xe0000000 0xa 0xe0000000 0x0 0x10000000>,
+				 <0x82000000 0x0 0x10000000 0xa 0xe0000000 0x0 0x10000000>,
 				 <0x81000000 0x0 0x00000000 0xa 0xf0000000 0x0 0x00100000>;
 			#address-cells = <3>;
 			#size-cells = <2>;
-- 
2.34.1

Re: [PATCH v1 3/3] arm64: dts: imx943: Avoid 32-bit PCIe window System RAM overlap

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The commit message incorrectly claims to modify the CPU address instead of the PCIe bus address.
--

--- Patch [3]: [PATCH v1 3/3] arm64: dts: imx943: Avoid 32-bit PCIe window System RAM overlap ---
commit 06a8fbf859a9df88332de43a908bb91e8293759a
Author: Richard Zhu <hongxing.zhu@nxp.com>

arm64: dts: imx943: Avoid 32-bit PCIe window System RAM overlap

This commit updates the PCIe non-prefetchable memory range for the imx943 to
avoid overlapping with DRAM. It adjusts the outbound address space
configuration to use a safe, reserved range.

> diff --git a/arch/arm64/boot/dts/freescale/imx943.dtsi b/arch/arm64/boot/dts/freescale/imx943.dtsi
> --- a/arch/arm64/boot/dts/freescale/imx943.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx943.dtsi
[ ... ]
> @@ -219,7 +219,7 @@ pcie1: pcie@4c380000 {
>  			      <0 0x4c3c0000 0 0x4000>;
>  			reg-names = "dbi", "config", "atu", "app";
>  			ranges = <0x43000000 0xa 0x00000000 0xa 0x00000000 0x0 0xe0000000>,
> -				 <0x82000000 0x0 0xe0000000 0xa 0xe0000000 0x0 0x10000000>,
> +				 <0x82000000 0x0 0x10000000 0xa 0xe0000000 0x0 0x10000000>,

[Severity: Medium]
The commit message states that this moves the PCIe non-prefetchable memory
CPU address from 0xe0000000 to 0x10000000. Is this description accurate?

Looking at the ranges property in pcie1, the format is
<child_hi child_mid child_low parent_hi parent_low size_hi size_low>.

This change modifies the third cell (child_low), which represents the PCIe
bus address, from 0xe0000000 to 0x10000000. However, the fourth and fifth
cells representing the parent CPU address remain completely unchanged at
0xa 0xe0000000.

Does the code need to change the parent CPU address cells instead, or should
the commit message be updated to reflect that the child bus address is what
is actually being modified?

>  				 <0x81000000 0x0 0x00000000 0xa 0xf0000000 0x0 0x00100000>;
>  			#address-cells = <3>;

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260820083620.877251-1-hongxing.zhu@oss.nxp.com?part=3