Re: [PATCH v6 2/4] arm64: dts: qcom: sm8550: add UART11 node

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:

Pre-existing issues:
- [High] The SPI nodes `spi11` and `spi12` in `sm8550.dtsi` incorrectly configure their GPI DMA channels to use the I2C protocol (`QCOM_GPI_I2C`) instead of the SPI protocol (`QCOM_GPI_SPI`).
--

--- Patch [2]: [PATCH v6 2/4] arm64: dts: qcom: sm8550: add UART11 node ---
commit 367c60765aa391aa9b6b3277a433dd844de194db
Author: Alexandre Hamamdjian <azkali.limited@gmail.com>

arm64: dts: qcom: sm8550: add UART11 node

This commit adds the UART11 controller node and its default pinctrl state
to sm8550.dtsi. It reuses the 120MHz OPP table already utilized by the
i2c11 and spi11 nodes.

> diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> @@ -1442,6 +1442,24 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
>  				status = "disabled";
>  			};
>  
> +			uart11: serial@88c000 {

[Severity: High]
This is a pre-existing issue, but while reviewing the new uart11 node and
its surrounding context, I noticed that the existing spi11 and spi12 nodes
appear to incorrectly configure their GPI DMA channels to use the I2C
protocol:

spi11 {
        ...
        dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
               <&gpi_dma2 1 3 QCOM_GPI_I2C>;
}

spi12 {
        ...
        dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
               <&gpi_dma2 1 4 QCOM_GPI_I2C>;
}

Does configuring the SPI controller's DMA engine with QCOM_GPI_I2C instead
of QCOM_GPI_SPI cause the hardware to expect I2C command sequences,
breaking SPI DMA functionality for any peripherals attached to these ports?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260824-pocketds-v6-0-370161574ca2@gmail.com?part=2