* [PATCH 0/4] Add PCIe support for Qualcomm Nord platform
@ 2026-08-25 3:40 Krishna Chaitanya Chundru
2026-08-25 3:40 ` [PATCH 1/4] dt-bindings: phy: qcom: add Nord QMP PCIe PHY binding Krishna Chaitanya Chundru
` (3 more replies)
0 siblings, 4 replies; 6+ messages in thread
From: Krishna Chaitanya Chundru @ 2026-08-25 3:40 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Bjorn Helgaas, Bjorn Andersson,
Maxime Chevallier, Philipp Zabel
Cc: Krishna Chaitanya Chundru, linux-arm-msm, linux-phy, devicetree,
linux-kernel, linux-pci
This series adds PCIe support for the Qualcomm Nord (SA8797P) platform.
Nord has a single Gen5-capable QMP PCIe PHY block split into four
independently-clocked and independently-resettable ports (A/B/C/D).
Firmware selects the active lane topology at boot via a TCSR
configuration register, and the same PHY block can appear as a single
x16 port, x8+x8, x8+x4+x4, or x8+x4+x2+x2 depending on that mode. This
is similar in spirit to the Glymur multi-PHY support already posted,
except Nord's PHY registers are programmed by Linux rather than by
firmware, so this series adds the PLL, TXRXZ, PCS and PCS-lane init
tables along with the power-up/power-down/soft-reset sequencing needed
to bring each port up.
The series also documents and wires up the qcom,nord-pcie compatible
(reusing the existing SA8775P PCIe controller binding), and adds a
CORE_CLK_CGC_DIS/AUX_PWR_DET workaround required to avoid a timing
convergence issue in the PCIe power domain.
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
---
To: Vinod Koul <vkoul@kernel.org>
To: Neil Armstrong <neil.armstrong@linaro.org>
To: Rob Herring <robh@kernel.org>
To: Krzysztof Kozlowski <krzk+dt@kernel.org>
To: Conor Dooley <conor+dt@kernel.org>
To: Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
To: Lorenzo Pieralisi <lpieralisi@kernel.org>
To: Krzysztof Wilczyński <kwilczynski@kernel.org>
To: Manivannan Sadhasivam <mani@kernel.org>
To: Bjorn Helgaas <bhelgaas@google.com>
To: Bjorn Andersson <andersson@kernel.org>
To: Maxime Chevallier <maxime.chevallier@bootlin.com>
To: Philipp Zabel <p.zabel@pengutronix.de>
Cc: linux-arm-msm@vger.kernel.org
Cc: linux-phy@lists.infradead.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-pci@vger.kernel.org
---
Krishna Chaitanya Chundru (4):
dt-bindings: phy: qcom: add Nord QMP PCIe PHY binding
dt-bindings: pci: qcom: add Nord PCIe controller compatible
PCI: qcom: Add CGC disable workaround for Nord PCIe
phy: qcom: qmp-pcie: Add Nord Gen5x16 PCIe multi-PHY support
.../devicetree/bindings/pci/qcom,pcie-sa8775p.yaml | 1 +
.../bindings/phy/qcom,nord-qmp-pcie-phy.yaml | 276 +++++
drivers/pci/controller/dwc/pcie-qcom.c | 16 +
drivers/phy/qualcomm/phy-qcom-qmp-pcie-multiphy.c | 1077 +++++++++++++++++++-
drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_40.h | 56 +
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_40.h | 14 +
.../qualcomm/phy-qcom-qmp-qserdes-com-pcie-v6_40.h | 94 ++
.../phy-qcom-qmp-qserdes-txrxz-pcie-v6_40.h | 194 ++++
8 files changed, 1688 insertions(+), 40 deletions(-)
---
base-commit: c76bb6ed13d3c7dcd1ab3b248299c5a6f1460ec4
change-id: 20260810-nord-461809f1d5ae
Best regards,
--
Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 1/4] dt-bindings: phy: qcom: add Nord QMP PCIe PHY binding
2026-08-25 3:40 [PATCH 0/4] Add PCIe support for Qualcomm Nord platform Krishna Chaitanya Chundru
@ 2026-08-25 3:40 ` Krishna Chaitanya Chundru
2026-08-25 9:04 ` Krzysztof Kozlowski
2026-08-25 3:40 ` [PATCH 2/4] dt-bindings: pci: qcom: add Nord PCIe controller compatible Krishna Chaitanya Chundru
` (2 subsequent siblings)
3 siblings, 1 reply; 6+ messages in thread
From: Krishna Chaitanya Chundru @ 2026-08-25 3:40 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Bjorn Helgaas, Bjorn Andersson,
Maxime Chevallier, Philipp Zabel
Cc: Krishna Chaitanya Chundru, linux-arm-msm, linux-phy, devicetree,
linux-kernel, linux-pci
Document the PCIe PHY found on the Qualcomm Nord platform.
Nord has a Gen5-capable QMP PCIe PHY that can operate in multiple
lane configurations using four PHY segments (A/B/C/D). The active
topology is selected by firmware through a TCSR configuration
register and may be configured as x16, x8+x8, x8+x4+x4, or
x8+x4+x2+x2.
The binding describes the register regions, clocks, resets, power
domains, regulators, PHY provider interface, clock provider interface,
and the qcom,link-mode property used by the driver to discover the
active lane configuration programmed by firmware.
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
---
.../bindings/phy/qcom,nord-qmp-pcie-phy.yaml | 276 +++++++++++++++++++++
1 file changed, 276 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/qcom,nord-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,nord-qmp-pcie-phy.yaml
new file mode 100644
index 000000000000..3575e99dadfd
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/qcom,nord-qmp-pcie-phy.yaml
@@ -0,0 +1,276 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/qcom,nord-qmp-pcie-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Nord QMP Bifurcated PCIe PHY
+
+maintainers:
+ - Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
+
+description: |
+ The Qualcomm Nord PCIe PHY is a Gen5-capable QMP PCIe PHY composed
+ of four PHY ports (A/B/C/D). The ports can be combined to support
+ multiple lane topologies, including x16, x8+x8, x8+x4+x4 and
+ x8+x4+x2+x2 configurations.
+
+ The selected topology is determined by the PCIe link configuration mode
+ programmed in TCSR registers. Depending on the selected mode, PHY ports
+ may operate independently or be grouped together to form wider PCIe links.
+
+ Each port provides dedicated register space, clocks, resets and power
+ resources required for PHY operation.
+
+properties:
+ compatible:
+ enum:
+ - qcom,nord-qmp-gen5x16-pcie-phy
+
+ reg:
+ minItems: 4
+ maxItems: 4
+
+ reg-names:
+ items:
+ - const: port_a
+ - const: port_b
+ - const: port_c
+ - const: port_d
+
+ clocks:
+ minItems: 17
+ maxItems: 17
+
+ clock-names:
+ items:
+ - const: aux_a
+ - const: cfg_ahb_a
+ - const: rchng_a
+ - const: pipe_a
+ - const: aux_b
+ - const: cfg_ahb_b
+ - const: rchng_b
+ - const: pipe_b
+ - const: aux_c
+ - const: cfg_ahb_c
+ - const: rchng_c
+ - const: pipe_c
+ - const: aux_d
+ - const: cfg_ahb_d
+ - const: rchng_d
+ - const: pipe_d
+ - const: ref
+
+ power-domains:
+ minItems: 4
+ maxItems: 4
+
+ power-domain-names:
+ items:
+ - const: port_a
+ - const: port_b
+ - const: port_c
+ - const: port_d
+
+ resets:
+ minItems: 8
+ maxItems: 8
+
+ reset-names:
+ items:
+ - const: port_a
+ - const: port_a_nocsr
+ - const: port_b
+ - const: port_b_nocsr
+ - const: port_c
+ - const: port_c_nocsr
+ - const: port_d
+ - const: port_d_nocsr
+
+ vdda-phy-a-supply: true
+
+ vdda-phy-b-supply: true
+
+ vdda-phy-c-supply: true
+
+ vdda-phy-d-supply: true
+
+ vdda-pll-a-supply: true
+
+ vdda-pll-b-supply: true
+
+ vdda-pll-c-supply: true
+
+ vdda-pll-d-supply: true
+
+ qcom,link-mode:
+ description: |
+ Reference to the TCSR syscon and the offset of the
+ TCSR_PCIE_LINK_CONFIG_MODE register.
+ 0 (QMP_PCIE_NORD_MODE_X16) — all ports ganged as x16
+ 1 (QMP_PCIE_NORD_MODE_X8_X8) — x8 (port A) + x8 (port B+C+D)
+ 2 (QMP_PCIE_NORD_MODE_X8_X4_X4) — x8 (A) + x4 (B) + x4 (C+D)
+ 3 (QMP_PCIE_NORD_MODE_X8_X4_X2_X2)— x8 (A) + x4 (B) + x2 (C) + x2 (D)
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ - items:
+ - description: Phandle of the TCSR syscon
+ - description: Offset of TCSR_PCIE_LINK_CONFIG_MODE register
+
+ "#clock-cells":
+ const: 1
+ description: |
+ Selects the pipe clock output by port index (0=A, 1=B, 2=C, 3=D).
+ GCC pipe-clock mux parents reference this provider.
+
+ clock-output-names:
+ minItems: 1
+ maxItems: 4
+ description: Names for each port pipe clock output.
+
+ "#phy-cells":
+ const: 1
+ description: |
+ Selects the PHY instance by index:
+ 0 — port A (up to Gen4 x8; anchor in x16 mode)
+ 1 — port B (up to Gen4 x4)
+ 2 — port C (up to Gen2 x2)
+ 3 — port D (up to Gen2 x2)
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+ - clock-names
+ - power-domains
+ - power-domain-names
+ - resets
+ - reset-names
+ - vdda-phy-a-supply
+ - vdda-phy-b-supply
+ - vdda-phy-c-supply
+ - vdda-phy-d-supply
+ - vdda-pll-a-supply
+ - vdda-pll-b-supply
+ - vdda-pll-c-supply
+ - vdda-pll-d-supply
+ - qcom,link-mode
+ - "#clock-cells"
+ - clock-output-names
+ - "#phy-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,nord-gcc.h>
+ #include <dt-bindings/clock/qcom,nord-tcsrcc.h>
+ #include <dt-bindings/phy/phy-qcom-qmp.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ phy@1b00000 {
+ compatible = "qcom,nord-qmp-gen5x16-pcie-phy";
+
+ reg = <0x0 0x01b00000 0x0 0x10000>,
+ <0x0 0x01b10000 0x0 0x10000>,
+ <0x0 0x01b20000 0x0 0x10000>,
+ <0x0 0x01b30000 0x0 0x10000>;
+ reg-names = "port_a",
+ "port_b",
+ "port_c",
+ "port_d";
+
+ clocks = <&gcc GCC_PCIE_A_PHY_AUX_CLK>,
+ <&gcc GCC_PCIE_A_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_A_PHY_RCHNG_CLK>,
+ <&gcc GCC_PCIE_A_PIPE_CLK>,
+ <&gcc GCC_PCIE_B_PHY_AUX_CLK>,
+ <&gcc GCC_PCIE_B_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_B_PHY_RCHNG_CLK>,
+ <&gcc GCC_PCIE_B_PIPE_CLK>,
+ <&gcc GCC_PCIE_C_PHY_AUX_CLK>,
+ <&gcc GCC_PCIE_C_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_C_PHY_RCHNG_CLK>,
+ <&gcc GCC_PCIE_C_PIPE_CLK>,
+ <&gcc GCC_PCIE_D_PHY_AUX_CLK>,
+ <&gcc GCC_PCIE_D_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_D_PHY_RCHNG_CLK>,
+ <&gcc GCC_PCIE_D_PIPE_CLK>,
+ <&tcsrcc TCSR_PCIE_CLKREF_EN>;
+ clock-names = "aux_a",
+ "cfg_ahb_a",
+ "rchng_a",
+ "pipe_a",
+ "aux_b",
+ "cfg_ahb_b",
+ "rchng_b",
+ "pipe_b",
+ "aux_c",
+ "cfg_ahb_c",
+ "rchng_c",
+ "pipe_c",
+ "aux_d",
+ "cfg_ahb_d",
+ "rchng_d",
+ "pipe_d",
+ "ref";
+
+ assigned-clocks = <&gcc GCC_PCIE_A_PHY_RCHNG_CLK>,
+ <&gcc GCC_PCIE_B_PHY_RCHNG_CLK>,
+ <&gcc GCC_PCIE_C_PHY_RCHNG_CLK>,
+ <&gcc GCC_PCIE_D_PHY_RCHNG_CLK>;
+ assigned-clock-rates = <100000000>, <100000000>,
+ <100000000>, <100000000>;
+
+ power-domains = <&gcc GCC_PCIE_A_PHY_GDSC>,
+ <&gcc GCC_PCIE_B_PHY_GDSC>,
+ <&gcc GCC_PCIE_C_PHY_GDSC>,
+ <&gcc GCC_PCIE_D_PHY_GDSC>;
+ power-domain-names = "port_a",
+ "port_b",
+ "port_c",
+ "port_d";
+
+ resets = <&gcc GCC_PCIE_A_PHY_COM_BCR>,
+ <&gcc GCC_PCIE_A_NOCSR_COM_PHY_BCR>,
+ <&gcc GCC_PCIE_B_PHY_COM_BCR>,
+ <&gcc GCC_PCIE_B_NOCSR_COM_PHY_BCR>,
+ <&gcc GCC_PCIE_C_PHY_COM_BCR>,
+ <&gcc GCC_PCIE_C_NOCSR_COM_PHY_BCR>,
+ <&gcc GCC_PCIE_D_PHY_COM_BCR>,
+ <&gcc GCC_PCIE_D_NOCSR_COM_PHY_BCR>;
+ reset-names = "port_a",
+ "port_a_nocsr",
+ "port_b",
+ "port_b_nocsr",
+ "port_c",
+ "port_c_nocsr",
+ "port_d",
+ "port_d_nocsr";
+
+ vdda-phy-a-supply = <&vreg_l6a_1p2>;
+ vdda-phy-b-supply = <&vreg_l4a_1p2>;
+ vdda-phy-c-supply = <&vreg_l4a_1p2>;
+ vdda-phy-d-supply = <&vreg_l4a_1p2>;
+ vdda-pll-a-supply = <&vreg_l1e_0p9>;
+ vdda-pll-b-supply = <&vreg_l1e_0p9>;
+ vdda-pll-c-supply = <&vreg_l1e_0p9>;
+ vdda-pll-d-supply = <&vreg_l1e_0p9>;
+
+ qcom,link-mode = <&tcsr 0x71050>;
+
+ #clock-cells = <1>;
+ clock-output-names = "pcie_a_pipe_clk",
+ "pcie_b_pipe_clk",
+ "pcie_c_pipe_clk",
+ "pcie_d_pipe_clk";
+
+ #phy-cells = <1>;
+ status = "disabled";
+ };
+ };
--
2.34.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 2/4] dt-bindings: pci: qcom: add Nord PCIe controller compatible
2026-08-25 3:40 [PATCH 0/4] Add PCIe support for Qualcomm Nord platform Krishna Chaitanya Chundru
2026-08-25 3:40 ` [PATCH 1/4] dt-bindings: phy: qcom: add Nord QMP PCIe PHY binding Krishna Chaitanya Chundru
@ 2026-08-25 3:40 ` Krishna Chaitanya Chundru
2026-08-25 3:40 ` [PATCH 3/4] PCI: qcom: Add CGC disable workaround for Nord PCIe Krishna Chaitanya Chundru
2026-08-25 3:40 ` [PATCH 4/4] phy: qcom: qmp-pcie: Add Nord Gen5x16 PCIe multi-PHY support Krishna Chaitanya Chundru
3 siblings, 0 replies; 6+ messages in thread
From: Krishna Chaitanya Chundru @ 2026-08-25 3:40 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Bjorn Helgaas, Bjorn Andersson,
Maxime Chevallier, Philipp Zabel
Cc: Krishna Chaitanya Chundru, linux-arm-msm, linux-phy, devicetree,
linux-kernel, linux-pci
Add the qcom,nord-pcie compatible string to the Qualcomm PCIe
controller binding.
The Nord PCIe controller is compatible with the SA8775P PCIe
controller implementation and reuses the same binding definition.
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
---
Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml
index 63630a814f28..b8ba2c4449b7 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml
@@ -20,6 +20,7 @@ properties:
- const: qcom,pcie-sa8775p
- items:
- enum:
+ - qcom,nord-pcie
- qcom,pcie-qcs8300
- const: qcom,pcie-sa8775p
--
2.34.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 3/4] PCI: qcom: Add CGC disable workaround for Nord PCIe
2026-08-25 3:40 [PATCH 0/4] Add PCIe support for Qualcomm Nord platform Krishna Chaitanya Chundru
2026-08-25 3:40 ` [PATCH 1/4] dt-bindings: phy: qcom: add Nord QMP PCIe PHY binding Krishna Chaitanya Chundru
2026-08-25 3:40 ` [PATCH 2/4] dt-bindings: pci: qcom: add Nord PCIe controller compatible Krishna Chaitanya Chundru
@ 2026-08-25 3:40 ` Krishna Chaitanya Chundru
2026-08-25 3:40 ` [PATCH 4/4] phy: qcom: qmp-pcie: Add Nord Gen5x16 PCIe multi-PHY support Krishna Chaitanya Chundru
3 siblings, 0 replies; 6+ messages in thread
From: Krishna Chaitanya Chundru @ 2026-08-25 3:40 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Bjorn Helgaas, Bjorn Andersson,
Maxime Chevallier, Philipp Zabel
Cc: Krishna Chaitanya Chundru, linux-arm-msm, linux-phy, devicetree,
linux-kernel, linux-pci
Nord requires a workaround to address a timing convergence issue in the
PCIe power domain. To avoid the issue, set the CORE_CLK_CGC_DIS and
AUX_PWR_DET bits in PARF_SYS_CTRL after controller initialization.
The SLV_ACLK_CGC_DIS bit is already configured by hardware reset. This
change adds the remaining required settings as documented in
QCTDD11972446.
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
---
drivers/pci/controller/dwc/pcie-qcom.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index d8eb52857f69..9fa7ab47c86e 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -266,6 +266,7 @@ struct qcom_pcie_cfg {
bool override_no_snoop;
bool firmware_managed;
bool no_l0s;
+ bool cgc_dis_workaround;
};
struct qcom_pcie_perst {
@@ -1073,11 +1074,18 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie)
static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie)
{
const struct qcom_pcie_cfg *pcie_cfg = pcie->cfg;
+ int val;
if (pcie_cfg->override_no_snoop)
writel(WR_NO_SNOOP_OVERRIDE_EN | RD_NO_SNOOP_OVERRIDE_EN,
pcie->parf + PARF_NO_SNOOP_OVERRIDE);
+ if (pcie_cfg->cgc_dis_workaround) {
+ val = readl(pcie->parf + PARF_SYS_CTRL);
+ val |= CORE_CLK_CGC_DIS | AUX_PWR_DET;
+ writel(val, pcie->parf + PARF_SYS_CTRL);
+ }
+
qcom_pcie_set_slot_nccs(pcie->pci);
return 0;
@@ -1604,6 +1612,13 @@ static const struct qcom_pcie_cfg cfg_2_9_0 = {
.ops = &ops_2_9_0,
};
+static const struct qcom_pcie_cfg cfg_nord = {
+ .ops = &ops_1_9_0,
+ .override_no_snoop = true,
+ .no_l0s = true,
+ .cgc_dis_workaround = true,
+};
+
static const struct qcom_pcie_cfg cfg_sc8280xp = {
.ops = &ops_1_21_0,
.no_l0s = true,
@@ -2282,6 +2297,7 @@ static int qcom_pcie_resume_noirq(struct device *dev)
}
static const struct of_device_id qcom_pcie_match[] = {
+ { .compatible = "qcom,nord-pcie", .data = &cfg_nord },
{ .compatible = "qcom,pcie-apq8064", .data = &cfg_2_1_0 },
{ .compatible = "qcom,pcie-apq8084", .data = &cfg_1_0_0 },
{ .compatible = "qcom,pcie-ipq4019", .data = &cfg_2_4_0 },
--
2.34.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 4/4] phy: qcom: qmp-pcie: Add Nord Gen5x16 PCIe multi-PHY support
2026-08-25 3:40 [PATCH 0/4] Add PCIe support for Qualcomm Nord platform Krishna Chaitanya Chundru
` (2 preceding siblings ...)
2026-08-25 3:40 ` [PATCH 3/4] PCI: qcom: Add CGC disable workaround for Nord PCIe Krishna Chaitanya Chundru
@ 2026-08-25 3:40 ` Krishna Chaitanya Chundru
3 siblings, 0 replies; 6+ messages in thread
From: Krishna Chaitanya Chundru @ 2026-08-25 3:40 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Bjorn Helgaas, Bjorn Andersson,
Maxime Chevallier, Philipp Zabel
Cc: Krishna Chaitanya Chundru, linux-arm-msm, linux-phy, devicetree,
linux-kernel, linux-pci
Add support for the Nord Gen5x16 bifurcated QMP PCIe PHY.
Nord has a single PCIe PHY block split into four ports which can be
used in multiple lane configurations: x16, x8+x8, x8+x4+x4 and
x8+x4+x2+x2. The active topology is selected through the link mode
configuration register, and the driver exposes the corresponding PHY
instances based on that mode.
Unlike Glymur, where the PHY is initialized by firmware, Nord requires
Linux to program the PHY registers. Add the PLL, TXRXZ, PCS and PCS
lane initialization tables, along with the required power-up,
power-down and soft-reset sequencing.
Add per-port and grouped PHY configurations for all supported Nord
lane modes. Also add support for regular PHY resets in addition to the
NOCSR resets, and handle the shared PHY power domain by attaching it
once at the multi-PHY level and reusing it across segment groups. The
GDSC init is now done using the device created for the PHY itself
(devm_phy_create()), rather than the parent multi-PHY platform device.
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
---
drivers/phy/qualcomm/phy-qcom-qmp-pcie-multiphy.c | 1077 +++++++++++++++++++-
drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_40.h | 56 +
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_40.h | 14 +
.../qualcomm/phy-qcom-qmp-qserdes-com-pcie-v6_40.h | 94 ++
.../phy-qcom-qmp-qserdes-txrxz-pcie-v6_40.h | 194 ++++
5 files changed, 1395 insertions(+), 40 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-multiphy.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-multiphy.c
index e93cba4369fb..076b86bf9953 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-multiphy.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-multiphy.c
@@ -3,6 +3,7 @@
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
+#include <linux/bits.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/delay.h>
@@ -20,8 +21,16 @@
#include <linux/regulator/consumer.h>
#include <linux/reset.h>
#include <linux/slab.h>
+#include <linux/string.h>
+
+#include <dt-bindings/phy/phy-qcom-qmp.h>
#include "phy-qcom-qmp.h"
+#include "phy-qcom-qmp-common.h"
+#include "phy-qcom-qmp-pcs-v6_40.h"
+#include "phy-qcom-qmp-pcs-pcie-v6_40.h"
+#include "phy-qcom-qmp-qserdes-com-pcie-v6_40.h"
+#include "phy-qcom-qmp-qserdes-txrxz-pcie-v6_40.h"
#define PHY_INIT_COMPLETE_TIMEOUT_US 10000
@@ -30,8 +39,19 @@ enum qmp_pcie_glymur_link_mode {
QMP_PCIE_GLYMUR_MODE_X4X4,
};
+enum qmp_pcie_nord_link_mode {
+ QMP_PCIE_NORD_MODE_X16,
+ QMP_PCIE_NORD_MODE_X8_X8,
+ QMP_PCIE_NORD_MODE_X8_X4_X4,
+ QMP_PCIE_NORD_MODE_X8_X4_X2_X2
+};
+
enum qphy_reg_layout {
QPHY_PCS_STATUS,
+ QPHY_PCS_START_CONTROL,
+ QPHY_PCS_SW_RESET,
+ QPHY_PCS_POWER_DOWN_CONTROL,
+ QPHY_COM_BIAS_EN_CLKBUFLR_EN,
QPHY_LAYOUT_SIZE
};
@@ -39,16 +59,42 @@ static const unsigned int pciephy_v8_50_regs_layout[QPHY_LAYOUT_SIZE] = {
[QPHY_PCS_STATUS] = QPHY_V8_50_PCS_STATUS1,
};
+static const unsigned int nord_pciephy_v6_40_regs_layout[QPHY_LAYOUT_SIZE] = {
+ [QPHY_PCS_STATUS] = QPHY_V6_40_PCS_STATUS1,
+ [QPHY_PCS_START_CONTROL] = QPHY_V6_40_PCS_START_CONTROL,
+ [QPHY_PCS_SW_RESET] = QPHY_V6_40_PCS_SW_RESET,
+ [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V6_40_PCS_POWER_DOWN_CONTROL,
+ [QPHY_COM_BIAS_EN_CLKBUFLR_EN] = QSERDES_PCIE_V6_40_COM_BIAS_EN_CLKBUFLR_EN,
+};
+
struct qmp_pcie_offsets {
u16 pcs;
+ u16 pll;
+ u16 txrxz;
+ u16 pcs_lanez;
+};
+
+struct qmp_phy_cfg_tbls {
+ const struct qmp_phy_init_tbl *txrxz;
+ int txrxz_num;
+ const struct qmp_phy_init_tbl *pcs;
+ int pcs_num;
+ const struct qmp_phy_init_tbl *pcs_lanez;
+ int pcs_lanez_num;
};
struct qmp_phy_cfg {
const struct qmp_pcie_offsets *offsets;
+ struct qmp_phy_cfg_tbls tbls;
+ struct qmp_phy_init_tbl **pll_tbls;
+ int *pll_nums;
+ bool bifurcated;
const char * const *reg_names;
int num_regs;
const char * const *pd_names;
int num_pds;
+ const char * const *reset_list;
+ int num_resets;
const char * const *nocsr_reset_list;
int num_nocsr_resets;
const char * const *vreg_list;
@@ -67,6 +113,7 @@ struct qmp_pcie {
void __iomem **base;
struct clk_bulk_data *clks;
struct clk_bulk_data *pipe_clks;
+ struct reset_control_bulk_data *resets;
struct reset_control_bulk_data *nocsr_resets;
struct regulator_bulk_data *vregs;
struct device **pd_devs;
@@ -89,6 +136,10 @@ struct qmp_pcie_match_data {
u32 num_modes;
};
+/* QSERDES_PCIE_V6_40_COM_BIAS_EN_CLKBUFLR_EN bits */
+#define COM_BIAS_EN BIT(0)
+#define COM_BIAS_EN_MUX BIT(1)
+
static const char * const glymur_pciephy_clk_l[] = {
"aux", "cfg_ahb", "ref", "rchng", "phy_b_aux",
};
@@ -232,6 +283,890 @@ static const struct qmp_pcie_match_data glymur_qmp_gen5x8_match_data = {
.num_modes = ARRAY_SIZE(glymur_qmp_gen5x8_mode_cfgs),
};
+static const char * const nord_pciephy_port_a_vreg_l[] = {
+ "vdda-phy-a", "vdda-pll-a",
+};
+
+static const char * const nord_pciephy_port_b_vreg_l[] = {
+ "vdda-phy-b", "vdda-pll-b",
+};
+
+static const char * const nord_pciephy_port_c_vreg_l[] = {
+ "vdda-phy-c", "vdda-pll-c",
+};
+
+static const char * const nord_pciephy_port_d_vreg_l[] = {
+ "vdda-phy-d", "vdda-pll-d",
+};
+
+static const char * const nord_pciephy_port_cd_vreg_l[] = {
+ "vdda-phy-c", "vdda-phy-d", "vdda-pll-c", "vdda-pll-d",
+};
+
+static const char * const nord_pciephy_port_bcd_vreg_l[] = {
+ "vdda-phy-b", "vdda-phy-c", "vdda-phy-d",
+ "vdda-pll-b", "vdda-pll-c", "vdda-pll-d",
+};
+
+static const char * const nord_pciephy_port_abcd_vreg_l[] = {
+ "vdda-phy-a", "vdda-phy-b", "vdda-phy-c", "vdda-phy-d",
+ "vdda-pll-a", "vdda-pll-b", "vdda-pll-c", "vdda-pll-d",
+};
+
+static const struct qmp_pcie_offsets nord_pcie_offsets_v6_40 = {
+ .pll = 0x8000,
+ .pcs = 0x9000,
+ .txrxz = 0xd000,
+ .pcs_lanez = 0xe800,
+};
+
+static struct qmp_phy_init_tbl nord_qmp_pcie_pll_a_tbl[] = {
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CLK_FWD_CONFIG_1, 0x0f),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_SSC_STEP_SIZE1_MODE2, 0xab),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_SSC_STEP_SIZE2_MODE2, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CP_CTRL_MODE2, 0x06),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_PLL_RCTRL_MODE2, 0x16),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_PLL_CCTRL_MODE2, 0x36),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CORECLK_DIV_MODE2, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_LOCK_CMP1_MODE2, 0x0a),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_LOCK_CMP2_MODE2, 0x1a),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DEC_START_MODE2, 0x68),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DIV_FRAC_START1_MODE2, 0xab),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DIV_FRAC_START2_MODE2, 0xaa),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DIV_FRAC_START3_MODE2, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_BIN_VCOCAL_CMP_CODE1_MODE2, 0xa4),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_BIN_VCOCAL_CMP_CODE2_MODE2, 0x18),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_SSC_STEP_SIZE1_MODE1, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_SSC_STEP_SIZE2_MODE1, 0x03),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CP_CTRL_MODE1, 0x06),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_PLL_RCTRL_MODE1, 0x16),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_PLL_CCTRL_MODE1, 0x36),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CORECLK_DIV_MODE1, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_LOCK_CMP1_MODE1, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_LOCK_CMP2_MODE1, 0x0d),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DEC_START_MODE1, 0x68),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DIV_FRAC_START1_MODE1, 0xab),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DIV_FRAC_START2_MODE1, 0xaa),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DIV_FRAC_START3_MODE1, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x52),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x0c),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_HSCLK_SEL_1, 0x3c),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_HSCLK_SEL_2, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_BIN_VCOCAL_HSCLK_SEL_1, 0x3c),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_BIN_VCOCAL_HSCLK_SEL_2, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_SSC_STEP_SIZE1_MODE0, 0xe0),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_SSC_STEP_SIZE2_MODE0, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CP_CTRL_MODE0, 0x06),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_PLL_RCTRL_MODE0, 0x16),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_PLL_CCTRL_MODE0, 0x36),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CORECLK_DIV_MODE0, 0x0a),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_LOCK_CMP1_MODE0, 0x40),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_LOCK_CMP2_MODE0, 0x03),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DEC_START_MODE0, 0x41),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DIV_FRAC_START1_MODE0, 0xab),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DIV_FRAC_START2_MODE0, 0xaa),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DIV_FRAC_START3_MODE0, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xd4),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x03),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_HSCLK_HS_SWITCH_SEL_1, 0x16),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_HSCLK_HS_SWITCH_SEL_2, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_BG_TIMER, 0x0a),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_VCO_TUNE_CTRL, 0x40),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_SSC_EN_CENTER, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_SSC_PER1, 0x62),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_SSC_PER2, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_POST_DIV_MUX, 0xc0),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_BIAS_EN_CLKBUFLR_EN, 0x1f),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CLK_ENABLE1, 0x90),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_SYS_CLK_CTRL, 0x82),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_PLL_IVCO, 0x1f),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_PLL_IVCO_MODE1, 0x1f),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_PLL_IVCO_MODE2, 0x1f),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_SYSCLK_EN_SEL, 0x08),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_LOCK_CMP_EN, 0x46),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_LOCK_CMP_CFG, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_VCO_TUNE_MAP, 0x24),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CLK_SELECT, 0x34),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CORE_CLK_EN, 0xe0),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CMN_CONFIG_1, 0x86),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CMN_MISC1, 0x88),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CMN_MODE, 0x14),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_VCO_DC_LEVEL_CTRL, 0x0f),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CMN_CONFIG_2, 0x10),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CLK_EP_DIV_MODE1, 0x14),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CLK_EP_DIV_MODE0, 0x32),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_PSM_CAL_EN, 0x05),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_PLL_SPARE_FOR_ECO, 0x40),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DCC_CAL_1, 0x40),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DCC_CAL_2, 0x07),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DCC_CAL_3, 0x60),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DCC_CAL_8, 0x32),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_IP_CTRL_AND_DP_SEL, 0xaf),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CMN_IETRIM, 0x0d),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DCC_CAL_7, 0x31),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DCC_CAL_9, 0x31),
+};
+
+static struct qmp_phy_init_tbl nord_qmp_pcie_pll_b_tbl[] = {
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CLK_FWD_CONFIG_1, 0x0f),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_SSC_STEP_SIZE1_MODE2, 0xab),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_SSC_STEP_SIZE2_MODE2, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CP_CTRL_MODE2, 0x06),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_PLL_RCTRL_MODE2, 0x16),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_PLL_CCTRL_MODE2, 0x36),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CORECLK_DIV_MODE2, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_LOCK_CMP1_MODE2, 0x0a),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_LOCK_CMP2_MODE2, 0x1a),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DEC_START_MODE2, 0x68),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DIV_FRAC_START1_MODE2, 0xab),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DIV_FRAC_START2_MODE2, 0xaa),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DIV_FRAC_START3_MODE2, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_BIN_VCOCAL_CMP_CODE1_MODE2, 0xa4),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_BIN_VCOCAL_CMP_CODE2_MODE2, 0x18),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_SSC_STEP_SIZE1_MODE1, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_SSC_STEP_SIZE2_MODE1, 0x03),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CP_CTRL_MODE1, 0x06),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_PLL_RCTRL_MODE1, 0x16),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_PLL_CCTRL_MODE1, 0x36),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CORECLK_DIV_MODE1, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_LOCK_CMP1_MODE1, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_LOCK_CMP2_MODE1, 0x0d),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DEC_START_MODE1, 0x68),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DIV_FRAC_START1_MODE1, 0xab),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DIV_FRAC_START2_MODE1, 0xaa),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DIV_FRAC_START3_MODE1, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x52),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x0c),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_HSCLK_SEL_1, 0x3c),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_HSCLK_SEL_2, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_BIN_VCOCAL_HSCLK_SEL_1, 0x3c),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_BIN_VCOCAL_HSCLK_SEL_2, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_SSC_STEP_SIZE1_MODE0, 0xe0),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_SSC_STEP_SIZE2_MODE0, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CP_CTRL_MODE0, 0x06),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_PLL_RCTRL_MODE0, 0x16),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_PLL_CCTRL_MODE0, 0x36),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CORECLK_DIV_MODE0, 0x0a),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_LOCK_CMP1_MODE0, 0x40),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_LOCK_CMP2_MODE0, 0x03),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DEC_START_MODE0, 0x41),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DIV_FRAC_START1_MODE0, 0xab),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DIV_FRAC_START2_MODE0, 0xaa),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DIV_FRAC_START3_MODE0, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xd4),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x03),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_HSCLK_HS_SWITCH_SEL_1, 0x16),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_HSCLK_HS_SWITCH_SEL_2, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_BG_TIMER, 0x0a),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_VCO_TUNE_CTRL, 0x40),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_SSC_EN_CENTER, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_SSC_PER1, 0x62),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_SSC_PER2, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_POST_DIV_MUX, 0xc0),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_BIAS_EN_CLKBUFLR_EN, 0x1f),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CLK_ENABLE1, 0x90),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_SYS_CLK_CTRL, 0x82),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_PLL_IVCO, 0x1f),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_PLL_IVCO_MODE1, 0x1f),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_PLL_IVCO_MODE2, 0x1f),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_SYSCLK_EN_SEL, 0x08),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_LOCK_CMP_EN, 0x46),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_LOCK_CMP_CFG, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_VCO_TUNE_MAP, 0x24),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CLK_SELECT, 0x34),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CORE_CLK_EN, 0xe0),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CMN_CONFIG_1, 0x86),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CMN_MISC1, 0x88),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CMN_MODE, 0x14),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_VCO_DC_LEVEL_CTRL, 0x0f),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CMN_CONFIG_2, 0x10),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CLK_EP_DIV_MODE1, 0x14),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CLK_EP_DIV_MODE0, 0x32),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_PSM_CAL_EN, 0x05),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_PLL_SPARE_FOR_ECO, 0x40),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DCC_CAL_1, 0x40),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DCC_CAL_2, 0x07),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DCC_CAL_3, 0x60),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DCC_CAL_8, 0x32),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_IP_CTRL_AND_DP_SEL, 0xaf),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CMN_IETRIM, 0x0d),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DCC_CAL_7, 0x32),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DCC_CAL_9, 0x22),
+};
+
+static struct qmp_phy_init_tbl nord_qmp_pcie_pll_c_tbl[] = {
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CLK_FWD_CONFIG_1, 0x0f),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_SSC_STEP_SIZE1_MODE2, 0xab),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_SSC_STEP_SIZE2_MODE2, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CP_CTRL_MODE2, 0x06),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_PLL_RCTRL_MODE2, 0x16),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_PLL_CCTRL_MODE2, 0x36),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CORECLK_DIV_MODE2, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_LOCK_CMP1_MODE2, 0x0a),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_LOCK_CMP2_MODE2, 0x1a),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DEC_START_MODE2, 0x68),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DIV_FRAC_START1_MODE2, 0xab),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DIV_FRAC_START2_MODE2, 0xaa),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DIV_FRAC_START3_MODE2, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_BIN_VCOCAL_CMP_CODE1_MODE2, 0xa4),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_BIN_VCOCAL_CMP_CODE2_MODE2, 0x18),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_SSC_STEP_SIZE1_MODE1, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_SSC_STEP_SIZE2_MODE1, 0x03),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CP_CTRL_MODE1, 0x06),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_PLL_RCTRL_MODE1, 0x16),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_PLL_CCTRL_MODE1, 0x36),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CORECLK_DIV_MODE1, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_LOCK_CMP1_MODE1, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_LOCK_CMP2_MODE1, 0x0d),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DEC_START_MODE1, 0x68),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DIV_FRAC_START1_MODE1, 0xab),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DIV_FRAC_START2_MODE1, 0xaa),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DIV_FRAC_START3_MODE1, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x52),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x0c),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_HSCLK_SEL_1, 0x3c),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_HSCLK_SEL_2, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_BIN_VCOCAL_HSCLK_SEL_1, 0x3c),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_BIN_VCOCAL_HSCLK_SEL_2, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_SSC_STEP_SIZE1_MODE0, 0xe0),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_SSC_STEP_SIZE2_MODE0, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CP_CTRL_MODE0, 0x06),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_PLL_RCTRL_MODE0, 0x16),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_PLL_CCTRL_MODE0, 0x36),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CORECLK_DIV_MODE0, 0x0a),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_LOCK_CMP1_MODE0, 0x40),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_LOCK_CMP2_MODE0, 0x03),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DEC_START_MODE0, 0x41),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DIV_FRAC_START1_MODE0, 0xab),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DIV_FRAC_START2_MODE0, 0xaa),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DIV_FRAC_START3_MODE0, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xd4),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x03),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_HSCLK_HS_SWITCH_SEL_1, 0x16),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_HSCLK_HS_SWITCH_SEL_2, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_BG_TIMER, 0x0a),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_VCO_TUNE_CTRL, 0x40),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_SSC_EN_CENTER, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_SSC_PER1, 0x62),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_SSC_PER2, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_POST_DIV_MUX, 0xc0),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_BIAS_EN_CLKBUFLR_EN, 0x1f),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CLK_ENABLE1, 0x90),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_SYS_CLK_CTRL, 0x82),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_PLL_IVCO, 0x1f),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_PLL_IVCO_MODE1, 0x1f),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_PLL_IVCO_MODE2, 0x1f),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_SYSCLK_EN_SEL, 0x08),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_LOCK_CMP_EN, 0x46),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_LOCK_CMP_CFG, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_VCO_TUNE_MAP, 0x24),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CLK_SELECT, 0x34),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CORE_CLK_EN, 0xe0),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CMN_CONFIG_1, 0x86),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CMN_MISC1, 0x88),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CMN_MODE, 0x14),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_VCO_DC_LEVEL_CTRL, 0x0f),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CMN_CONFIG_2, 0x10),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CLK_EP_DIV_MODE1, 0x14),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CLK_EP_DIV_MODE0, 0x32),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_PSM_CAL_EN, 0x05),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_PLL_SPARE_FOR_ECO, 0x40),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DCC_CAL_1, 0x40),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DCC_CAL_2, 0x07),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DCC_CAL_3, 0x60),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DCC_CAL_8, 0x32),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_IP_CTRL_AND_DP_SEL, 0xaf),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CMN_IETRIM, 0x0d),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DCC_CAL_7, 0x20),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DCC_CAL_9, 0x31),
+};
+
+static struct qmp_phy_init_tbl nord_qmp_pcie_pll_d_tbl[] = {
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CLK_FWD_CONFIG_1, 0x0f),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_SSC_STEP_SIZE1_MODE2, 0xab),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_SSC_STEP_SIZE2_MODE2, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CP_CTRL_MODE2, 0x06),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_PLL_RCTRL_MODE2, 0x16),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_PLL_CCTRL_MODE2, 0x36),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CORECLK_DIV_MODE2, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_LOCK_CMP1_MODE2, 0x0a),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_LOCK_CMP2_MODE2, 0x1a),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DEC_START_MODE2, 0x68),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DIV_FRAC_START1_MODE2, 0xab),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DIV_FRAC_START2_MODE2, 0xaa),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DIV_FRAC_START3_MODE2, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_BIN_VCOCAL_CMP_CODE1_MODE2, 0xa4),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_BIN_VCOCAL_CMP_CODE2_MODE2, 0x18),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_SSC_STEP_SIZE1_MODE1, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_SSC_STEP_SIZE2_MODE1, 0x03),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CP_CTRL_MODE1, 0x06),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_PLL_RCTRL_MODE1, 0x16),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_PLL_CCTRL_MODE1, 0x36),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CORECLK_DIV_MODE1, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_LOCK_CMP1_MODE1, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_LOCK_CMP2_MODE1, 0x0d),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DEC_START_MODE1, 0x68),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DIV_FRAC_START1_MODE1, 0xab),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DIV_FRAC_START2_MODE1, 0xaa),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DIV_FRAC_START3_MODE1, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x52),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x0c),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_HSCLK_SEL_1, 0x3c),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_HSCLK_SEL_2, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_BIN_VCOCAL_HSCLK_SEL_1, 0x3c),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_BIN_VCOCAL_HSCLK_SEL_2, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_SSC_STEP_SIZE1_MODE0, 0xe0),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_SSC_STEP_SIZE2_MODE0, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CP_CTRL_MODE0, 0x06),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_PLL_RCTRL_MODE0, 0x16),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_PLL_CCTRL_MODE0, 0x36),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CORECLK_DIV_MODE0, 0x0a),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_LOCK_CMP1_MODE0, 0x40),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_LOCK_CMP2_MODE0, 0x03),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DEC_START_MODE0, 0x41),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DIV_FRAC_START1_MODE0, 0xab),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DIV_FRAC_START2_MODE0, 0xaa),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DIV_FRAC_START3_MODE0, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xd4),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x03),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_HSCLK_HS_SWITCH_SEL_1, 0x16),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_HSCLK_HS_SWITCH_SEL_2, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_BG_TIMER, 0x0a),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_VCO_TUNE_CTRL, 0x40),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_SSC_EN_CENTER, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_SSC_PER1, 0x62),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_SSC_PER2, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_POST_DIV_MUX, 0xc0),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_BIAS_EN_CLKBUFLR_EN, 0x1f),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CLK_ENABLE1, 0x90),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_SYS_CLK_CTRL, 0x82),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_PLL_IVCO, 0x1f),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_PLL_IVCO_MODE1, 0x1f),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_PLL_IVCO_MODE2, 0x1f),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_SYSCLK_EN_SEL, 0x08),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_LOCK_CMP_EN, 0x46),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_LOCK_CMP_CFG, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_VCO_TUNE_MAP, 0x24),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CLK_SELECT, 0x34),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CORE_CLK_EN, 0xe0),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CMN_CONFIG_1, 0x86),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CMN_MISC1, 0x88),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CMN_MODE, 0x14),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_VCO_DC_LEVEL_CTRL, 0x0f),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CMN_CONFIG_2, 0x10),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CLK_EP_DIV_MODE1, 0x14),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CLK_EP_DIV_MODE0, 0x32),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_PSM_CAL_EN, 0x05),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_PLL_SPARE_FOR_ECO, 0x40),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DCC_CAL_1, 0x40),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DCC_CAL_2, 0x07),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DCC_CAL_3, 0x60),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DCC_CAL_8, 0x32),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_IP_CTRL_AND_DP_SEL, 0xaf),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_CMN_IETRIM, 0x0d),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DCC_CAL_7, 0x22),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_COM_DCC_CAL_9, 0x22),
+};
+
+static const struct qmp_phy_init_tbl nord_qmp_pcie_txrxz_tbl[] = {
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_SIGDET_ENABLES, 0x1c),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE2_B0, 0xcd),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE2_B1, 0x34),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE2_B2, 0x55),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE2_B3, 0x50),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE2_B4, 0xac),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE2_B5, 0xdb),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE2_B6, 0x52),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE2_B7, 0x3e),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE3_B0, 0xce),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE3_B1, 0x55),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE3_B2, 0x6d),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE3_B3, 0x60),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE3_B4, 0x8c),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE3_B5, 0x9d),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE3_B6, 0x6d),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE3_B7, 0x26),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE4_B0, 0xfb),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE4_B1, 0xea),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE4_B2, 0xe8),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE4_B3, 0x70),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE4_B4, 0x9c),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE4_B5, 0xf4),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE4_B6, 0x6d),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE4_B7, 0x3b),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_RX_SUMMER_CAL_SPD_MODE_RATE_0123, 0x6f),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_TX_ADAPT_POST_THRESH1, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_TX_ADAPT_POST_THRESH2, 0x0d),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_PHPRE_CTRL, 0x20),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_TX_ADPT_CTRL, 0x30),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE_0_1_B0, 0xff),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE_0_1_B1, 0x4a),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE_0_1_B2, 0x77),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE_0_1_B3, 0x50),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE_0_1_B4, 0x9a),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE_0_1_B5, 0x47),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE_0_1_B6, 0x52),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE_0_1_B7, 0x1d),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_LANE_MODE_1, 0x05),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_LANE_MODE_2, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_LANE_MODE_3, 0x41),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_LANE_MODE_4, 0x0f),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_PCIE_V6_40_TOP_LDO_CODE_CTRL1, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_PCIE_V6_40_TOP_LDO_CODE_CTRL2, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_PCIE_V6_40_TOP_LDO_CODE_CTRL3, 0x81),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_PCIE_V6_40_TOP_LDO_CODE_CTRL4, 0x8d),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_LOCK_CTRL, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_DFE_TAP1_DAC_ENABLE, 0x1c),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_DFE_TAP2_DAC_ENABLE, 0x1c),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_DFE_TAP345_DAC_ENABLE, 0x18),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_DFE_TAP67_DAC_ENABLE, 0x10),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_CP_CUR_FLL_RATE0, 0x07),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_CP_CUR_FLL_RATE1, 0x07),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_CP_CUR_FLL_RATE2, 0x0a),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_CP_CUR_FLL_RATE3, 0x0a),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_CP_CUR_FLL_RATE4, 0x0a),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_CP_CUR_PLL_RATE0, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_CP_CUR_PLL_RATE1, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_CP_CUR_PLL_RATE2, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_CP_CUR_PLL_RATE3, 0x03),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_CP_CUR_PLL_RATE4, 0x03),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_FLL_DIV_RATIO_RATE_0123, 0x94),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_LOOP_CCODE_RATE_01, 0x66),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_LOOP_CCODE_RATE_23, 0x77),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_LOOP_CCODE_RATE4, 0x07),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_IQTUNE_CTRL, 0x58),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_IQTUNE_MAN_INDEX, 0x0d),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_IQTUNE_ANA_CTRL, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_LOOP_FUNC_CTRL, 0xd0),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_KP_CAL_UPPER_FREQ_DIFF_BND1_RATE0, 0xff),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_KP_CAL_UPPER_FREQ_DIFF_BND1_RATE1, 0xff),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_KP_CAL_UPPER_FREQ_DIFF_BND1_RATE2, 0xff),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_KP_CAL_UPPER_FREQ_DIFF_BND1_RATE3, 0xff),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_KP_CAL_UPPER_FREQ_DIFF_BND1_RATE4, 0xff),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_KP_CAL_LOWER_FREQ_DIFF_BND_RATE0, 0x15),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_KP_CAL_LOWER_FREQ_DIFF_BND_RATE1, 0x15),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_KP_CAL_LOWER_FREQ_DIFF_BND_RATE2, 0x10),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_KP_CAL_LOWER_FREQ_DIFF_BND_RATE3, 0x07),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_KP_CAL_LOWER_FREQ_DIFF_BND_RATE4, 0x0c),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_KP_CODE_OVRD_RATE_2_3, 0x24),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_RX_IVCM_CAL_CTRL2, 0x83),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_RX_IVCM_CAL_CTRL3, 0x44),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_RX_IVCM_CAL_CTRL4, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_LOOP_RCODE_PLL_RATE_0_1, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_LOOP_RCODE_PLL_RATE_2_3, 0x11),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_LOOP_RCODE_PLL_RATE4, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_LOOP_RCODE_FLL_RATE_0_1, 0x33),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_LOOP_RCODE_FLL_RATE_2_3, 0x33),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_LOOP_RCODE_FLL_RATE4, 0x03),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_LOOP_RCODE_FAST_RATE_0_1, 0x22),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_LOOP_RCODE_FAST_RATE_2_3, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_LOOP_RCODE_FAST_RATE4, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_IQTUNE_DIV2_CTRL_RATE0123, 0x7f),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_VCO_CTUNE_MEAS_CNT1_RATE0, 0x13),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_VCO_CTUNE_MEAS_CNT2_RATE0, 0x13),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_VCO_CTUNE_MEAS_CNT1_RATE1, 0x26),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_VCO_CTUNE_MEAS_CNT2_RATE1, 0x26),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_VCO_CTUNE_MEAS_CNT1_RATE2, 0x9c),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_VCO_CTUNE_MEAS_CNT2_RATE2, 0x3d),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_VCO_CTUNE_MEAS_CNT1_RATE3, 0x9c),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_VCO_CTUNE_MEAS_CNT2_RATE3, 0x3d),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_VCO_CTUNE_MEAS_CNT1_RATE4, 0x09),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_VCO_CTUNE_MEAS_CNT2_RATE4, 0x3d),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_RX_EQU_ADAPTOR_CNTRL3, 0x0a),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_RX_EQU_ADAPTOR_CNTRL4, 0xaa),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_RX_EQU_ADAPTOR_CNTRL5, 0x0a),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_VGA_CAL_CNTRL1, 0xe1),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_VGA_CAL_MAN_VAL_RATE0_1, 0xdd),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_VGA_CAL_MAN_VAL_RATE2_3, 0xdc),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_VGA_CAL_MAN_VAL_RATE4, 0x05),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_VCO_CAP_CODE_OVRD_MUXES, 0x11),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_VCO_CAP_CODE_RATE_0123, 0x55),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_VCO_CAP_CODE_RATE4, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_KVCO_IDEAL_FREQ_DIFF1_RATE0, 0x4b),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_KVCO_IDEAL_FREQ_DIFF2_RATE0, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_KVCO_IDEAL_FREQ_DIFF1_RATE1, 0x4b),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_KVCO_IDEAL_FREQ_DIFF2_RATE1, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_KVCO_IDEAL_FREQ_DIFF1_RATE2, 0x35),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_KVCO_IDEAL_FREQ_DIFF2_RATE2, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_KVCO_IDEAL_FREQ_DIFF1_RATE3, 0x28),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_KVCO_IDEAL_FREQ_DIFF1_RATE4, 0x14),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_KVCO_INIT_RATE_0_1, 0x11),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_KVCO_INIT_RATE_2_3, 0x22),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_KVCO_INIT_RATE_4, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_KVCO_CODE_OVRD_RATE0, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_KVCO_CODE_OVRD_RATE1, 0x03),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_KVCO_CODE_OVRD_RATE2, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_FREQ_LOCK_DET_DLY_RATE0, 0xff),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_FREQ_LOCK_DET_DLY_RATE1, 0xff),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_FREQ_LOCK_DET_DLY_RATE2, 0xff),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_FREQ_LOCK_DET_DLY_RATE3, 0xff),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_FREQ_LOCK_DET_DLY_RATE4, 0xff),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_VCTRL_RATE_0_1, 0x43),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_VCTRL_RATE_2_3, 0x44),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_VCO_TYPE_CONFIG, 0x03),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CTLE_POST_CAL_OFFSET_RATE_0_1_2, 0x67),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CDR_VCO_EN_LOWFREQ, 0x1f),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_RES_CODE_LANE_OFFSET_RX, 0x18),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_GM_CAL_RES_RATE0_1, 0x88),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_GM_CAL_RES_RATE2_3, 0x88),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_GM_CAL_RES_RATE4, 0x09),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_VTHRESH_CAL_MAN_VAL_RATE4, 0x56),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_CLKBUF_ENABLE, 0x40),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_VCO_CTUNE_UPPER_BND_RATE0, 0x1e),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_VCO_CTUNE_UPPER_BND_RATE1, 0x1e),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_VCO_CTUNE_UPPER_BND_RATE2, 0x1e),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_VCO_CTUNE_UPPER_BND_RATE3, 0x1e),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_VCO_CTUNE_UPPER_BND_RATE4, 0x1e),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_SIGDET_CNTRL, 0x2f),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_SIGDET_LVL, 0x84),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_SIGDET_CAL_CTRL1, 0x10),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_DIG_BKUP_CTRL15, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_DIG_BKUP_CTRL16, 0x52),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_RESTRIM_CAL_CTRL, 0x08),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_RESTRIM_POST_CAL_OFFSET, 0x10),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_RESTRIM_VREF_SEL, 0x16),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_BLW_CTRL, 0x3c),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_BLW_MAN_VAL_RATE3, 0x17),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_BLW_MAN_VAL_RATE4, 0x17),
+};
+
+static const struct qmp_phy_init_tbl nord_qmp_pcie_pcs_tbl[] = {
+ QMP_PHY_INIT_CFG(QPHY_PCIE_V6_40_PCS_COM_POWER_STATE_CONFIG2, 0x3d),
+ QMP_PHY_INIT_CFG(QPHY_PCIE_V6_40_PCS_COM_POWER_STATE_CONFIG5, 0xe4),
+ QMP_PHY_INIT_CFG(QPHY_PCIE_V6_40_PCS_COM_POWER_STATE_CONFIG6, 0x1f),
+ QMP_PHY_INIT_CFG(QPHY_PCIE_V6_40_PCS_COM_POWER_STATE_CONFIG7, 0x0d),
+ QMP_PHY_INIT_CFG(QPHY_PCIE_V6_40_PCS_COM_MULTIPHY_CONFIG2, 0x01),
+ QMP_PHY_INIT_CFG(QPHY_PCIE_V6_40_PCS_COM_PCS_TX_RX_CONFIG2, 0xe4),
+ QMP_PHY_INIT_CFG(QPHY_PCIE_V6_40_PCS_COM_PCS_TX_RX_CONFIG3, 0x30),
+ QMP_PHY_INIT_CFG(QPHY_PCIE_V6_40_PCS_COM_PCS_TX_RX_CONFIG5, 0x05),
+ QMP_PHY_INIT_CFG(QPHY_PCIE_V6_40_PCS_COM_PCS_TX_RX_CONFIG6, 0x08),
+ QMP_PHY_INIT_CFG(QPHY_PCIE_V6_40_PCS_COM_PCS_TX_RX_CONFIG7, 0x20),
+ QMP_PHY_INIT_CFG(QPHY_PCIE_V6_40_PCS_COM_PCS_TX_RX_CONFIG8, 0x20),
+ QMP_PHY_INIT_CFG(QPHY_PCIE_V6_40_PCS_COM_PCS_TX_RX_CONFIG10, 0x40),
+ QMP_PHY_INIT_CFG(QPHY_PCIE_V6_40_PCS_COM_DIVTX_CLK_DCC_CAL_CONFIG2, 0x00),
+ QMP_PHY_INIT_CFG(QPHY_PCIE_V6_40_PCS_COM_DIVTX_CLK_DCC_CAL_CONFIG3, 0x00),
+ QMP_PHY_INIT_CFG(QPHY_PCIE_V6_40_PCS_COM_DIVTX_CLK_DCC_CAL_CONFIG4, 0x00),
+ QMP_PHY_INIT_CFG(QPHY_PCIE_V6_40_PCS_COM_ENDPOINT_REFCLK_DRIVE, 0xc1),
+ QMP_PHY_INIT_CFG(QPHY_PCIE_V6_40_PCS_COM_RX_SIGDET_LVL, 0x66),
+ QMP_PHY_INIT_CFG(QPHY_PCIE_V6_40_PCS_COM_OSC_DTCT_ACTIONS, 0x00),
+ QMP_PHY_INIT_CFG(QPHY_PCIE_V6_40_PCS_COM_LOCK_DETECT_CONFIG1, 0xff),
+ QMP_PHY_INIT_CFG(QPHY_PCIE_V6_40_PCS_COM_ALIGN_DETECT_CONFIG1, 0x00),
+ QMP_PHY_INIT_CFG(QPHY_PCIE_V6_40_PCS_COM_ALIGN_DETECT_CONFIG2, 0x04),
+ QMP_PHY_INIT_CFG(QPHY_PCIE_V6_40_PCS_COM_ALIGN_DETECT_CONFIG3, 0x1f),
+ QMP_PHY_INIT_CFG(QPHY_PCIE_V6_40_PCS_COM_ALIGN_DETECT_CONFIG7, 0x35),
+ QMP_PHY_INIT_CFG(QPHY_PCIE_V6_40_PCS_COM_ALIGN_DETECT_CONFIG8, 0x3e),
+ QMP_PHY_INIT_CFG(QPHY_PCIE_V6_40_PCS_COM_EQ_CONFIG1, 0x06),
+ QMP_PHY_INIT_CFG(QPHY_PCIE_V6_40_PCS_COM_EQ_CONFIG2, 0x1c),
+ QMP_PHY_INIT_CFG(QPHY_PCIE_V6_40_PCS_COM_G345_EQ_CONFIG1, 0x03),
+ QMP_PHY_INIT_CFG(QPHY_PCIE_V6_40_PCS_COM_G345_EQ_CONFIG3, 0x00),
+ QMP_PHY_INIT_CFG(QPHY_PCIE_V6_40_PCS_COM_G3_EQ_CONFIG1, 0x00),
+ QMP_PHY_INIT_CFG(QPHY_PCIE_V6_40_PCS_COM_G3_EQ_CONFIG5, 0x90),
+ QMP_PHY_INIT_CFG(QPHY_PCIE_V6_40_PCS_COM_G3_EQ_CONFIG7, 0x0d),
+ QMP_PHY_INIT_CFG(QPHY_PCIE_V6_40_PCS_COM_G4_EQ_CONFIG1, 0x00),
+ QMP_PHY_INIT_CFG(QPHY_PCIE_V6_40_PCS_COM_G4_EQ_CONFIG5, 0x90),
+ QMP_PHY_INIT_CFG(QPHY_PCIE_V6_40_PCS_COM_G4_EQ_CONFIG7, 0x0d),
+ QMP_PHY_INIT_CFG(QPHY_PCIE_V6_40_PCS_COM_G5_EQ_CONFIG1, 0x00),
+ QMP_PHY_INIT_CFG(QPHY_PCIE_V6_40_PCS_COM_G5_EQ_CONFIG5, 0x90),
+ QMP_PHY_INIT_CFG(QPHY_PCIE_V6_40_PCS_COM_G5_EQ_CONFIG7, 0x0d),
+ QMP_PHY_INIT_CFG(QPHY_PCIE_V6_40_PCS_COM_TEST_CONTROL1, 0x08),
+};
+
+static const struct qmp_phy_init_tbl nord_qmp_pcie_pcs_lanez_tbl[] = {
+ QMP_PHY_INIT_CFG(QPHY_PCIE_V6_40_PCS_LANEZ_OUTSIG_MX_CTRL2, 0x00),
+ QMP_PHY_INIT_CFG(QPHY_PCIE_V6_40_PCS_LANEZ_OUTSIG_MX_CTRL5, 0x00),
+};
+
+static const struct qmp_phy_cfg_tbls nord_qmp_pcie_tbls = {
+ .txrxz = nord_qmp_pcie_txrxz_tbl,
+ .txrxz_num = ARRAY_SIZE(nord_qmp_pcie_txrxz_tbl),
+ .pcs = nord_qmp_pcie_pcs_tbl,
+ .pcs_num = ARRAY_SIZE(nord_qmp_pcie_pcs_tbl),
+ .pcs_lanez = nord_qmp_pcie_pcs_lanez_tbl,
+ .pcs_lanez_num = ARRAY_SIZE(nord_qmp_pcie_pcs_lanez_tbl),
+};
+
+static const struct qmp_phy_init_tbl nord_qmp_pcie_bifurcated_pre_pwrup_tbl[] = {
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_PRE_STALL_LDO_BOOST_EN, 0x80),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_LDO_TIMER_CTRL, 0x91),
+};
+
+static const struct qmp_phy_init_tbl nord_qmp_pcie_bifurcated_post_cfg_tbl[] = {
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_LDO_TIMER_CTRL, 0x11),
+ QMP_PHY_INIT_CFG(QSERDES_PCIE_V6_40_TXRXZ_PRE_STALL_LDO_BOOST_EN, 0x00),
+};
+
+static struct qmp_phy_init_tbl *nord_qmp_pcie_pll_a[] = {
+ nord_qmp_pcie_pll_a_tbl,
+};
+
+static int nord_qmp_pcie_pll_a_nums[] = {
+ ARRAY_SIZE(nord_qmp_pcie_pll_a_tbl),
+};
+
+static struct qmp_phy_init_tbl *nord_qmp_pcie_pll_b[] = {
+ nord_qmp_pcie_pll_b_tbl,
+};
+
+static int nord_qmp_pcie_pll_b_nums[] = {
+ ARRAY_SIZE(nord_qmp_pcie_pll_b_tbl),
+};
+
+static struct qmp_phy_init_tbl *nord_qmp_pcie_pll_c[] = {
+ nord_qmp_pcie_pll_c_tbl,
+};
+
+static int nord_qmp_pcie_pll_c_nums[] = {
+ ARRAY_SIZE(nord_qmp_pcie_pll_c_tbl),
+};
+
+static struct qmp_phy_init_tbl *nord_qmp_pcie_pll_d[] = {
+ nord_qmp_pcie_pll_d_tbl,
+};
+
+static int nord_qmp_pcie_pll_d_nums[] = {
+ ARRAY_SIZE(nord_qmp_pcie_pll_d_tbl),
+};
+
+static struct qmp_phy_init_tbl *nord_qmp_pcie_pll_cd[] = {
+ nord_qmp_pcie_pll_c_tbl, nord_qmp_pcie_pll_d_tbl,
+};
+
+static int nord_qmp_pcie_pll_cd_nums[] = {
+ ARRAY_SIZE(nord_qmp_pcie_pll_c_tbl), ARRAY_SIZE(nord_qmp_pcie_pll_d_tbl),
+};
+
+static struct qmp_phy_init_tbl *nord_qmp_pcie_pll_bcd[] = {
+ nord_qmp_pcie_pll_b_tbl, nord_qmp_pcie_pll_c_tbl, nord_qmp_pcie_pll_d_tbl,
+};
+
+static int nord_qmp_pcie_pll_bcd_nums[] = {
+ ARRAY_SIZE(nord_qmp_pcie_pll_b_tbl), ARRAY_SIZE(nord_qmp_pcie_pll_c_tbl),
+ ARRAY_SIZE(nord_qmp_pcie_pll_d_tbl),
+};
+
+static struct qmp_phy_init_tbl *nord_qmp_pcie_pll_abcd[] = {
+ nord_qmp_pcie_pll_a_tbl, nord_qmp_pcie_pll_b_tbl,
+ nord_qmp_pcie_pll_c_tbl, nord_qmp_pcie_pll_d_tbl,
+};
+
+static int nord_qmp_pcie_pll_abcd_nums[] = {
+ ARRAY_SIZE(nord_qmp_pcie_pll_a_tbl), ARRAY_SIZE(nord_qmp_pcie_pll_b_tbl),
+ ARRAY_SIZE(nord_qmp_pcie_pll_c_tbl), ARRAY_SIZE(nord_qmp_pcie_pll_d_tbl),
+};
+
+static const char * const nord_pciephy_port_a_reg_l[] = { "port_a" };
+static const char * const nord_pciephy_port_b_reg_l[] = { "port_b" };
+static const char * const nord_pciephy_port_c_reg_l[] = { "port_c" };
+static const char * const nord_pciephy_port_d_reg_l[] = { "port_d" };
+static const char * const nord_pciephy_port_cd_reg_l[] = { "port_c", "port_d" };
+static const char * const nord_pciephy_port_bcd_reg_l[] = { "port_b", "port_c", "port_d" };
+static const char * const nord_pciephy_port_abcd_reg_l[] = {
+ "port_a", "port_b", "port_c", "port_d"
+};
+
+static const char * const nord_pciephy_port_a_clk_l[] = { "aux_a", "cfg_ahb_a", "rchng_a", "ref" };
+static const char * const nord_pciephy_port_b_clk_l[] = {
+ "aux_a", "aux_b", "cfg_ahb_b", "rchng_b", "ref",
+};
+
+static const char * const nord_pciephy_port_c_clk_l[] = {
+ "aux_a", "aux_c", "cfg_ahb_c", "rchng_c", "ref",
+};
+
+static const char * const nord_pciephy_port_d_clk_l[] = {
+ "aux_a", "aux_d", "cfg_ahb_d", "rchng_d", "ref",
+};
+
+static const char * const nord_pciephy_port_cd_clk_l[] = {
+ "aux_a", "aux_c", "cfg_ahb_c", "rchng_c", "aux_d", "cfg_ahb_d", "rchng_d", "ref",
+};
+
+static const char * const nord_pciephy_port_bcd_clk_l[] = {
+ "aux_a", "aux_b", "cfg_ahb_b", "rchng_b",
+ "aux_c", "cfg_ahb_c", "rchng_c",
+ "aux_d", "cfg_ahb_d", "rchng_d", "ref",
+};
+
+static const char * const nord_pciephy_port_abcd_clk_l[] = {
+ "aux_a", "cfg_ahb_a", "rchng_a",
+ "aux_b", "cfg_ahb_b", "rchng_b",
+ "aux_c", "cfg_ahb_c", "rchng_c",
+ "aux_d", "cfg_ahb_d", "rchng_d", "ref",
+};
+
+static const char * const nord_pciephy_port_a_pipeclk_l[] = { "pipe_a" };
+static const char * const nord_pciephy_port_b_pipeclk_l[] = { "pipe_b" };
+static const char * const nord_pciephy_port_c_pipeclk_l[] = { "pipe_c" };
+static const char * const nord_pciephy_port_d_pipeclk_l[] = { "pipe_d" };
+
+static const char * const nord_pciephy_port_a_reset_l[] = { "port_a" };
+static const char * const nord_pciephy_port_b_reset_l[] = { "port_b" };
+static const char * const nord_pciephy_port_c_reset_l[] = { "port_c" };
+static const char * const nord_pciephy_port_d_reset_l[] = { "port_d" };
+static const char * const nord_pciephy_port_cd_reset_l[] = {
+ "port_c", "port_d",
+};
+
+static const char * const nord_pciephy_port_bcd_reset_l[] = {
+ "port_b", "port_c", "port_d",
+};
+
+static const char * const nord_pciephy_port_abcd_reset_l[] = {
+ "port_a", "port_b", "port_c", "port_d",
+};
+
+static const char * const nord_pciephy_port_a_nocsr_reset_l[] = { "port_a_nocsr" };
+static const char * const nord_pciephy_port_b_nocsr_reset_l[] = { "port_b_nocsr" };
+static const char * const nord_pciephy_port_c_nocsr_reset_l[] = { "port_c_nocsr" };
+static const char * const nord_pciephy_port_d_nocsr_reset_l[] = { "port_d_nocsr" };
+static const char * const nord_pciephy_port_cd_nocsr_reset_l[] = { "port_c_nocsr", "port_d_nocsr" };
+static const char * const nord_pciephy_port_bcd_nocsr_reset_l[] = {
+ "port_b_nocsr", "port_c_nocsr", "port_d_nocsr",
+};
+
+static const char * const nord_pciephy_port_abcd_nocsr_reset_l[] = {
+ "port_a_nocsr", "port_b_nocsr", "port_c_nocsr", "port_d_nocsr",
+};
+
+static const char * const nord_pciephy_port_a_pd_l[] = { "port_a" };
+static const char * const nord_pciephy_port_b_pd_l[] = { "port_a", "port_b" };
+static const char * const nord_pciephy_port_c_pd_l[] = { "port_a", "port_c" };
+static const char * const nord_pciephy_port_d_pd_l[] = { "port_a", "port_d" };
+static const char * const nord_pciephy_port_cd_pd_l[] = {
+ "port_a", "port_c", "port_d",
+};
+
+static const char * const nord_pciephy_port_bcd_pd_l[] = {
+ "port_a", "port_b", "port_c", "port_d",
+};
+
+#define nord_pciephy_port_abcd_pd_l nord_pciephy_port_bcd_pd_l
+
+#define NORD_QMP_PCIE_PORT_CFG(_port, _pipeclk_l, _bifurcated) \
+static const struct qmp_phy_cfg nord_qmp_pcie_port_##_port##_cfg = { \
+ .offsets = &nord_pcie_offsets_v6_40, \
+ .tbls = nord_qmp_pcie_tbls, \
+ .pll_tbls = nord_qmp_pcie_pll_##_port, \
+ .pll_nums = nord_qmp_pcie_pll_##_port##_nums, \
+ .bifurcated = _bifurcated, \
+ .reg_names = nord_pciephy_port_##_port##_reg_l, \
+ .num_regs = ARRAY_SIZE(nord_pciephy_port_##_port##_reg_l), \
+ .pd_names = nord_pciephy_port_##_port##_pd_l, \
+ .num_pds = ARRAY_SIZE(nord_pciephy_port_##_port##_pd_l), \
+ .reset_list = nord_pciephy_port_##_port##_reset_l, \
+ .num_resets = ARRAY_SIZE(nord_pciephy_port_##_port##_reset_l), \
+ .nocsr_reset_list = nord_pciephy_port_##_port##_nocsr_reset_l, \
+ .num_nocsr_resets = ARRAY_SIZE(nord_pciephy_port_##_port##_nocsr_reset_l), \
+ .vreg_list = nord_pciephy_port_##_port##_vreg_l, \
+ .num_vregs = ARRAY_SIZE(nord_pciephy_port_##_port##_vreg_l), \
+ .regs = nord_pciephy_v6_40_regs_layout, \
+ .phy_status = PHYSTATUS_4_20, \
+ .clk_list = nord_pciephy_port_##_port##_clk_l, \
+ .num_clks = ARRAY_SIZE(nord_pciephy_port_##_port##_clk_l), \
+ .pipe_clk_list = _pipeclk_l, \
+ .num_pipe_clks = 1, \
+}
+
+NORD_QMP_PCIE_PORT_CFG(a, nord_pciephy_port_a_pipeclk_l, true);
+NORD_QMP_PCIE_PORT_CFG(b, nord_pciephy_port_b_pipeclk_l, true);
+NORD_QMP_PCIE_PORT_CFG(c, nord_pciephy_port_c_pipeclk_l, true);
+NORD_QMP_PCIE_PORT_CFG(d, nord_pciephy_port_d_pipeclk_l, true);
+NORD_QMP_PCIE_PORT_CFG(cd, nord_pciephy_port_c_pipeclk_l, true);
+NORD_QMP_PCIE_PORT_CFG(bcd, nord_pciephy_port_b_pipeclk_l, true);
+NORD_QMP_PCIE_PORT_CFG(abcd, nord_pciephy_port_a_pipeclk_l, false);
+
+#undef NORD_QMP_PCIE_PORT_CFG
+
+static const struct qmp_phy_cfg * const nord_qmp_gen5x16_mode_x16_cfgs[] = {
+ &nord_qmp_pcie_port_abcd_cfg,
+};
+
+static const struct qmp_phy_cfg * const nord_qmp_gen5x16_mode_x8x8_cfgs[] = {
+ &nord_qmp_pcie_port_a_cfg,
+ &nord_qmp_pcie_port_bcd_cfg,
+};
+
+static const struct qmp_phy_cfg * const nord_qmp_gen5x16_mode_x8x4x4_cfgs[] = {
+ &nord_qmp_pcie_port_a_cfg,
+ &nord_qmp_pcie_port_b_cfg,
+ &nord_qmp_pcie_port_cd_cfg,
+};
+
+static const struct qmp_phy_cfg * const nord_qmp_gen5x16_mode_x8x4x2x2_cfgs[] = {
+ &nord_qmp_pcie_port_a_cfg,
+ &nord_qmp_pcie_port_b_cfg,
+ &nord_qmp_pcie_port_c_cfg,
+ &nord_qmp_pcie_port_d_cfg,
+};
+
+static const struct qmp_pcie_link_mode_cfg nord_qmp_gen5x16_mode_cfgs[] = {
+ [QMP_PCIE_NORD_MODE_X16] = {
+ .cfgs = nord_qmp_gen5x16_mode_x16_cfgs,
+ .num_phys = ARRAY_SIZE(nord_qmp_gen5x16_mode_x16_cfgs),
+ },
+ [QMP_PCIE_NORD_MODE_X8_X8] = {
+ .cfgs = nord_qmp_gen5x16_mode_x8x8_cfgs,
+ .num_phys = ARRAY_SIZE(nord_qmp_gen5x16_mode_x8x8_cfgs),
+ },
+ [QMP_PCIE_NORD_MODE_X8_X4_X4] = {
+ .cfgs = nord_qmp_gen5x16_mode_x8x4x4_cfgs,
+ .num_phys = ARRAY_SIZE(nord_qmp_gen5x16_mode_x8x4x4_cfgs),
+ },
+ [QMP_PCIE_NORD_MODE_X8_X4_X2_X2] = {
+ .cfgs = nord_qmp_gen5x16_mode_x8x4x2x2_cfgs,
+ .num_phys = ARRAY_SIZE(nord_qmp_gen5x16_mode_x8x4x2x2_cfgs),
+ },
+};
+
+static const struct qmp_pcie_match_data nord_qmp_gen5x16_match_data = {
+ .mode_cfgs = nord_qmp_gen5x16_mode_cfgs,
+ .num_modes = ARRAY_SIZE(nord_qmp_gen5x16_mode_cfgs),
+};
+
+static void qmp_pcie_init_port_registers(struct qmp_pcie *qmp)
+{
+ const struct qmp_phy_cfg *cfg = qmp->cfg;
+ const struct qmp_pcie_offsets *offs = cfg->offsets;
+ const struct qmp_phy_cfg_tbls *tbls = &cfg->tbls;
+ int i;
+
+ for (i = 0; i < cfg->num_regs; i++) {
+ void __iomem *port = qmp->base[i];
+ u32 val;
+
+ if (cfg->bifurcated)
+ qmp_configure(qmp->dev, port + offs->txrxz,
+ nord_qmp_pcie_bifurcated_pre_pwrup_tbl,
+ ARRAY_SIZE(nord_qmp_pcie_bifurcated_pre_pwrup_tbl));
+
+ writel(SW_PWRDN | REFCLK_DRV_DSBL,
+ port + offs->pcs + cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]);
+
+ if (cfg->bifurcated) {
+ void __iomem *bias_en = port + offs->pll +
+ cfg->regs[QPHY_COM_BIAS_EN_CLKBUFLR_EN];
+
+ val = readl(bias_en);
+ val |= COM_BIAS_EN_MUX | COM_BIAS_EN;
+ writel(val, bias_en);
+ }
+
+ qmp_configure(qmp->dev, port + offs->pll,
+ cfg->pll_tbls[i], cfg->pll_nums[i]);
+ qmp_configure(qmp->dev, port + offs->txrxz,
+ tbls->txrxz, tbls->txrxz_num);
+ qmp_configure(qmp->dev, port + offs->pcs,
+ tbls->pcs, tbls->pcs_num);
+ qmp_configure(qmp->dev, port + offs->pcs_lanez,
+ tbls->pcs_lanez, tbls->pcs_lanez_num);
+
+ if (cfg->bifurcated)
+ qmp_configure(qmp->dev, port + offs->txrxz,
+ nord_qmp_pcie_bifurcated_post_cfg_tbl,
+ ARRAY_SIZE(nord_qmp_pcie_bifurcated_post_cfg_tbl));
+ }
+}
+
static int qmp_pcie_pd_power_on(struct qmp_pcie *qmp)
{
const struct qmp_phy_cfg *cfg = qmp->cfg;
@@ -280,20 +1215,37 @@ static int qmp_pcie_init(struct phy *phy)
goto err_pd_power_off;
}
+ ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets);
+ if (ret) {
+ dev_err(qmp->dev, "reset assert failed: %d\n", ret);
+ goto err_disable_regulators;
+ }
+
ret = reset_control_bulk_assert(qmp->cfg->num_nocsr_resets, qmp->nocsr_resets);
if (ret) {
dev_err(qmp->dev, "no-csr reset assert failed: %d\n", ret);
- goto err_disable_regulators;
+ goto err_assert_reset;
}
usleep_range(200, 300);
+ ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets);
+ if (ret) {
+ dev_err(qmp->dev, "reset deassert failed: %d\n", ret);
+ goto err_assert_reset;
+ }
+
ret = clk_bulk_prepare_enable(qmp->cfg->num_clks, qmp->clks);
if (ret)
- goto err_disable_regulators;
+ goto err_assert_reset;
+
+ if (cfg->pll_tbls)
+ qmp_pcie_init_port_registers(qmp);
return 0;
+err_assert_reset:
+ reset_control_bulk_assert(cfg->num_resets, qmp->resets);
err_disable_regulators:
regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
err_pd_power_off:
@@ -306,8 +1258,19 @@ static int qmp_pcie_exit(struct phy *phy)
{
struct qmp_pcie *qmp = phy_get_drvdata(phy);
const struct qmp_phy_cfg *cfg = qmp->cfg;
+ const struct qmp_pcie_offsets *offs = cfg->offsets;
+ int i;
- reset_control_bulk_assert(qmp->cfg->num_nocsr_resets, qmp->nocsr_resets);
+ if (cfg->pll_tbls) {
+ for (i = 0; i < cfg->num_regs; i++)
+ writel(0x00, qmp->base[i] + offs->pcs +
+ cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]);
+ }
+
+ if (qmp->nocsr_resets)
+ reset_control_bulk_assert(qmp->cfg->num_nocsr_resets, qmp->nocsr_resets);
+ if (qmp->resets)
+ reset_control_bulk_assert(cfg->num_resets, qmp->resets);
clk_bulk_disable_unprepare(qmp->cfg->num_clks, qmp->clks);
regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
@@ -335,6 +1298,15 @@ static int qmp_pcie_power_on(struct phy *phy)
goto err_disable_pipe_clk;
}
+ if (cfg->pll_tbls) {
+ for (i = 0; i < cfg->num_regs; i++) {
+ writel(0x00, qmp->base[i] + offs->pcs + cfg->regs[QPHY_PCS_SW_RESET]);
+ writel(0x03, qmp->base[i] + offs->pcs + cfg->regs[QPHY_PCS_START_CONTROL]);
+ }
+
+ usleep_range(2000, 2500);
+ }
+
for (i = 0; i < cfg->num_regs; i++) {
status = qmp->base[i] + offs->pcs + cfg->regs[QPHY_PCS_STATUS];
ret = readl_poll_timeout(status, val, !(val & cfg->phy_status), 200,
@@ -357,6 +1329,14 @@ static int qmp_pcie_power_on(struct phy *phy)
static int qmp_pcie_power_off(struct phy *phy)
{
struct qmp_pcie *qmp = phy_get_drvdata(phy);
+ const struct qmp_phy_cfg *cfg = qmp->cfg;
+ const struct qmp_pcie_offsets *offs = cfg->offsets;
+ int i;
+
+ if (cfg->pll_tbls) {
+ for (i = 0; i < cfg->num_regs; i++)
+ writel(0x01, qmp->base[i] + offs->pcs + cfg->regs[QPHY_PCS_SW_RESET]);
+ }
clk_bulk_disable_unprepare(qmp->cfg->num_pipe_clks, qmp->pipe_clks);
@@ -398,45 +1378,39 @@ static const struct phy_ops qmp_pcie_phy_ops = {
static void qmp_pcie_pd_detach(void *data)
{
struct qmp_pcie *qmp = data;
- const struct qmp_phy_cfg *cfg = qmp->cfg;
int i;
- for (i = 0; i < cfg->num_pds; i++) {
+ for (i = 0; i < qmp->cfg->num_pds; i++) {
if (!IS_ERR_OR_NULL(qmp->pd_devs[i]))
dev_pm_domain_detach(qmp->pd_devs[i], true);
}
}
-static int qmp_pcie_pd_init(struct qmp_pcie *qmp)
+static int qmp_pcie_pd_init(struct qmp_pcie *qmp, struct phy *phy)
{
const struct qmp_phy_cfg *cfg = qmp->cfg;
- struct device *dev = qmp->dev;
+ struct device *pd_dev = &phy->dev;
int i, ret;
if (!cfg->num_pds)
return 0;
- qmp->pd_devs = devm_kcalloc(dev, cfg->num_pds, sizeof(*qmp->pd_devs),
+ qmp->pd_devs = devm_kcalloc(pd_dev, cfg->num_pds, sizeof(*qmp->pd_devs),
GFP_KERNEL);
if (!qmp->pd_devs)
return -ENOMEM;
+ ret = devm_add_action_or_reset(pd_dev, qmp_pcie_pd_detach, qmp);
+ if (ret)
+ return ret;
+
for (i = 0; i < cfg->num_pds; i++) {
- qmp->pd_devs[i] = dev_pm_domain_attach_by_name(dev,
- cfg->pd_names[i]);
- if (IS_ERR_OR_NULL(qmp->pd_devs[i])) {
- ret = PTR_ERR(qmp->pd_devs[i]) ? : -ENODATA;
- goto err_detach;
- }
+ qmp->pd_devs[i] = dev_pm_domain_attach_by_name(pd_dev, cfg->pd_names[i]);
+ if (IS_ERR_OR_NULL(qmp->pd_devs[i]))
+ return PTR_ERR_OR_ZERO(qmp->pd_devs[i]) ? : -ENODATA;
}
- return devm_add_action_or_reset(dev, qmp_pcie_pd_detach, qmp);
-
-err_detach:
- while (--i >= 0)
- dev_pm_domain_detach(qmp->pd_devs[i], false);
-
- return ret;
+ return 0;
}
static int qmp_pcie_vreg_init(struct qmp_pcie *qmp)
@@ -462,20 +1436,37 @@ static int qmp_pcie_reset_init(struct qmp_pcie *qmp)
struct device *dev = qmp->dev;
int i, ret;
- qmp->nocsr_resets = devm_kcalloc(dev, cfg->num_nocsr_resets,
- sizeof(*qmp->nocsr_resets),
- GFP_KERNEL);
- if (!qmp->nocsr_resets)
- return -ENOMEM;
+ if (cfg->num_resets) {
+ qmp->resets = devm_kcalloc(dev, cfg->num_resets,
+ sizeof(*qmp->resets), GFP_KERNEL);
+ if (!qmp->resets)
+ return -ENOMEM;
- for (i = 0; i < cfg->num_nocsr_resets; i++)
- qmp->nocsr_resets[i].id = cfg->nocsr_reset_list[i];
+ for (i = 0; i < cfg->num_resets; i++)
+ qmp->resets[i].id = cfg->reset_list[i];
- ret = devm_reset_control_bulk_get_exclusive(dev,
- cfg->num_nocsr_resets,
- qmp->nocsr_resets);
- if (ret)
- return dev_err_probe(dev, ret, "failed to get no-csr resets\n");
+ ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets,
+ qmp->resets);
+ if (ret)
+ return dev_err_probe(dev, ret, "failed to get resets\n");
+ }
+
+ if (cfg->num_nocsr_resets) {
+ qmp->nocsr_resets = devm_kcalloc(dev, cfg->num_nocsr_resets,
+ sizeof(*qmp->nocsr_resets),
+ GFP_KERNEL);
+ if (!qmp->nocsr_resets)
+ return -ENOMEM;
+
+ for (i = 0; i < cfg->num_nocsr_resets; i++)
+ qmp->nocsr_resets[i].id = cfg->nocsr_reset_list[i];
+
+ ret = devm_reset_control_bulk_get_exclusive(dev,
+ cfg->num_nocsr_resets,
+ qmp->nocsr_resets);
+ if (ret)
+ return dev_err_probe(dev, ret, "failed to get no-csr resets\n");
+ }
return 0;
}
@@ -630,6 +1621,7 @@ static struct phy *qmp_pcie_multiphy_xlate(struct device *dev,
static int qmp_pcie_probe_phy(struct qmp_pcie *qmp, struct device_node *np,
struct phy **out_phy)
{
+ struct phy *phy;
int ret;
ret = qmp_pcie_get_mmio(qmp);
@@ -648,15 +1640,16 @@ static int qmp_pcie_probe_phy(struct qmp_pcie *qmp, struct device_node *np,
if (ret)
return ret;
- ret = qmp_pcie_pd_init(qmp);
+ phy = devm_phy_create(qmp->dev, np, &qmp_pcie_phy_ops);
+ if (IS_ERR(phy))
+ return PTR_ERR(phy);
+
+ ret = qmp_pcie_pd_init(qmp, phy);
if (ret)
return ret;
- *out_phy = devm_phy_create(qmp->dev, np, &qmp_pcie_phy_ops);
- if (IS_ERR(*out_phy))
- return PTR_ERR(*out_phy);
-
- phy_set_drvdata(*out_phy, qmp);
+ phy_set_drvdata(phy, qmp);
+ *out_phy = phy;
return 0;
}
@@ -725,6 +1718,10 @@ static const struct of_device_id qmp_pcie_multiphy_of_match_table[] = {
.compatible = "qcom,glymur-qmp-gen5x8-pcie-phy",
.data = &glymur_qmp_gen5x8_match_data,
},
+ {
+ .compatible = "qcom,nord-qmp-gen5x16-pcie-phy",
+ .data = &nord_qmp_gen5x16_match_data,
+ },
{ }
};
MODULE_DEVICE_TABLE(of, qmp_pcie_multiphy_of_match_table);
@@ -739,5 +1736,5 @@ static struct platform_driver qmp_pcie_multiphy_driver = {
module_platform_driver(qmp_pcie_multiphy_driver);
MODULE_AUTHOR("Qiang Yu <qiang.yu@oss.qualcomm.com>");
-MODULE_DESCRIPTION("Qualcomm QMP PCIe Multi-PHY driver for Glymur");
+MODULE_DESCRIPTION("Qualcomm QMP PCIe Multi-PHY driver for Glymur and Nord");
MODULE_LICENSE("GPL");
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_40.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_40.h
new file mode 100644
index 000000000000..4c6859cebd42
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_40.h
@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef QCOM_PHY_QMP_PCS_PCIE_V6_40_H_
+#define QCOM_PHY_QMP_PCS_PCIE_V6_40_H_
+
+/* PCS COM — power, start, clocks */
+#define QPHY_PCIE_V6_40_PCS_COM_POWER_STATE_CONFIG2 0x06c
+#define QPHY_PCIE_V6_40_PCS_COM_POWER_STATE_CONFIG5 0x078
+#define QPHY_PCIE_V6_40_PCS_COM_POWER_STATE_CONFIG6 0x07c
+#define QPHY_PCIE_V6_40_PCS_COM_POWER_STATE_CONFIG7 0x080
+#define QPHY_PCIE_V6_40_PCS_COM_MULTIPHY_CONFIG2 0x088
+#define QPHY_PCIE_V6_40_PCS_COM_PCS_TX_RX_CONFIG2 0x0a0
+#define QPHY_PCIE_V6_40_PCS_COM_PCS_TX_RX_CONFIG3 0x0a4
+#define QPHY_PCIE_V6_40_PCS_COM_PCS_TX_RX_CONFIG5 0x0ac
+#define QPHY_PCIE_V6_40_PCS_COM_PCS_TX_RX_CONFIG6 0x0b0
+#define QPHY_PCIE_V6_40_PCS_COM_PCS_TX_RX_CONFIG7 0x0b4
+#define QPHY_PCIE_V6_40_PCS_COM_PCS_TX_RX_CONFIG8 0x0b8
+#define QPHY_PCIE_V6_40_PCS_COM_PCS_TX_RX_CONFIG10 0x0c0
+#define QPHY_PCIE_V6_40_PCS_COM_ENDPOINT_REFCLK_DRIVE 0x0c8
+#define QPHY_PCIE_V6_40_PCS_COM_RX_SIGDET_LVL 0x0ec
+#define QPHY_PCIE_V6_40_PCS_COM_DIVTX_CLK_DCC_CAL_CONFIG2 0x0f8
+#define QPHY_PCIE_V6_40_PCS_COM_DIVTX_CLK_DCC_CAL_CONFIG3 0x0fc
+#define QPHY_PCIE_V6_40_PCS_COM_DIVTX_CLK_DCC_CAL_CONFIG4 0x100
+#define QPHY_PCIE_V6_40_PCS_COM_OSC_DTCT_ACTIONS 0x194
+#define QPHY_PCIE_V6_40_PCS_COM_LOCK_DETECT_CONFIG1 0x1bc
+#define QPHY_PCIE_V6_40_PCS_COM_LOCK_DETECT_CONFIG2 0x1c0
+#define QPHY_PCIE_V6_40_PCS_COM_ALIGN_DETECT_CONFIG1 0x1dc
+#define QPHY_PCIE_V6_40_PCS_COM_ALIGN_DETECT_CONFIG2 0x1e0
+#define QPHY_PCIE_V6_40_PCS_COM_ALIGN_DETECT_CONFIG3 0x1e4
+#define QPHY_PCIE_V6_40_PCS_COM_ALIGN_DETECT_CONFIG7 0x1f4
+#define QPHY_PCIE_V6_40_PCS_COM_ALIGN_DETECT_CONFIG8 0x1f8
+
+/* PCS COM — EQ config */
+#define QPHY_PCIE_V6_40_PCS_COM_EQ_CONFIG1 0x380
+#define QPHY_PCIE_V6_40_PCS_COM_EQ_CONFIG2 0x384
+#define QPHY_PCIE_V6_40_PCS_COM_G345_EQ_CONFIG1 0x38c
+#define QPHY_PCIE_V6_40_PCS_COM_G345_EQ_CONFIG3 0x394
+#define QPHY_PCIE_V6_40_PCS_COM_G3_EQ_CONFIG1 0x3a4
+#define QPHY_PCIE_V6_40_PCS_COM_G3_EQ_CONFIG5 0x3b4
+#define QPHY_PCIE_V6_40_PCS_COM_G3_EQ_CONFIG7 0x3bc
+#define QPHY_PCIE_V6_40_PCS_COM_G4_EQ_CONFIG1 0x3c8
+#define QPHY_PCIE_V6_40_PCS_COM_G4_EQ_CONFIG5 0x3d8
+#define QPHY_PCIE_V6_40_PCS_COM_G4_EQ_CONFIG7 0x3e0
+#define QPHY_PCIE_V6_40_PCS_COM_G5_EQ_CONFIG1 0x3ec
+#define QPHY_PCIE_V6_40_PCS_COM_G5_EQ_CONFIG5 0x3fc
+#define QPHY_PCIE_V6_40_PCS_COM_G5_EQ_CONFIG7 0x404
+#define QPHY_PCIE_V6_40_PCS_COM_TEST_CONTROL1 0x468
+
+/* PCS LANEZ — output signal mux control */
+#define QPHY_PCIE_V6_40_PCS_LANEZ_OUTSIG_MX_CTRL2 0x0e0
+#define QPHY_PCIE_V6_40_PCS_LANEZ_OUTSIG_MX_CTRL5 0x0f8
+
+#endif /* QCOM_PHY_QMP_PCS_PCIE_V6_40_H_ */
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_40.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_40.h
new file mode 100644
index 000000000000..c7ac7b3bd97e
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_40.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef QCOM_PHY_QMP_PCS_V6_40_H_
+#define QCOM_PHY_QMP_PCS_V6_40_H_
+
+#define QPHY_V6_40_PCS_STATUS1 0x010
+#define QPHY_V6_40_PCS_START_CONTROL 0x05c
+#define QPHY_V6_40_PCS_SW_RESET 0x060
+#define QPHY_V6_40_PCS_POWER_DOWN_CONTROL 0x064
+
+#endif /* QCOM_PHY_QMP_PCS_V6_40_H_ */
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-pcie-v6_40.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-pcie-v6_40.h
new file mode 100644
index 000000000000..a7efd3a8718c
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-pcie-v6_40.h
@@ -0,0 +1,94 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef QCOM_PHY_QMP_QSERDES_COM_PCIE_V6_40_NORD_H_
+#define QCOM_PHY_QMP_QSERDES_COM_PCIE_V6_40_NORD_H_
+
+#define QSERDES_PCIE_V6_40_COM_SSC_STEP_SIZE1_MODE1 0x000
+#define QSERDES_PCIE_V6_40_COM_SSC_STEP_SIZE2_MODE1 0x004
+#define QSERDES_PCIE_V6_40_COM_CLK_EP_DIV_MODE1 0x00c
+#define QSERDES_PCIE_V6_40_COM_CP_CTRL_MODE1 0x010
+#define QSERDES_PCIE_V6_40_COM_PLL_RCTRL_MODE1 0x014
+#define QSERDES_PCIE_V6_40_COM_PLL_CCTRL_MODE1 0x018
+#define QSERDES_PCIE_V6_40_COM_CORECLK_DIV_MODE1 0x01c
+#define QSERDES_PCIE_V6_40_COM_LOCK_CMP1_MODE1 0x020
+#define QSERDES_PCIE_V6_40_COM_LOCK_CMP2_MODE1 0x024
+#define QSERDES_PCIE_V6_40_COM_DEC_START_MODE1 0x028
+#define QSERDES_PCIE_V6_40_COM_DIV_FRAC_START1_MODE1 0x030
+#define QSERDES_PCIE_V6_40_COM_DIV_FRAC_START2_MODE1 0x034
+#define QSERDES_PCIE_V6_40_COM_DIV_FRAC_START3_MODE1 0x038
+#define QSERDES_PCIE_V6_40_COM_HSCLK_SEL_1 0x03c
+#define QSERDES_PCIE_V6_40_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x050
+#define QSERDES_PCIE_V6_40_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x054
+#define QSERDES_PCIE_V6_40_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x058
+#define QSERDES_PCIE_V6_40_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x05c
+#define QSERDES_PCIE_V6_40_COM_SSC_STEP_SIZE1_MODE0 0x060
+#define QSERDES_PCIE_V6_40_COM_SSC_STEP_SIZE2_MODE0 0x064
+#define QSERDES_PCIE_V6_40_COM_CLK_EP_DIV_MODE0 0x06c
+#define QSERDES_PCIE_V6_40_COM_CP_CTRL_MODE0 0x070
+#define QSERDES_PCIE_V6_40_COM_PLL_RCTRL_MODE0 0x074
+#define QSERDES_PCIE_V6_40_COM_PLL_CCTRL_MODE0 0x078
+#define QSERDES_PCIE_V6_40_COM_CORECLK_DIV_MODE0 0x07c
+#define QSERDES_PCIE_V6_40_COM_LOCK_CMP1_MODE0 0x080
+#define QSERDES_PCIE_V6_40_COM_LOCK_CMP2_MODE0 0x084
+#define QSERDES_PCIE_V6_40_COM_DEC_START_MODE0 0x088
+#define QSERDES_PCIE_V6_40_COM_DIV_FRAC_START1_MODE0 0x090
+#define QSERDES_PCIE_V6_40_COM_DIV_FRAC_START2_MODE0 0x094
+#define QSERDES_PCIE_V6_40_COM_DIV_FRAC_START3_MODE0 0x098
+#define QSERDES_PCIE_V6_40_COM_HSCLK_HS_SWITCH_SEL_1 0x09c
+#define QSERDES_PCIE_V6_40_COM_BG_TIMER 0x0bc
+#define QSERDES_PCIE_V6_40_COM_SSC_EN_CENTER 0x0c0
+#define QSERDES_PCIE_V6_40_COM_SSC_PER1 0x0cc
+#define QSERDES_PCIE_V6_40_COM_SSC_PER2 0x0d0
+#define QSERDES_PCIE_V6_40_COM_POST_DIV_MUX 0x0d8
+#define QSERDES_PCIE_V6_40_COM_BIAS_EN_CLKBUFLR_EN 0x0dc
+#define QSERDES_PCIE_V6_40_COM_CLK_ENABLE1 0x0e0
+#define QSERDES_PCIE_V6_40_COM_SYS_CLK_CTRL 0x0e4
+#define QSERDES_PCIE_V6_40_COM_PLL_IVCO 0x0f4
+#define QSERDES_PCIE_V6_40_COM_CMN_IETRIM 0x0fc
+#define QSERDES_PCIE_V6_40_COM_SYSCLK_EN_SEL 0x110
+#define QSERDES_PCIE_V6_40_COM_LOCK_CMP_EN 0x120
+#define QSERDES_PCIE_V6_40_COM_LOCK_CMP_CFG 0x124
+#define QSERDES_PCIE_V6_40_COM_VCO_TUNE_CTRL 0x13c
+#define QSERDES_PCIE_V6_40_COM_VCO_TUNE_MAP 0x140
+#define QSERDES_PCIE_V6_40_COM_CLK_SELECT 0x164
+#define QSERDES_PCIE_V6_40_COM_CORE_CLK_EN 0x170
+#define QSERDES_PCIE_V6_40_COM_CMN_CONFIG_1 0x174
+#define QSERDES_PCIE_V6_40_COM_CMN_MISC1 0x188
+#define QSERDES_PCIE_V6_40_COM_CMN_MODE 0x18c
+#define QSERDES_PCIE_V6_40_COM_BIN_VCOCAL_HSCLK_SEL_1 0x1a0
+#define QSERDES_PCIE_V6_40_COM_VCO_DC_LEVEL_CTRL 0x19c
+#define QSERDES_PCIE_V6_40_COM_HSCLK_SEL_2 0x21c
+#define QSERDES_PCIE_V6_40_COM_BIN_VCOCAL_CMP_CODE1_MODE2 0x220
+#define QSERDES_PCIE_V6_40_COM_BIN_VCOCAL_CMP_CODE2_MODE2 0x224
+#define QSERDES_PCIE_V6_40_COM_HSCLK_HS_SWITCH_SEL_2 0x228
+#define QSERDES_PCIE_V6_40_COM_BIN_VCOCAL_HSCLK_SEL_2 0x230
+#define QSERDES_PCIE_V6_40_COM_CMN_CONFIG_2 0x22c
+#define QSERDES_PCIE_V6_40_COM_SSC_STEP_SIZE1_MODE2 0x1cc
+#define QSERDES_PCIE_V6_40_COM_SSC_STEP_SIZE2_MODE2 0x1d0
+#define QSERDES_PCIE_V6_40_COM_CP_CTRL_MODE2 0x1dc
+#define QSERDES_PCIE_V6_40_COM_PLL_RCTRL_MODE2 0x1e0
+#define QSERDES_PCIE_V6_40_COM_PLL_CCTRL_MODE2 0x1e4
+#define QSERDES_PCIE_V6_40_COM_CORECLK_DIV_MODE2 0x1e8
+#define QSERDES_PCIE_V6_40_COM_LOCK_CMP1_MODE2 0x1ec
+#define QSERDES_PCIE_V6_40_COM_LOCK_CMP2_MODE2 0x1f0
+#define QSERDES_PCIE_V6_40_COM_DEC_START_MODE2 0x1f4
+#define QSERDES_PCIE_V6_40_COM_DIV_FRAC_START1_MODE2 0x1fc
+#define QSERDES_PCIE_V6_40_COM_DIV_FRAC_START2_MODE2 0x200
+#define QSERDES_PCIE_V6_40_COM_DIV_FRAC_START3_MODE2 0x204
+#define QSERDES_PCIE_V6_40_COM_DCC_CAL_1 0x2d8
+#define QSERDES_PCIE_V6_40_COM_DCC_CAL_2 0x2dc
+#define QSERDES_PCIE_V6_40_COM_DCC_CAL_3 0x2e0
+#define QSERDES_PCIE_V6_40_COM_PSM_CAL_EN 0x2f0
+#define QSERDES_PCIE_V6_40_COM_CLK_FWD_CONFIG_1 0x2f4
+#define QSERDES_PCIE_V6_40_COM_IP_CTRL_AND_DP_SEL 0x2fc
+#define QSERDES_PCIE_V6_40_COM_PLL_SPARE_FOR_ECO 0x2b8
+#define QSERDES_PCIE_V6_40_COM_PLL_IVCO_MODE1 0x0f8
+#define QSERDES_PCIE_V6_40_COM_PLL_IVCO_MODE2 0x218
+#define QSERDES_PCIE_V6_40_COM_DCC_CAL_7 0x300
+#define QSERDES_PCIE_V6_40_COM_DCC_CAL_8 0x304
+#define QSERDES_PCIE_V6_40_COM_DCC_CAL_9 0x308
+
+#endif /* QCOM_PHY_QMP_QSERDES_COM_PCIE_V6_40_NORD_H_ */
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrxz-pcie-v6_40.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrxz-pcie-v6_40.h
new file mode 100644
index 000000000000..dba8599be1fb
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrxz-pcie-v6_40.h
@@ -0,0 +1,194 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef QCOM_PHY_QMP_QSERDES_TXRXZ_PCIE_V6_40_NORD_H_
+#define QCOM_PHY_QMP_QSERDES_TXRXZ_PCIE_V6_40_NORD_H_
+
+/* Lane mode / LDO */
+#define QSERDES_PCIE_V6_40_TXRXZ_PCIE_V6_40_TOP_LDO_CODE_CTRL1 0x070
+#define QSERDES_PCIE_V6_40_TXRXZ_PCIE_V6_40_TOP_LDO_CODE_CTRL2 0x074
+#define QSERDES_PCIE_V6_40_TXRXZ_PCIE_V6_40_TOP_LDO_CODE_CTRL3 0x078
+#define QSERDES_PCIE_V6_40_TXRXZ_PCIE_V6_40_TOP_LDO_CODE_CTRL4 0x07c
+#define QSERDES_PCIE_V6_40_TXRXZ_LANE_MODE_1 0x094
+#define QSERDES_PCIE_V6_40_TXRXZ_LANE_MODE_2 0x098
+#define QSERDES_PCIE_V6_40_TXRXZ_LANE_MODE_3 0x09c
+#define QSERDES_PCIE_V6_40_TXRXZ_LANE_MODE_4 0x0a0
+#define QSERDES_PCIE_V6_40_TXRXZ_RESTRIM_VREF_SEL 0x0bc
+#define QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE_0_1_B0 0x0f4
+#define QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE_0_1_B1 0x0f8
+#define QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE_0_1_B2 0x0fc
+#define QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE_0_1_B3 0x100
+#define QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE_0_1_B4 0x104
+#define QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE_0_1_B5 0x108
+#define QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE_0_1_B6 0x10c
+#define QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE_0_1_B7 0x110
+#define QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE2_B0 0x114
+#define QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE2_B1 0x118
+#define QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE2_B2 0x11c
+#define QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE2_B3 0x120
+#define QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE2_B4 0x124
+#define QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE2_B5 0x128
+#define QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE2_B6 0x12c
+#define QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE2_B7 0x130
+#define QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE3_B0 0x134
+#define QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE3_B1 0x138
+#define QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE3_B2 0x13c
+#define QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE3_B3 0x140
+#define QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE3_B4 0x144
+#define QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE3_B5 0x148
+#define QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE3_B6 0x14c
+#define QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE3_B7 0x150
+#define QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE4_B0 0x154
+#define QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE4_B1 0x158
+#define QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE4_B2 0x15c
+#define QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE4_B3 0x160
+#define QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE4_B4 0x164
+#define QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE4_B5 0x168
+#define QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE4_B6 0x16c
+#define QSERDES_PCIE_V6_40_TXRXZ_RX_MODE_RATE4_B7 0x170
+
+/* VCO / KVCO calibration */
+#define QSERDES_PCIE_V6_40_TXRXZ_CDR_VCO_CTUNE_MEAS_CNT1_RATE0 0x1b4
+#define QSERDES_PCIE_V6_40_TXRXZ_CDR_VCO_CTUNE_MEAS_CNT2_RATE0 0x1b8
+#define QSERDES_PCIE_V6_40_TXRXZ_CDR_VCO_CTUNE_MEAS_CNT1_RATE1 0x1bc
+#define QSERDES_PCIE_V6_40_TXRXZ_CDR_VCO_CTUNE_MEAS_CNT2_RATE1 0x1c0
+#define QSERDES_PCIE_V6_40_TXRXZ_CDR_VCO_CTUNE_MEAS_CNT1_RATE2 0x1c4
+#define QSERDES_PCIE_V6_40_TXRXZ_CDR_VCO_CTUNE_MEAS_CNT2_RATE2 0x1c8
+#define QSERDES_PCIE_V6_40_TXRXZ_CDR_VCO_CTUNE_MEAS_CNT1_RATE3 0x1cc
+#define QSERDES_PCIE_V6_40_TXRXZ_CDR_VCO_CTUNE_MEAS_CNT2_RATE3 0x1d0
+#define QSERDES_PCIE_V6_40_TXRXZ_CDR_VCO_CTUNE_MEAS_CNT1_RATE4 0x1d4
+#define QSERDES_PCIE_V6_40_TXRXZ_CDR_VCO_CTUNE_MEAS_CNT2_RATE4 0x1d8
+#define QSERDES_PCIE_V6_40_TXRXZ_CDR_VCTRL_RATE_0_1 0x1dc
+#define QSERDES_PCIE_V6_40_TXRXZ_CDR_VCTRL_RATE_2_3 0x1e0
+#define QSERDES_PCIE_V6_40_TXRXZ_KVCO_INIT_RATE_0_1 0x1e8
+#define QSERDES_PCIE_V6_40_TXRXZ_KVCO_INIT_RATE_2_3 0x1ec
+#define QSERDES_PCIE_V6_40_TXRXZ_KVCO_INIT_RATE_4 0x1f0
+#define QSERDES_PCIE_V6_40_TXRXZ_KVCO_CODE_OVRD_RATE0 0x1f4
+#define QSERDES_PCIE_V6_40_TXRXZ_KVCO_CODE_OVRD_RATE1 0x1f8
+#define QSERDES_PCIE_V6_40_TXRXZ_KVCO_CODE_OVRD_RATE2 0x1fc
+#define QSERDES_PCIE_V6_40_TXRXZ_KVCO_IDEAL_FREQ_DIFF1_RATE0 0x220
+#define QSERDES_PCIE_V6_40_TXRXZ_KVCO_IDEAL_FREQ_DIFF2_RATE0 0x224
+#define QSERDES_PCIE_V6_40_TXRXZ_KVCO_IDEAL_FREQ_DIFF1_RATE1 0x228
+#define QSERDES_PCIE_V6_40_TXRXZ_KVCO_IDEAL_FREQ_DIFF2_RATE1 0x22c
+#define QSERDES_PCIE_V6_40_TXRXZ_KVCO_IDEAL_FREQ_DIFF1_RATE2 0x230
+#define QSERDES_PCIE_V6_40_TXRXZ_KVCO_IDEAL_FREQ_DIFF2_RATE2 0x234
+#define QSERDES_PCIE_V6_40_TXRXZ_KVCO_IDEAL_FREQ_DIFF1_RATE3 0x238
+#define QSERDES_PCIE_V6_40_TXRXZ_KVCO_IDEAL_FREQ_DIFF1_RATE4 0x240
+#define QSERDES_PCIE_V6_40_TXRXZ_KP_CODE_OVRD_RATE_2_3 0x250
+#define QSERDES_PCIE_V6_40_TXRXZ_KP_CAL_UPPER_FREQ_DIFF_BND1_RATE0 0x258
+#define QSERDES_PCIE_V6_40_TXRXZ_KP_CAL_UPPER_FREQ_DIFF_BND1_RATE1 0x260
+#define QSERDES_PCIE_V6_40_TXRXZ_KP_CAL_UPPER_FREQ_DIFF_BND1_RATE2 0x268
+#define QSERDES_PCIE_V6_40_TXRXZ_KP_CAL_UPPER_FREQ_DIFF_BND1_RATE3 0x270
+#define QSERDES_PCIE_V6_40_TXRXZ_KP_CAL_UPPER_FREQ_DIFF_BND1_RATE4 0x278
+#define QSERDES_PCIE_V6_40_TXRXZ_KP_CAL_LOWER_FREQ_DIFF_BND_RATE0 0x280
+#define QSERDES_PCIE_V6_40_TXRXZ_KP_CAL_LOWER_FREQ_DIFF_BND_RATE1 0x284
+#define QSERDES_PCIE_V6_40_TXRXZ_KP_CAL_LOWER_FREQ_DIFF_BND_RATE2 0x288
+#define QSERDES_PCIE_V6_40_TXRXZ_KP_CAL_LOWER_FREQ_DIFF_BND_RATE3 0x28c
+#define QSERDES_PCIE_V6_40_TXRXZ_KP_CAL_LOWER_FREQ_DIFF_BND_RATE4 0x290
+#define QSERDES_PCIE_V6_40_TXRXZ_RX_SUMMER_CAL_SPD_MODE_RATE_0123 0x2a8
+#define QSERDES_PCIE_V6_40_TXRXZ_RX_IVCM_CAL_CTRL2 0x2c8
+#define QSERDES_PCIE_V6_40_TXRXZ_RX_IVCM_CAL_CTRL3 0x2cc
+#define QSERDES_PCIE_V6_40_TXRXZ_RX_IVCM_CAL_CTRL4 0x2d0
+
+/* Signal detect */
+#define QSERDES_PCIE_V6_40_TXRXZ_SIGDET_ENABLES 0x31c
+#define QSERDES_PCIE_V6_40_TXRXZ_FREQ_LOCK_DET_DLY_RATE0 0x33c
+#define QSERDES_PCIE_V6_40_TXRXZ_FREQ_LOCK_DET_DLY_RATE1 0x340
+#define QSERDES_PCIE_V6_40_TXRXZ_FREQ_LOCK_DET_DLY_RATE2 0x344
+#define QSERDES_PCIE_V6_40_TXRXZ_FREQ_LOCK_DET_DLY_RATE3 0x348
+#define QSERDES_PCIE_V6_40_TXRXZ_FREQ_LOCK_DET_DLY_RATE4 0x34c
+
+/* CDR */
+#define QSERDES_PCIE_V6_40_TXRXZ_CDR_LOCK_CTRL 0x364
+#define QSERDES_PCIE_V6_40_TXRXZ_CDR_CP_CUR_FLL_RATE0 0x368
+#define QSERDES_PCIE_V6_40_TXRXZ_CDR_CP_CUR_FLL_RATE1 0x36c
+#define QSERDES_PCIE_V6_40_TXRXZ_CDR_CP_CUR_FLL_RATE2 0x370
+#define QSERDES_PCIE_V6_40_TXRXZ_CDR_CP_CUR_FLL_RATE3 0x374
+#define QSERDES_PCIE_V6_40_TXRXZ_CDR_CP_CUR_FLL_RATE4 0x378
+#define QSERDES_PCIE_V6_40_TXRXZ_CDR_CP_CUR_PLL_RATE0 0x37c
+#define QSERDES_PCIE_V6_40_TXRXZ_CDR_CP_CUR_PLL_RATE1 0x380
+#define QSERDES_PCIE_V6_40_TXRXZ_CDR_CP_CUR_PLL_RATE2 0x384
+#define QSERDES_PCIE_V6_40_TXRXZ_CDR_CP_CUR_PLL_RATE3 0x388
+#define QSERDES_PCIE_V6_40_TXRXZ_CDR_CP_CUR_PLL_RATE4 0x38c
+#define QSERDES_PCIE_V6_40_TXRXZ_CDR_FLL_DIV_RATIO_RATE_0123 0x390
+#define QSERDES_PCIE_V6_40_TXRXZ_CDR_LOOP_CCODE_RATE_01 0x398
+#define QSERDES_PCIE_V6_40_TXRXZ_CDR_LOOP_CCODE_RATE_23 0x39c
+#define QSERDES_PCIE_V6_40_TXRXZ_CDR_LOOP_CCODE_RATE4 0x3a0
+#define QSERDES_PCIE_V6_40_TXRXZ_CDR_LOOP_RCODE_FAST_RATE_0_1 0x3a4
+#define QSERDES_PCIE_V6_40_TXRXZ_CDR_LOOP_RCODE_FAST_RATE_2_3 0x3a8
+#define QSERDES_PCIE_V6_40_TXRXZ_CDR_LOOP_RCODE_FAST_RATE4 0x3ac
+#define QSERDES_PCIE_V6_40_TXRXZ_CDR_LOOP_RCODE_FLL_RATE_0_1 0x3b0
+#define QSERDES_PCIE_V6_40_TXRXZ_CDR_LOOP_RCODE_FLL_RATE_2_3 0x3b4
+#define QSERDES_PCIE_V6_40_TXRXZ_CDR_LOOP_RCODE_FLL_RATE4 0x3b8
+#define QSERDES_PCIE_V6_40_TXRXZ_CDR_LOOP_RCODE_PLL_RATE_0_1 0x3bc
+#define QSERDES_PCIE_V6_40_TXRXZ_CDR_LOOP_RCODE_PLL_RATE_2_3 0x3c0
+#define QSERDES_PCIE_V6_40_TXRXZ_CDR_LOOP_RCODE_PLL_RATE4 0x3c4
+#define QSERDES_PCIE_V6_40_TXRXZ_CDR_VCO_CAP_CODE_RATE_0123 0x3c8
+#define QSERDES_PCIE_V6_40_TXRXZ_CDR_VCO_TYPE_CONFIG 0x3d0
+#define QSERDES_PCIE_V6_40_TXRXZ_CDR_VCO_EN_LOWFREQ 0x3d4
+#define QSERDES_PCIE_V6_40_TXRXZ_CDR_LOOP_FUNC_CTRL 0x3dc
+
+/* Rescode / residuals */
+#define QSERDES_PCIE_V6_40_TXRXZ_RES_CODE_LANE_OFFSET_RX 0x3f4
+
+/* VGA / GM calibration */
+#define QSERDES_PCIE_V6_40_TXRXZ_GM_CAL_RES_RATE0_1 0x404
+#define QSERDES_PCIE_V6_40_TXRXZ_GM_CAL_RES_RATE2_3 0x408
+#define QSERDES_PCIE_V6_40_TXRXZ_GM_CAL_RES_RATE4 0x40c
+
+/* RX equalizer */
+#define QSERDES_PCIE_V6_40_TXRXZ_RX_EQU_ADAPTOR_CNTRL3 0x454
+#define QSERDES_PCIE_V6_40_TXRXZ_RX_EQU_ADAPTOR_CNTRL4 0x458
+#define QSERDES_PCIE_V6_40_TXRXZ_RX_EQU_ADAPTOR_CNTRL5 0x45c
+#define QSERDES_PCIE_V6_40_TXRXZ_CTLE_POST_CAL_OFFSET_RATE_0_1_2 0x478
+#define QSERDES_PCIE_V6_40_TXRXZ_VGA_CAL_MAN_VAL_RATE0_1 0x490
+#define QSERDES_PCIE_V6_40_TXRXZ_VGA_CAL_MAN_VAL_RATE2_3 0x494
+#define QSERDES_PCIE_V6_40_TXRXZ_VGA_CAL_MAN_VAL_RATE4 0x498
+#define QSERDES_PCIE_V6_40_TXRXZ_VTHRESH_CAL_MAN_VAL_RATE4 0x4bc
+
+/* DFE */
+#define QSERDES_PCIE_V6_40_TXRXZ_DFE_TAP1_DAC_ENABLE 0x50c
+#define QSERDES_PCIE_V6_40_TXRXZ_DFE_TAP2_DAC_ENABLE 0x510
+#define QSERDES_PCIE_V6_40_TXRXZ_DFE_TAP345_DAC_ENABLE 0x514
+#define QSERDES_PCIE_V6_40_TXRXZ_DFE_TAP67_DAC_ENABLE 0x518
+#define QSERDES_PCIE_V6_40_TXRXZ_PHPRE_CTRL 0x51c
+#define QSERDES_PCIE_V6_40_TXRXZ_TX_ADAPT_POST_THRESH1 0x52c
+#define QSERDES_PCIE_V6_40_TXRXZ_TX_ADAPT_POST_THRESH2 0x530
+#define QSERDES_PCIE_V6_40_TXRXZ_TX_ADPT_CTRL 0x53c
+#define QSERDES_PCIE_V6_40_TXRXZ_CDR_IQTUNE_CTRL 0x548
+#define QSERDES_PCIE_V6_40_TXRXZ_CDR_IQTUNE_MAN_INDEX 0x550
+#define QSERDES_PCIE_V6_40_TXRXZ_CDR_IQTUNE_ANA_CTRL 0x584
+#define QSERDES_PCIE_V6_40_TXRXZ_CDR_IQTUNE_DIV2_CTRL_RATE0123 0x58c
+#define QSERDES_PCIE_V6_40_TXRXZ_CDR_VCO_CAP_CODE_OVRD_MUXES 0x5ac
+#define QSERDES_PCIE_V6_40_TXRXZ_CDR_VCO_CAP_CODE_RATE4 0x3cc
+
+/* Clock buffer / LDO stall control (used by bifurcated pre/post-pwrup sequences) */
+#define QSERDES_PCIE_V6_40_TXRXZ_CLKBUF_ENABLE 0x04c
+#define QSERDES_PCIE_V6_40_TXRXZ_PRE_STALL_LDO_BOOST_EN 0x06c
+#define QSERDES_PCIE_V6_40_TXRXZ_LDO_TIMER_CTRL 0x0d8
+
+/* Restrim / VGA / signal-detect (v2-only) */
+#define QSERDES_PCIE_V6_40_TXRXZ_RESTRIM_CAL_CTRL 0x0b0
+#define QSERDES_PCIE_V6_40_TXRXZ_RESTRIM_POST_CAL_OFFSET 0x0b8
+#define QSERDES_PCIE_V6_40_TXRXZ_SIGDET_CNTRL 0x320
+#define QSERDES_PCIE_V6_40_TXRXZ_SIGDET_LVL 0x324
+#define QSERDES_PCIE_V6_40_TXRXZ_SIGDET_CAL_CTRL1 0x32c
+#define QSERDES_PCIE_V6_40_TXRXZ_VGA_CAL_CNTRL1 0x488
+
+/* BLW / VCO coarse-tune bands (v2-only) */
+#define QSERDES_PCIE_V6_40_TXRXZ_BLW_CTRL 0x594
+#define QSERDES_PCIE_V6_40_TXRXZ_BLW_MAN_VAL_RATE3 0x5a4
+#define QSERDES_PCIE_V6_40_TXRXZ_BLW_MAN_VAL_RATE4 0x5a8
+#define QSERDES_PCIE_V6_40_TXRXZ_VCO_CTUNE_UPPER_BND_RATE0 0x5c4
+#define QSERDES_PCIE_V6_40_TXRXZ_VCO_CTUNE_UPPER_BND_RATE1 0x5c8
+#define QSERDES_PCIE_V6_40_TXRXZ_VCO_CTUNE_UPPER_BND_RATE2 0x5cc
+#define QSERDES_PCIE_V6_40_TXRXZ_VCO_CTUNE_UPPER_BND_RATE3 0x5d0
+#define QSERDES_PCIE_V6_40_TXRXZ_VCO_CTUNE_UPPER_BND_RATE4 0x5d4
+
+/* Analog backup control (v2-only) */
+#define QSERDES_PCIE_V6_40_TXRXZ_DIG_BKUP_CTRL15 0x7e8
+#define QSERDES_PCIE_V6_40_TXRXZ_DIG_BKUP_CTRL16 0x7ec
+
+#endif /* QCOM_PHY_QMP_QSERDES_TXRXZ_PCIE_V6_40_NORD_H_ */
--
2.34.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 1/4] dt-bindings: phy: qcom: add Nord QMP PCIe PHY binding
2026-08-25 3:40 ` [PATCH 1/4] dt-bindings: phy: qcom: add Nord QMP PCIe PHY binding Krishna Chaitanya Chundru
@ 2026-08-25 9:04 ` Krzysztof Kozlowski
0 siblings, 0 replies; 6+ messages in thread
From: Krzysztof Kozlowski @ 2026-08-25 9:04 UTC (permalink / raw)
To: Krishna Chaitanya Chundru, Vinod Koul, Neil Armstrong,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Lorenzo Pieralisi,
Krzysztof Wilczyński, Manivannan Sadhasivam, Bjorn Helgaas,
Bjorn Andersson, Maxime Chevallier, Philipp Zabel
Cc: linux-arm-msm, linux-phy, devicetree, linux-kernel, linux-pci
On 25/08/2026 05:40, Krishna Chaitanya Chundru wrote:
> Document the PCIe PHY found on the Qualcomm Nord platform.
>
> Nord has a Gen5-capable QMP PCIe PHY that can operate in multiple
> lane configurations using four PHY segments (A/B/C/D). The active
> topology is selected by firmware through a TCSR configuration
> register and may be configured as x16, x8+x8, x8+x4+x4, or
> x8+x4+x2+x2.
>
> The binding describes the register regions, clocks, resets, power
> domains, regulators, PHY provider interface, clock provider interface,
> and the qcom,link-mode property used by the driver to discover the
> active lane configuration programmed by firmware.
>
> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
> ---
> .../bindings/phy/qcom,nord-qmp-pcie-phy.yaml | 276 +++++++++++++++++++++
> 1 file changed, 276 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/phy/qcom,nord-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,nord-qmp-pcie-phy.yaml
> new file mode 100644
> index 000000000000..3575e99dadfd
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/qcom,nord-qmp-pcie-phy.yaml
> @@ -0,0 +1,276 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/qcom,nord-qmp-pcie-phy.yaml#
Filename should match compatible.
...
> + #clock-cells = <1>;
> + clock-output-names = "pcie_a_pipe_clk",
> + "pcie_b_pipe_clk",
> + "pcie_c_pipe_clk",
> + "pcie_d_pipe_clk";
> +
> + #phy-cells = <1>;
> + status = "disabled";
So your code was never tested. Drop. Please read carefully writing
bindings/schema, DTS101 or internal guideline.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2026-08-25 9:04 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-08-25 3:40 [PATCH 0/4] Add PCIe support for Qualcomm Nord platform Krishna Chaitanya Chundru
2026-08-25 3:40 ` [PATCH 1/4] dt-bindings: phy: qcom: add Nord QMP PCIe PHY binding Krishna Chaitanya Chundru
2026-08-25 9:04 ` Krzysztof Kozlowski
2026-08-25 3:40 ` [PATCH 2/4] dt-bindings: pci: qcom: add Nord PCIe controller compatible Krishna Chaitanya Chundru
2026-08-25 3:40 ` [PATCH 3/4] PCI: qcom: Add CGC disable workaround for Nord PCIe Krishna Chaitanya Chundru
2026-08-25 3:40 ` [PATCH 4/4] phy: qcom: qmp-pcie: Add Nord Gen5x16 PCIe multi-PHY support Krishna Chaitanya Chundru
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