From: sashiko-bot@kernel.org
To: "Santhosh Kumar K" <s-k6@ti.com>
Cc: "Miquel Raynal" <miquel.raynal@bootlin.com>,
"Pratyush Yadav" <pratyush@kernel.org>,
robh@kernel.org, "Michael Walle" <mwalle@kernel.org>,
"Takahiro Kuwano" <takahiro.kuwano@infineon.com>,
conor+dt@kernel.org, "Richard Weinberger" <richard@nod.at>,
devicetree@vger.kernel.org,
"Vignesh Raghavendra" <vigneshr@ti.com>
Subject: Re: [PATCH v9 03/18] spi: parse spi-max-post-config-frequency-hz into post_config_max_speed_hz
Date: Tue, 25 Aug 2026 17:30:43 +0000 [thread overview]
Message-ID: <20260825173043.F21CA1F00A3A@smtp.kernel.org> (raw)
In-Reply-To: <20260825171737.776052-4-s-k6@ti.com>
Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Medium] The new `post_config_max_speed_hz` property is not clamped to the SPI controller's maximum supported speed during device setup.
- [Medium] `post_config_max_speed_hz` is not copied to ancillary or multiplexed SPI devices, breaking high-speed operations for multi-die packages and proxy devices.
--
commit 5705672f7b6c77c877910c5996844e5029e278fd
Author: Santhosh Kumar K <s-k6@ti.com>
spi: parse spi-max-post-config-frequency-hz into post_config_max_speed_hz
This commit adds a post_config_max_speed_hz field to struct spi_device to
support SPI devices operating at distinct pre- and post-configuration clock
rates. The new property is parsed from the spi-max-post-config-frequency-hz
Device Tree property.
> diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h
> index 88d17fce02dcb..02fd602f29e8b 100644
> --- a/include/linux/spi/spi.h
> +++ b/include/linux/spi/spi.h
[ ... ]
> @@ -195,6 +197,7 @@ struct spi_device {
> struct device dev;
> struct spi_controller *controller;
> u32 max_speed_hz;
> + u32 post_config_max_speed_hz;
[Severity: Medium]
Does the new post_config_max_speed_hz need to be clamped to the controller's
maximum supported speed during device setup?
Looking at drivers/spi/spi.c:__spi_setup(), the existing max_speed_hz is
strictly validated against the hardware capabilities:
if (spi->controller->max_speed_hz &&
(!spi->max_speed_hz ||
spi->max_speed_hz > spi->controller->max_speed_hz))
spi->max_speed_hz = spi->controller->max_speed_hz;
Without similar clamping for post_config_max_speed_hz, a misconfigured
Device Tree could inject an arbitrarily large frequency, causing the
underlying controller to configure hardware for an unsupported rate.
[Severity: Medium]
Should post_config_max_speed_hz also be cloned for ancillary or multiplexed
SPI devices to ensure multi-die packages can use post-config speeds?
Looking at drivers/spi/spi.c:spi_new_ancillary_device(), only the primary
max_speed_hz is copied to secondary logical devices:
/* Take over SPI mode/speed from SPI main device */
ancillary->max_speed_hz = spi->max_speed_hz;
ancillary->mode = spi->mode;
A similar omission exists in drivers/spi/spi-mux.c:spi_mux_select():
/* copy the child device's settings except for the cs */
priv->spi->max_speed_hz = spi->max_speed_hz;
priv->spi->mode = spi->mode;
Without cloning this new property, these proxy devices will have a zero
post-config frequency, forcing secondary dies to operate at the slower
pre-configuration rate.
> u8 bits_per_word;
> bool rt;
> #define SPI_NO_TX BIT(31) /* No transmit wire */
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260825171737.776052-1-s-k6@ti.com?part=3
next prev parent reply other threads:[~2026-08-25 17:30 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-25 17:17 [PATCH v9 00/18] spi: cadence-quadspi: add PHY tuning support Santhosh Kumar K
2026-08-25 17:17 ` [PATCH v9 01/18] spi: dt-bindings: add spi-max-post-config-frequency-hz property Santhosh Kumar K
2026-08-25 17:17 ` [PATCH v9 02/18] spi: dt-bindings: add spi-phy-pattern-partition property Santhosh Kumar K
2026-08-25 17:17 ` [PATCH v9 03/18] spi: parse spi-max-post-config-frequency-hz into post_config_max_speed_hz Santhosh Kumar K
2026-08-25 17:30 ` sashiko-bot [this message]
2026-08-25 17:17 ` [PATCH v9 04/18] spi: spi-mem: teach spi_mem_adjust_op_freq() about post-config ops Santhosh Kumar K
2026-08-25 17:30 ` sashiko-bot
2026-08-25 17:17 ` [PATCH v9 05/18] spi: spi-mem: add execute_tuning callback and spi_mem_execute_tuning() Santhosh Kumar K
2026-08-25 17:17 ` [PATCH v9 06/18] spi: cadence-quadspi: move cqspi_readdata_capture earlier Santhosh Kumar K
2026-08-25 17:17 ` [PATCH v9 07/18] spi: cadence-quadspi: add DQS support to read data capture Santhosh Kumar K
2026-08-25 17:29 ` sashiko-bot
2026-08-25 17:17 ` [PATCH v9 08/18] spi: cadence-quadspi: add PHY tuning support Santhosh Kumar K
2026-08-25 17:40 ` sashiko-bot
2026-08-26 21:43 ` Mark Brown
2026-08-25 17:17 ` [PATCH v9 09/18] spi: cadence-quadspi: skip DDR PHY tuning for 2-byte-address ops (i2383) Santhosh Kumar K
2026-08-25 17:17 ` [PATCH v9 10/18] spi: cadence-quadspi: refactor direct read path for PHY support Santhosh Kumar K
2026-08-25 17:31 ` sashiko-bot
2026-08-25 17:17 ` [PATCH v9 11/18] spi: cadence-quadspi: enable PHY for direct reads Santhosh Kumar K
2026-08-25 17:32 ` sashiko-bot
2026-08-25 17:17 ` [PATCH v9 12/18] spi: cadence-quadspi: enable PHY for indirect writes Santhosh Kumar K
2026-08-25 17:32 ` sashiko-bot
2026-08-25 17:17 ` [PATCH v9 13/18] spi: cadence-quadspi: reprogram CS timing on every chip-select switch Santhosh Kumar K
2026-08-25 17:17 ` [PATCH v9 14/18] spi: cadence-quadspi: reprogram PHY DLL on runtime resume Santhosh Kumar K
2026-08-25 17:36 ` sashiko-bot
2026-08-25 17:17 ` [PATCH v9 15/18] mtd: spinand: extract variant ranking logic into spinand_op_find_best_variant() Santhosh Kumar K
2026-08-25 17:17 ` [PATCH v9 16/18] mtd: spinand: negotiate optimal controller operating point before dirmap creation Santhosh Kumar K
2026-08-25 17:43 ` sashiko-bot
2026-08-25 17:17 ` [PATCH v9 17/18] mtd: spi-nor: extract read op template construction into helper Santhosh Kumar K
2026-08-25 17:17 ` [PATCH v9 18/18] mtd: spi-nor: run controller optimization before dirmap creation Santhosh Kumar K
2026-08-25 17:45 ` sashiko-bot
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