Re: [PATCH v3 5/5] arm64: dts: rockchip: add ISP nodes to rk3588

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Low] Mismatch between the number of interrupts and interrupt-names in the isp0 node, violating the dt-binding schema.
- [Low] The newly added ISP and IOMMU nodes are not sorted by their unit address in the .dtsi file.
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commit 9cc7cdafa66ffa2298585c4888f169256dd48661
Author: Xu Hongfei <xuhf@rock-chips.com>

arm64: dts: rockchip: add ISP nodes to rk3588

Add device tree nodes for the ISP and their iommus on the RK3588.

> diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
> index fc1fdbfd31622..22b78465a8235 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
> @@ -3590,6 +3590,63 @@ gpio4: gpio@fec50000 {
>  			#interrupt-cells = <2>;
>  		};
>  	};
> +
> +	isp0: isp@fdcb0000 {
> +		compatible = "rockchip,rk3588-isp";

[Severity: Low]
Are these new ISP and IOMMU nodes sorted by their unit address in the .dtsi
file? 

The standard convention is to order sibling nodes strictly by their unit
address, but placing isp@fdcb0000 after gpio@fec50000 breaks this
chronological ordering.

> +		reg = <0x0 0xfdcb0000 0x0 0x7f00>;
> +		interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>,
> +			     <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH 0>,
> +			     <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH 0>;
> +		interrupt-names = "isp_irq", "mi_irq";

[Severity: Low]
Is there a mismatch here between the number of items in the interrupts
property and the interrupt-names property?

The rockchip,rk3588-isp dt-binding schema strictly enforces a maximum of 2
items for the interrupts property. Including three interrupts will result
in a schema validation error when building the devicetree with dtbs_check.

[ ... ]

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260827-rkisp2-v3-0-e91ff0a604d6@ideasonboard.com?part=5