[PATCH 00/11] arm64: dts: qcom: Disable Inline Crypto Engine by default accross all SoCs

[PATCH 00/11] arm64: dts: qcom: Disable Inline Crypto Engine by default accross all SoCs

[Abel Vesa]

Since UFS_PHY_GDSC was attached to the Inline Crypto Engine and the driver
does not currently do runtime PM, the GDSC remains enabled while the
device is idle, even on boards where there are no consumers.

I'm working on getting runtime PM enabled in the ICE driver, but the
node should not be enabled on such boards anyways.

So disable the Inline Crypto Engine by default in the SoC DTSI and enable
it only in board DTS files that use it.

Do this accross the board, for all SoCs that have dedicated ICE DT node.

Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
Abel Vesa (11):
      arm64: dts: qcom: sm8550: Disable Inline Crypto Engine by default
      arm64: dts: qcom: sm8450: Disable Inline Crypto Engine by default
      arm64: dts: qcom: sm8650: Disable Inline Crypto Engine by default
      arm64: dts: qcom: sm8750: Disable Inline Crypto Engine by default
      arm64: dts: qcom: eliza: Disable Inline Crypto Engine by default
      arm64: dts: qcom: kaanapali: Disable Inline Crypto Engine by default
      arm64: dts: qcom: lemans: Disable Inline Crypto Engine by default
      arm64: dts: qcom: milos: Disable Inline Crypto Engine by default
      arm64: dts: qcom: kodiak: Disable Inline Crypto Engine by default
      arm64: dts: qcom: monaco: Disable Inline Crypto Engine by default
      arm64: dts: qcom: sc7180: Disable Inline Crypto Engine by default

 arch/arm64/boot/dts/qcom/eliza-mtp.dts                        | 4 ++++
 arch/arm64/boot/dts/qcom/eliza.dtsi                           | 2 ++
 arch/arm64/boot/dts/qcom/kaanapali-mtp.dts                    | 4 ++++
 arch/arm64/boot/dts/qcom/kaanapali-qrd.dts                    | 4 ++++
 arch/arm64/boot/dts/qcom/kaanapali.dtsi                       | 2 ++
 arch/arm64/boot/dts/qcom/kodiak.dtsi                          | 2 ++
 arch/arm64/boot/dts/qcom/lemans-evk.dts                       | 4 ++++
 arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi              | 4 ++++
 arch/arm64/boot/dts/qcom/lemans.dtsi                          | 2 ++
 arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts              | 4 ++++
 arch/arm64/boot/dts/qcom/milos.dtsi                           | 2 ++
 arch/arm64/boot/dts/qcom/monaco-evk.dts                       | 4 ++++
 arch/arm64/boot/dts/qcom/monaco.dtsi                          | 2 ++
 arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts            | 4 ++++
 arch/arm64/boot/dts/qcom/qcm6490-idp.dts                      | 4 ++++
 arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts         | 4 ++++
 arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts              | 4 ++++
 arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts                  | 4 ++++
 arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts | 4 ++++
 arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts     | 4 ++++
 arch/arm64/boot/dts/qcom/qcs8300-ride.dts                     | 4 ++++
 arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi                  | 4 ++++
 arch/arm64/boot/dts/qcom/qcs8550-rb5gen2.dts                  | 4 ++++
 arch/arm64/boot/dts/qcom/sc7180.dtsi                          | 2 ++
 arch/arm64/boot/dts/qcom/sc7280-idp.dtsi                      | 4 ++++
 arch/arm64/boot/dts/qcom/sm7125-xiaomi-common.dtsi            | 4 ++++
 arch/arm64/boot/dts/qcom/sm7325-motorola-dubai-common.dtsi    | 4 ++++
 arch/arm64/boot/dts/qcom/sm7325-motorola-dubai.dts            | 4 ++++
 arch/arm64/boot/dts/qcom/sm7325-nothing-spacewar.dts          | 4 ++++
 arch/arm64/boot/dts/qcom/sm7325-xiaomi-taoyao.dts             | 4 ++++
 arch/arm64/boot/dts/qcom/sm8450-hdk.dts                       | 4 ++++
 arch/arm64/boot/dts/qcom/sm8450-qrd.dts                       | 4 ++++
 arch/arm64/boot/dts/qcom/sm8450.dtsi                          | 2 ++
 arch/arm64/boot/dts/qcom/sm8550-hdk.dts                       | 4 ++++
 arch/arm64/boot/dts/qcom/sm8550-mtp.dts                       | 4 ++++
 arch/arm64/boot/dts/qcom/sm8550-qrd.dts                       | 4 ++++
 arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts               | 4 ++++
 arch/arm64/boot/dts/qcom/sm8550.dtsi                          | 2 ++
 arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts          | 4 ++++
 arch/arm64/boot/dts/qcom/sm8650-hdk.dts                       | 4 ++++
 arch/arm64/boot/dts/qcom/sm8650-mtp.dts                       | 4 ++++
 arch/arm64/boot/dts/qcom/sm8650-qrd.dts                       | 4 ++++
 arch/arm64/boot/dts/qcom/sm8650.dtsi                          | 2 ++
 arch/arm64/boot/dts/qcom/sm8750-mtp.dts                       | 4 ++++
 arch/arm64/boot/dts/qcom/sm8750-qrd.dts                       | 4 ++++
 arch/arm64/boot/dts/qcom/sm8750.dtsi                          | 2 ++
 46 files changed, 162 insertions(+)
---
base-commit: 3d83758432b5e6ed9507500a57efb0f3af41ee7d
change-id: 20260828-b4-dts-qcom-disable-ice-by-default-4d9cde057a51

Best regards,
--  
Abel Vesa <abel.vesa@oss.qualcomm.com>

[PATCH 01/11] arm64: dts: qcom: sm8550: Disable Inline Crypto Engine by default

[Abel Vesa]

Since UFS_PHY_GDSC is attached to the Inline Crypto Engine and the driver
does not currently enable runtime PM, the GDSC remains enabled while the
device is idle, even on boards where there are no consumers.

So disable the Inline Crypto Engine by default in the SoC DTSI and enable
it only in board DTS files that use it.

Fixes: 52696dbbe7bb ("arm64: dts: qcom: sm8550: Add power-domain and iface clk for ice node")
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi    | 4 ++++
 arch/arm64/boot/dts/qcom/qcs8550-rb5gen2.dts    | 4 ++++
 arch/arm64/boot/dts/qcom/sm8550-hdk.dts         | 4 ++++
 arch/arm64/boot/dts/qcom/sm8550-mtp.dts         | 4 ++++
 arch/arm64/boot/dts/qcom/sm8550-qrd.dts         | 4 ++++
 arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts | 4 ++++
 arch/arm64/boot/dts/qcom/sm8550.dtsi            | 2 ++
 7 files changed, 26 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi b/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi
index ae301d78e071..ddcbdb1b9fca 100644
--- a/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi
@@ -326,6 +326,10 @@ vreg_l3g_1p2: ldo3 {
 	};
 };
 
+&ice {
+	status = "okay";
+};
+
 &mdss_dsi0 {
 	vdda-supply = <&vreg_l3e_1p2>;
 };
diff --git a/arch/arm64/boot/dts/qcom/qcs8550-rb5gen2.dts b/arch/arm64/boot/dts/qcom/qcs8550-rb5gen2.dts
index 9df8dcd6c62b..da460474fac0 100644
--- a/arch/arm64/boot/dts/qcom/qcs8550-rb5gen2.dts
+++ b/arch/arm64/boot/dts/qcom/qcs8550-rb5gen2.dts
@@ -998,6 +998,10 @@ &i2c_master_hub_0 {
 	status = "okay";
 };
 
+&ice {
+	status = "okay";
+};
+
 &ipa {
 	firmware-name = "qcom/sm8550/ipa_fws.mbn";
 
diff --git a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
index 82fb10ed6b6b..cf4821716f27 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
@@ -1024,6 +1024,10 @@ &i2c_master_hub_0 {
 	status = "okay";
 };
 
+&ice {
+	status = "okay";
+};
+
 &ipa {
 	firmware-name = "qcom/sm8550/ipa_fws.mbn";
 	status = "okay";
diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts
index 7c634572c6b7..f54cef78292b 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts
@@ -672,6 +672,10 @@ fsa4480_sbu_mux: endpoint {
 	};
 };
 
+&ice {
+	status = "okay";
+};
+
 &iris {
 	status = "okay";
 };
diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
index 473ec4e27daf..e26c37ee5bb7 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
@@ -903,6 +903,10 @@ fsa4480_sbu_mux: endpoint {
 	};
 };
 
+&ice {
+	status = "okay";
+};
+
 &ipa {
 	firmware-name = "qcom/sm8550/ipa_fws.mbn";
 	status = "okay";
diff --git a/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts b/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts
index 81c02ee27fe9..3956941b21bc 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts
@@ -509,6 +509,10 @@ &i2c_master_hub_0 {
 	status = "okay";
 };
 
+&ice {
+	status = "okay";
+};
+
 &pcie0 {
 	wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
 	perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index 0e701e709235..a2bfd857f3fc 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -2840,6 +2840,8 @@ ice: crypto@1d88000 {
 			clock-names = "core",
 				      "iface";
 			power-domains = <&gcc UFS_PHY_GDSC>;
+
+			status = "disabled";
 		};
 
 		tcsr_mutex: hwlock@1f40000 {

-- 
2.54.0

[PATCH 02/11] arm64: dts: qcom: sm8450: Disable Inline Crypto Engine by default

[Abel Vesa]

Since UFS_PHY_GDSC is attached to the Inline Crypto Engine and the driver
does not currently enable runtime PM, the GDSC remains enabled while the
device is idle, even on boards where there are no consumers.

So disable the Inline Crypto Engine by default in the SoC DTSI and enable
it only in board DTS files that use it.

Fixes: 3a5cb1ccbfb3 ("arm64: dts: qcom: sm8450: Add power-domain and iface clk for ice node")
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 4 ++++
 arch/arm64/boot/dts/qcom/sm8450-qrd.dts | 4 ++++
 arch/arm64/boot/dts/qcom/sm8450.dtsi    | 2 ++
 3 files changed, 10 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts
index 4ade28f40cae..424c06e88afa 100644
--- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts
@@ -713,6 +713,10 @@ fsa4480_sbu_mux: endpoint {
 	};
 };
 
+&ice {
+	status = "okay";
+};
+
 &mdss {
 	status = "okay";
 };
diff --git a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts
index 4993059483e9..cf054226fa24 100644
--- a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts
+++ b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts
@@ -414,6 +414,10 @@ &i2c5 {
 	status = "okay";
 };
 
+&ice {
+	status = "okay";
+};
+
 &qupv3_id_0 {
 	status = "okay";
 };
diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index b8793482b181..6f9d5a87f1c4 100644
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -5370,6 +5370,8 @@ ice: crypto@1d88000 {
 			clock-names = "core",
 				      "iface";
 			power-domains = <&gcc UFS_PHY_GDSC>;
+
+			status = "disabled";
 		};
 
 		cryptobam: dma-controller@1dc4000 {

-- 
2.54.0

[PATCH 03/11] arm64: dts: qcom: sm8650: Disable Inline Crypto Engine by default

[Abel Vesa]

Since UFS_PHY_GDSC is attached to the Inline Crypto Engine and the driver
does not currently enable runtime PM, the GDSC remains enabled while the
device is idle, even on boards where there are no consumers.

So disable the Inline Crypto Engine by default in the SoC DTSI and enable
it only in board DTS files that use it.

Fixes: c62b084d5d15 ("arm64: dts: qcom: sm8650: Add power-domain and iface clk for ice node")
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts | 4 ++++
 arch/arm64/boot/dts/qcom/sm8650-hdk.dts              | 4 ++++
 arch/arm64/boot/dts/qcom/sm8650-mtp.dts              | 4 ++++
 arch/arm64/boot/dts/qcom/sm8650-qrd.dts              | 4 ++++
 arch/arm64/boot/dts/qcom/sm8650.dtsi                 | 2 ++
 5 files changed, 18 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts b/arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts
index 6ddf30ecabfe..1e93141cb754 100644
--- a/arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts
+++ b/arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts
@@ -1053,6 +1053,10 @@ redriver_ss_in: endpoint {
 	};
 };
 
+&ice {
+	status = "okay";
+};
+
 &iris {
 	status = "okay";
 };
diff --git a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts
index 41d0c7edc433..79594d6ce9a8 100644
--- a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts
@@ -973,6 +973,10 @@ lt9611_out: endpoint {
 	};
 };
 
+&ice {
+	status = "okay";
+};
+
 &ipa {
 	firmware-name = "qcom/sm8650/ipa_fws.mbn";
 
diff --git a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts
index 26045430d34a..129f77e1b100 100644
--- a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts
@@ -585,6 +585,10 @@ vreg_l7n_3p3: ldo7 {
 	};
 };
 
+&ice {
+	status = "okay";
+};
+
 &iris {
 	status = "okay";
 };
diff --git a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts
index 1fb78588a504..6dbdfe6b8fe1 100644
--- a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts
+++ b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts
@@ -946,6 +946,10 @@ redriver_ss_in: endpoint {
 	};
 };
 
+&ice {
+	status = "okay";
+};
+
 &ipa {
 	firmware-name = "qcom/sm8650/ipa_fws.mbn";
 
diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
index b679fd8afb7d..384aa2203dfa 100644
--- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
@@ -4142,6 +4142,8 @@ ice: crypto@1d88000 {
 			clock-names = "core",
 				      "iface";
 			power-domains = <&gcc UFS_PHY_GDSC>;
+
+			status = "disabled";
 		};
 
 		cryptobam: dma-controller@1dc4000 {

-- 
2.54.0

[PATCH 04/11] arm64: dts: qcom: sm8750: Disable Inline Crypto Engine by default

[Abel Vesa]

Since UFS_PHY_GDSC is attached to the Inline Crypto Engine and the driver
does not currently enable runtime PM, the GDSC remains enabled while the
device is idle, even on boards where there are no consumers.

So disable the Inline Crypto Engine by default in the SoC DTSI and enable
it only in board DTS files that use it.

Fixes: 081ac792f0ea ("arm64: dts: qcom: sm8750: Add power-domain and iface clk for ice node")
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/sm8750-mtp.dts | 4 ++++
 arch/arm64/boot/dts/qcom/sm8750-qrd.dts | 4 ++++
 arch/arm64/boot/dts/qcom/sm8750.dtsi    | 2 ++
 3 files changed, 10 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8750-mtp.dts b/arch/arm64/boot/dts/qcom/sm8750-mtp.dts
index 9b5fbc004df4..dc7ec23183ba 100644
--- a/arch/arm64/boot/dts/qcom/sm8750-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/sm8750-mtp.dts
@@ -971,6 +971,10 @@ wcd_usbss_headset_out: endpoint {
 	};
 };
 
+&ice {
+	status = "okay";
+};
+
 &iris {
 	status = "okay";
 };
diff --git a/arch/arm64/boot/dts/qcom/sm8750-qrd.dts b/arch/arm64/boot/dts/qcom/sm8750-qrd.dts
index b56317cfa9fc..0b28b381cf9c 100644
--- a/arch/arm64/boot/dts/qcom/sm8750-qrd.dts
+++ b/arch/arm64/boot/dts/qcom/sm8750-qrd.dts
@@ -858,6 +858,10 @@ vreg_l7n_3p3: ldo7 {
 	};
 };
 
+&ice {
+	status = "okay";
+};
+
 &iris {
 	status = "okay";
 };
diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi
index dd738d13df8e..76ab96633f74 100644
--- a/arch/arm64/boot/dts/qcom/sm8750.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi
@@ -2140,6 +2140,8 @@ ice: crypto@1d88000 {
 			clock-names = "core",
 				      "iface";
 			power-domains = <&gcc GCC_UFS_PHY_GDSC>;
+
+			status = "disabled";
 		};
 
 		cryptobam: dma-controller@1dc4000 {

-- 
2.54.0

[PATCH 05/11] arm64: dts: qcom: eliza: Disable Inline Crypto Engine by default

[Abel Vesa]

Since UFS_PHY_GDSC is attached to the Inline Crypto Engine and the driver
does not currently enable runtime PM, the GDSC remains enabled while the
device is idle, even on boards where there are no consumers.

So disable the Inline Crypto Engine by default in the SoC DTSI and enable
it only in board DTS files that use it.

Fixes: 90825ab392ac ("arm64: dts: qcom: eliza: Add power-domain and iface clk for ice node")
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/eliza-mtp.dts | 4 ++++
 arch/arm64/boot/dts/qcom/eliza.dtsi    | 2 ++
 2 files changed, 6 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/eliza-mtp.dts b/arch/arm64/boot/dts/qcom/eliza-mtp.dts
index 868ae6c34830..4cba8fbbc1da 100644
--- a/arch/arm64/boot/dts/qcom/eliza-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/eliza-mtp.dts
@@ -422,6 +422,10 @@ vreg_l7k: ldo7 {
 	};
 };
 
+&ice {
+	status = "okay";
+};
+
 &mdss {
 	status = "okay";
 };
diff --git a/arch/arm64/boot/dts/qcom/eliza.dtsi b/arch/arm64/boot/dts/qcom/eliza.dtsi
index 66ea4aaafd73..52c4c28d1b7f 100644
--- a/arch/arm64/boot/dts/qcom/eliza.dtsi
+++ b/arch/arm64/boot/dts/qcom/eliza.dtsi
@@ -1926,6 +1926,8 @@ ice: crypto@1d88000 {
 			clock-names = "core",
 				      "iface";
 			power-domains = <&gcc GCC_UFS_PHY_GDSC>;
+
+			status = "disabled";
 		};
 
 		cryptobam: dma-controller@1dc4000 {

-- 
2.54.0

[PATCH 06/11] arm64: dts: qcom: kaanapali: Disable Inline Crypto Engine by default

[Abel Vesa]

Since UFS_PHY_GDSC is attached to the Inline Crypto Engine and the driver
does not currently enable runtime PM, the GDSC remains enabled while the
device is idle, even on boards where there are no consumers.

So disable the Inline Crypto Engine by default in the SoC DTSI and enable
it only in board DTS files that use it.

Fixes: 11b48f6d5ed5 ("arm64: dts: qcom: kaanapali: Add power-domain and iface clk for ice node")
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/kaanapali-mtp.dts | 4 ++++
 arch/arm64/boot/dts/qcom/kaanapali-qrd.dts | 4 ++++
 arch/arm64/boot/dts/qcom/kaanapali.dtsi    | 2 ++
 3 files changed, 10 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
index 6d817381bb37..f1629889354a 100644
--- a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
@@ -908,6 +908,10 @@ vreg_l7n_3p3: ldo7 {
 	};
 };
 
+&ice {
+	status = "okay";
+};
+
 &lpass_vamacro {
 	pinctrl-0 = <&dmic01_default>, <&dmic23_default>;
 	pinctrl-names = "default";
diff --git a/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts b/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts
index abd3e9f8a3eb..1560717b6ea1 100644
--- a/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts
+++ b/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts
@@ -736,6 +736,10 @@ vreg_l7n_3p3: ldo7 {
 	};
 };
 
+&ice {
+	status = "okay";
+};
+
 &pmh0101_flash {
 	status = "okay";
 
diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
index 131fd2a16c54..0aafb249af76 100644
--- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi
+++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
@@ -2619,6 +2619,8 @@ ice: crypto@1d88000 {
 			clock-names = "core",
 				      "iface";
 			power-domains = <&gcc GCC_UFS_PHY_GDSC>;
+
+			status = "disabled";
 		};
 
 		cryptobam: dma-controller@1dc4000 {

-- 
2.54.0

[PATCH 07/11] arm64: dts: qcom: lemans: Disable Inline Crypto Engine by default

[Abel Vesa]

Since UFS_PHY_GDSC is attached to the Inline Crypto Engine and the driver
does not currently enable runtime PM, the GDSC remains enabled while the
device is idle, even on boards where there are no consumers.

So disable the Inline Crypto Engine by default in the SoC DTSI and enable
it only in board DTS files that use it.

Fixes: 04566e287b35 ("arm64: dts: qcom: lemans: Add power-domain and iface clk for ice node")
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/lemans-evk.dts          | 4 ++++
 arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi | 4 ++++
 arch/arm64/boot/dts/qcom/lemans.dtsi             | 2 ++
 3 files changed, 10 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/lemans-evk.dts b/arch/arm64/boot/dts/qcom/lemans-evk.dts
index a45485b54a5b..27dda67f3504 100644
--- a/arch/arm64/boot/dts/qcom/lemans-evk.dts
+++ b/arch/arm64/boot/dts/qcom/lemans-evk.dts
@@ -786,6 +786,10 @@ fan {
 	};
 };
 
+&ice {
+	status = "okay";
+};
+
 &iris {
 	firmware-name = "qcom/vpu/vpu30_p4_s6_16mb.mbn";
 
diff --git a/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi b/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi
index 144f117ba511..714414806730 100644
--- a/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi
+++ b/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi
@@ -581,6 +581,10 @@ dsi2dp_bridge1_out: endpoint {
 
 };
 
+&ice {
+	status = "okay";
+};
+
 &iris {
 	firmware-name = "qcom/vpu/vpu30_p4_s6.mbn";
 
diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi
index 695eae1b7256..0795b2be56cb 100644
--- a/arch/arm64/boot/dts/qcom/lemans.dtsi
+++ b/arch/arm64/boot/dts/qcom/lemans.dtsi
@@ -3093,6 +3093,8 @@ ice: crypto@1d88000 {
 			clock-names = "core",
 				      "iface";
 			power-domains = <&gcc UFS_PHY_GDSC>;
+
+			status = "disabled";
 		};
 
 		cryptobam: dma-controller@1dc4000 {

-- 
2.54.0

[PATCH 08/11] arm64: dts: qcom: milos: Disable Inline Crypto Engine by default

[Abel Vesa]

Since UFS_PHY_GDSC is attached to the Inline Crypto Engine and the driver
does not currently enable runtime PM, the GDSC remains enabled while the
device is idle, even on boards where there are no consumers.

So disable the Inline Crypto Engine by default in the SoC DTSI and enable
it only in board DTS files that use it.

Fixes: b7c9047f851e ("arm64: dts: qcom: milos: Add power-domain and iface clk for ice node")
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts | 4 ++++
 arch/arm64/boot/dts/qcom/milos.dtsi              | 2 ++
 2 files changed, 6 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts b/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts
index bb3b67e2fd01..dbda9dddcee7 100644
--- a/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts
+++ b/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts
@@ -700,6 +700,10 @@ vibrator@5a {
 	};
 };
 
+&ice {
+	status = "okay";
+};
+
 &ipa {
 	firmware-name = "qcom/milos/fairphone/fp6/ipa_fws.mbn";
 	memory-region = <&ipa_fw_mem>;
diff --git a/arch/arm64/boot/dts/qcom/milos.dtsi b/arch/arm64/boot/dts/qcom/milos.dtsi
index aad8bf678916..b910990e2220 100644
--- a/arch/arm64/boot/dts/qcom/milos.dtsi
+++ b/arch/arm64/boot/dts/qcom/milos.dtsi
@@ -1281,6 +1281,8 @@ ice: crypto@1d88000 {
 			clock-names = "core",
 				      "iface";
 			power-domains = <&gcc UFS_PHY_GDSC>;
+
+			status = "disabled";
 		};
 
 		cryptobam: dma-controller@1dc4000 {

-- 
2.54.0

[PATCH 09/11] arm64: dts: qcom: kodiak: Disable Inline Crypto Engine by default

[Abel Vesa]

Since UFS_PHY_GDSC is attached to the Inline Crypto Engine and the driver
does not currently enable runtime PM, the GDSC remains enabled while the
device is idle, even on boards where there are no consumers.

So disable the Inline Crypto Engine by default in the SoC DTSI and enable
it only in board DTS files that use it.

Fixes: cca53c338ad8 ("arm64: dts: qcom: kodiak: Add power-domain and iface clk for ice node")
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/kodiak.dtsi                          | 2 ++
 arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts            | 4 ++++
 arch/arm64/boot/dts/qcom/qcm6490-idp.dts                      | 4 ++++
 arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts         | 4 ++++
 arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts              | 4 ++++
 arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts                  | 4 ++++
 arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts | 4 ++++
 arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts     | 4 ++++
 arch/arm64/boot/dts/qcom/sc7280-idp.dtsi                      | 4 ++++
 arch/arm64/boot/dts/qcom/sm7325-motorola-dubai-common.dtsi    | 4 ++++
 arch/arm64/boot/dts/qcom/sm7325-motorola-dubai.dts            | 4 ++++
 arch/arm64/boot/dts/qcom/sm7325-nothing-spacewar.dts          | 4 ++++
 arch/arm64/boot/dts/qcom/sm7325-xiaomi-taoyao.dts             | 4 ++++
 13 files changed, 50 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi
index f2da3706d5c8..ffbf037b3838 100644
--- a/arch/arm64/boot/dts/qcom/kodiak.dtsi
+++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi
@@ -2586,6 +2586,8 @@ ice: crypto@1d88000 {
 			clock-names = "core",
 				      "iface";
 			power-domains = <&gcc GCC_UFS_PHY_GDSC>;
+
+			status = "disabled";
 		};
 
 		cryptobam: dma-controller@1dc4000 {
diff --git a/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts b/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts
index f41ad446a39e..b2e0cb0b3f71 100644
--- a/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts
+++ b/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts
@@ -937,6 +937,10 @@ &i2c9 {
 	/* VL53L3 ToF @ 29 */
 };
 
+&ice {
+	status = "okay";
+};
+
 &ipa {
 	firmware-name = "qcom/qcm6490/fairphone5/ipa_fws.mbn";
 
diff --git a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts
index 58cce89a0c1c..079254928e57 100644
--- a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts
+++ b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts
@@ -619,6 +619,10 @@ &gpu_zap_shader {
 	firmware-name = "qcom/qcm6490/a660_zap.mbn";
 };
 
+&ice {
+	status = "okay";
+};
+
 &lpass_rx_macro {
 	status = "okay";
 };
diff --git a/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts b/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts
index 5bb33a8a9830..f3f0ef54eeb8 100644
--- a/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts
+++ b/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts
@@ -499,6 +499,10 @@ &i2c1 {
 	status = "okay";
 };
 
+&ice {
+	status = "okay";
+};
+
 &ipa {
 	firmware-name = "qcom/qcm6490/particle/tachyon/ipa_fws.mbn";
 
diff --git a/arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts b/arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts
index cf74b3664cf5..e97e94572beb 100644
--- a/arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts
+++ b/arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts
@@ -552,6 +552,10 @@ &i2c13 {
 	/* focaltech FT3658U @ 38 */
 };
 
+&ice {
+	status = "okay";
+};
+
 &ipa {
 	firmware-name = "qcom/qcm6490/SHIFT/otter/ipa_fws.mbn";
 
diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
index a13315bf0fb0..dd83c424273e 100644
--- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
+++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
@@ -789,6 +789,10 @@ redriver_usb_con_sbu: endpoint {
 	};
 };
 
+&ice {
+	status = "okay";
+};
+
 &lpass_va_macro {
 	status = "okay";
 };
diff --git a/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts
index 31bafa2cf51d..394d1aff854a 100644
--- a/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts
+++ b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts
@@ -653,6 +653,10 @@ redriver_usb_con_sbu: endpoint {
 	};
 };
 
+&ice {
+	status = "okay";
+};
+
 &ipa {
 	/delete-property/ memory-region;
 };
diff --git a/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts
index 13e8e62f6205..7a1c8d868ddb 100644
--- a/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts
+++ b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts
@@ -774,6 +774,10 @@ lt9611_out: endpoint {
 	};
 };
 
+&ice {
+	status = "okay";
+};
+
 &ipa {
 	/delete-property/ memory-region;
 };
diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
index 96a7327f00a8..1bf3de6a4228 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
@@ -373,6 +373,10 @@ &gpi_dma1 {
 	status = "okay";
 };
 
+&ice {
+	status = "okay";
+};
+
 &lpass_cpu {
 	status = "okay";
 
diff --git a/arch/arm64/boot/dts/qcom/sm7325-motorola-dubai-common.dtsi b/arch/arm64/boot/dts/qcom/sm7325-motorola-dubai-common.dtsi
index 3860ab8508a0..bc183bd94da0 100644
--- a/arch/arm64/boot/dts/qcom/sm7325-motorola-dubai-common.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm7325-motorola-dubai-common.dtsi
@@ -723,6 +723,10 @@ fsa4480_sbu_mux: endpoint {
 	};
 };
 
+&ice {
+	status = "okay";
+};
+
 &ipa {
 	firmware-name = "qcom/sm7325/motorola/dubai/yupik_ipa_fws.mbn";
 	memory-region = <&ipa_fw_mem>;
diff --git a/arch/arm64/boot/dts/qcom/sm7325-motorola-dubai.dts b/arch/arm64/boot/dts/qcom/sm7325-motorola-dubai.dts
index d94571c05a59..51ec276d252e 100644
--- a/arch/arm64/boot/dts/qcom/sm7325-motorola-dubai.dts
+++ b/arch/arm64/boot/dts/qcom/sm7325-motorola-dubai.dts
@@ -725,6 +725,10 @@ fsa4480_sbu_mux: endpoint {
 	};
 };
 
+&ice {
+	status = "okay";
+};
+
 &ipa {
 	firmware-name = "qcom/sm7325/motorola/dubai/yupik_ipa_fws.mbn";
 
diff --git a/arch/arm64/boot/dts/qcom/sm7325-nothing-spacewar.dts b/arch/arm64/boot/dts/qcom/sm7325-nothing-spacewar.dts
index 7db9ae1c3cef..f96e8d7241ec 100644
--- a/arch/arm64/boot/dts/qcom/sm7325-nothing-spacewar.dts
+++ b/arch/arm64/boot/dts/qcom/sm7325-nothing-spacewar.dts
@@ -970,6 +970,10 @@ nfc@28 {
 	};
 };
 
+&ice {
+	status = "okay";
+};
+
 &ipa {
 	firmware-name = "qcom/sm7325/nothing/spacewar/ipa_fws.mbn";
 
diff --git a/arch/arm64/boot/dts/qcom/sm7325-xiaomi-taoyao.dts b/arch/arm64/boot/dts/qcom/sm7325-xiaomi-taoyao.dts
index 87f267aaeec0..19940fa627f1 100644
--- a/arch/arm64/boot/dts/qcom/sm7325-xiaomi-taoyao.dts
+++ b/arch/arm64/boot/dts/qcom/sm7325-xiaomi-taoyao.dts
@@ -638,6 +638,10 @@ fsa4480_sbu_mux: endpoint {
 	};
 };
 
+&ice {
+	status = "okay";
+};
+
 &ipa {
 	firmware-name = "qcom/sm7325/xiaomi/taoyao/ipa_fws.mbn";
 

-- 
2.54.0

[PATCH 10/11] arm64: dts: qcom: monaco: Disable Inline Crypto Engine by default

[Abel Vesa]

Since UFS_PHY_GDSC is attached to the Inline Crypto Engine and the driver
does not currently enable runtime PM, the GDSC remains enabled while the
device is idle, even on boards where there are no consumers.

So disable the Inline Crypto Engine by default in the SoC DTSI and enable
it only in board DTS files that use it.

Fixes: 68d5d9701a7a ("arm64: dts: qcom: monaco: Add power-domain and iface clk for ice node")
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/monaco-evk.dts   | 4 ++++
 arch/arm64/boot/dts/qcom/monaco.dtsi      | 2 ++
 arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 4 ++++
 3 files changed, 10 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/monaco-evk.dts b/arch/arm64/boot/dts/qcom/monaco-evk.dts
index 9d17ef7d2caf..25980c003a49 100644
--- a/arch/arm64/boot/dts/qcom/monaco-evk.dts
+++ b/arch/arm64/boot/dts/qcom/monaco-evk.dts
@@ -585,6 +585,10 @@ expander6: gpio@3e {
 	};
 };
 
+&ice {
+	status = "okay";
+};
+
 &iris {
 	status = "okay";
 };
diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi
index cfe39f923224..e9b807df4a8b 100644
--- a/arch/arm64/boot/dts/qcom/monaco.dtsi
+++ b/arch/arm64/boot/dts/qcom/monaco.dtsi
@@ -2723,6 +2723,8 @@ ice: crypto@1d88000 {
 			clock-names = "core",
 				      "iface";
 			power-domains = <&gcc GCC_UFS_PHY_GDSC>;
+
+			status = "disabled";
 		};
 
 		crypto: crypto@1dfa000 {
diff --git a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts
index 1ff39530ea3d..fbe36a3fc47b 100644
--- a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts
+++ b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts
@@ -569,6 +569,10 @@ dsi2dp_bridge_out: endpoint {
 	};
 };
 
+&ice {
+	status = "okay";
+};
+
 &pmm8650au_1_gpios {
 	usb2_en: usb2-en-state {
 		pins = "gpio7";

-- 
2.54.0

[PATCH 11/11] arm64: dts: qcom: sc7180: Disable Inline Crypto Engine by default

[Abel Vesa]

Since UFS_PHY_GDSC is attached to the Inline Crypto Engine and the driver
does not currently enable runtime PM, the GDSC remains enabled while the
device is idle, even on boards where there are no consumers.

So disable the Inline Crypto Engine by default in the SoC DTSI and enable
it only in board DTS files that use it.

Fixes: 7cd7271ac525 ("arm64: dts: qcom: sc7180: Add power-domain and iface clk for ice node")
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/sc7180.dtsi               | 2 ++
 arch/arm64/boot/dts/qcom/sm7125-xiaomi-common.dtsi | 4 ++++
 2 files changed, 6 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index 70fbfb31d4a4..9aabecdc57cc 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -1611,6 +1611,8 @@ ice: crypto@1d90000 {
 			clock-names = "core",
 				      "iface";
 			power-domains = <&gcc UFS_PHY_GDSC>;
+
+			status = "disabled";
 		};
 
 		ipa: ipa@1e40000 {
diff --git a/arch/arm64/boot/dts/qcom/sm7125-xiaomi-common.dtsi b/arch/arm64/boot/dts/qcom/sm7125-xiaomi-common.dtsi
index b9cff60efe6f..cb419a44ea4d 100644
--- a/arch/arm64/boot/dts/qcom/sm7125-xiaomi-common.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm7125-xiaomi-common.dtsi
@@ -333,6 +333,10 @@ &dispcc {
 	status = "disabled";
 };
 
+&ice {
+	status = "okay";
+};
+
 &pm6150_resin {
 	linux,code = <KEY_VOLUMEDOWN>;
 	status = "okay";

-- 
2.54.0

Re: [PATCH 01/11] arm64: dts: qcom: sm8550: Disable Inline Crypto Engine by default

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Disabling the Inline Crypto Engine (ICE) node by default in the SoC DTSI causes UFS probe to fail for any board that enables UFS without explicitly enabling ICE, breaking backward compatibility.
--

commit 16a0192ad11b331cfd04d9e22cced4ae705ad4f3
Author: Abel Vesa <abel.vesa@oss.qualcomm.com>

arm64: dts: qcom: sm8550: Disable Inline Crypto Engine by default

Since UFS_PHY_GDSC is attached to the Inline Crypto Engine and the driver
does not currently enable runtime PM, the GDSC remains enabled while the
device is idle, even on boards where there are no consumers.

So disable the Inline Crypto Engine by default in the SoC DTSI and enable
it only in board DTS files that use it.

> diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> index 0e701e709235c..a2bfd857f3fc0 100644
> --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> @@ -2840,6 +2840,8 @@ ice: crypto@1d88000 {
>  			clock-names = "core",
>  				      "iface";
>  			power-domains = <&gcc UFS_PHY_GDSC>;
> +
> +			status = "disabled";

[Severity: High]
Does disabling the ICE node by default break backward compatibility for
boards that enable UFS without explicitly enabling ICE?

Since the qcom,ice phandle is retained in the ufs_mem_hc node, when a
board doesn't explicitly set status = "okay" for the ICE node,
of_find_device_by_node() will return NULL for the disabled node.

This causes of_qcom_ice_get() to return -ENODEV instead of -EOPNOTSUPP:

drivers/soc/qcom/ice.c:of_qcom_ice_get() {
    ...
	pdev = of_find_device_by_node(node);
	if (!pdev) {
		dev_err(dev, "Cannot find device node %s\n", node->name);
		return ERR_PTR(-ENODEV);
	}
    ...
}

Because it returns -ENODEV, the UFS driver treats this as a hard error and
aborts the entire UFS probe, rather than gracefully degrading without inline
encryption:

drivers/ufs/host/ufs-qcom.c:ufs_qcom_ice_init() {
    ...
	ice = devm_of_qcom_ice_get(dev);
	if (IS_ERR(ice)) {
		if (ice != ERR_PTR(-EOPNOTSUPP))
			return PTR_ERR(ice);
    ...
}

Could this prevent the system from booting if the root filesystem is on UFS?

>  		};
>  
>  		tcsr_mutex: hwlock@1f40000 {

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260828-b4-dts-qcom-disable-ice-by-default-v1-0-1d6e0c2f5a69@oss.qualcomm.com?part=1

Re: [PATCH 00/11] arm64: dts: qcom: Disable Inline Crypto Engine by default accross all SoCs

[Kuldeep Singh]

On 28-08-2026 18:07, Abel Vesa wrote:
> Since UFS_PHY_GDSC was attached to the Inline Crypto Engine and the driver
> does not currently do runtime PM, the GDSC remains enabled while the
> device is idle, even on boards where there are no consumers.
> 
> I'm working on getting runtime PM enabled in the ICE driver, but the
> node should not be enabled on such boards anyways.
> 
> So disable the Inline Crypto Engine by default in the SoC DTSI and enable
> it only in board DTS files that use it.
> 
> Do this accross the board, for all SoCs that have dedicated ICE DT node.
> 
> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>

Kindly check discussion happenend before on adding such implementation.

https://lore.kernel.org/all/56ab63c3-4288-45f7-bfea-d40046437a9f@oss.qualcomm.com/

The idea is to enable ice as default and independent of storage media
and enable runtime PM enabled.

-- 
Regards
Kuldeep

Re: [PATCH 03/11] arm64: dts: qcom: sm8650: Disable Inline Crypto Engine by default

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Disabling the Inline Crypto Engine (ICE) node by default in `sm8650.dtsi` breaks the UFS controller probe on any board that does not explicitly re-enable it. The `ufs_mem_hc` node retains the `qcom,ice = <&ice>;` property, so `of_parse_phandle()` successfully finds the disabled node. However, because the node is disabled, no platform device is created for it, causing `of_find_device_by_node()` to return NULL. As a result, `of_qcom_ice_get()` returns `-ENODEV` instead of the graceful fallback `-EOPNOTSUPP`. The UFS driver treats `-ENODEV` as a fatal error, completely failing the UFS probe.
--

commit 9f42720f6440c4701f3e9fd798297a81e20c12ba
Author: Abel Vesa <abel.vesa@oss.qualcomm.com>

arm64: dts: qcom: sm8650: Disable Inline Crypto Engine by default

This commit disables the Inline Crypto Engine (ICE) by default in the SoC
DTSI to prevent the UFS_PHY_GDSC from remaining enabled while the device is
idle. The ICE node is then explicitly enabled in the board-specific DTS
files that use it.

> diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
> index b679fd8afb7d5..384aa2203dfa3 100644
> --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
> @@ -4142,6 +4142,8 @@ ice: crypto@1d88000 {
>  			clock-names = "core",
>  				      "iface";
>  			power-domains = <&gcc UFS_PHY_GDSC>;
> +
> +			status = "disabled";

[Severity: High]
Does disabling the ICE node by default break the UFS controller probe on boards
that do not explicitly re-enable it?

The ufs_mem_hc node retains the qcom,ice = <&ice>; property, so
of_parse_phandle() still finds the node. However, since the node is now disabled
by default, no platform device is created for it. 

When the UFS driver probes, of_qcom_ice_get() fails to find the platform device:

drivers/soc/qcom/ice.c:of_qcom_ice_get() {
    ...
	if (!pdev) {
		dev_err(dev, "Cannot find device node %s\n", node->name);
		return ERR_PTR(-ENODEV);
	}
    ...
}

This returns -ENODEV, which is then treated as a fatal error by the UFS driver
instead of a graceful fallback:

drivers/ufs/host/ufs-qcom.c:ufs_qcom_ice_init() {
    ...
	if (IS_ERR(ice)) {
		if (ice != ERR_PTR(-EOPNOTSUPP))
			return PTR_ERR(ice);

		dev_warn(dev, "Disabling inline encryption support\n");
		return 0;
	}
    ...
}

Because the driver only falls back gracefully on -EOPNOTSUPP, receiving -ENODEV
causes the entire UFS probe to fail. Could this lead to an unbootable system for
downstream or future boards that rely on the default DTSI configuration if their
root filesystem is on UFS?

>  		};
>  
>  		cryptobam: dma-controller@1dc4000 {

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260828-b4-dts-qcom-disable-ice-by-default-v1-0-1d6e0c2f5a69@oss.qualcomm.com?part=3

Re: [PATCH 02/11] arm64: dts: qcom: sm8450: Disable Inline Crypto Engine by default

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Setting the Inline Crypto Engine (ICE) node status to "disabled" by default breaks UFS controller probing for out-of-tree boards and fails to resolve the power leak for boards using ICE.
--

commit d9ad1358857797b30ecd80f68a27f70909a989e9
Author: Abel Vesa <abel.vesa@oss.qualcomm.com>

arm64: dts: qcom: sm8450: Disable Inline Crypto Engine by default

The Inline Crypto Engine (ICE) is attached to the UFS_PHY_GDSC, and the
driver currently lacks runtime PM support, leaving the GDSC enabled during
idle periods. This commit disables the ICE node in the SoC DTSI and re-enables
it in board DTS files to avoid the power leak on boards where it is unused.

> diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
> index b8793482b1815..6f9d5a87f1c4c 100644
> --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
> @@ -5370,6 +5370,8 @@ ice: crypto@1d88000 {
>  			clock-names = "core",
>  				      "iface";
>  			power-domains = <&gcc UFS_PHY_GDSC>;
> +
> +			status = "disabled";

[Severity: High]
Does disabling the ICE node by default create a configuration trap for
downstream boards inheriting the UFS phandle?

The ufs_mem_hc node in sm8450.dtsi retains the qcom,ice = <&ice>; property.
If a board enables UFS but does not explicitly enable ICE, the ICE node
remains disabled.

Because of_qcom_ice_get() doesn't check of_device_is_available(), a disabled
node results in -ENODEV instead of -EOPNOTSUPP:

drivers/soc/qcom/ice.c:of_qcom_ice_get() {
...
	pdev = of_find_device_by_node(node);
	if (!pdev) {
		dev_err(dev, "Cannot find device node %s\n", node->name);
		return ERR_PTR(-ENODEV);
	}
...
}

This error propagates to ufs_qcom_ice_init() where it is treated as fatal:

drivers/ufs/host/ufs-qcom.c:ufs_qcom_ice_init() {
...
	ice = devm_of_qcom_ice_get(dev);
	if (IS_ERR(ice)) {
		if (ice != ERR_PTR(-EOPNOTSUPP))
			return PTR_ERR(ice);
...
}

Since -ENODEV is not handled like -EOPNOTSUPP, this completely aborts the UFS
initialization, leading to a fatal controller probe failure. Will any
downstream board utilizing this DTSI without overriding the newly introduced
ICE disablement fail to boot on this kernel?

Furthermore, for boards that do enable ICE, does the GDSC power leak persist
since the qcom-ice driver lacks runtime PM support?

>  		};
>  
>  		cryptobam: dma-controller@1dc4000 {

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260828-b4-dts-qcom-disable-ice-by-default-v1-0-1d6e0c2f5a69@oss.qualcomm.com?part=2

Re: [PATCH 09/11] arm64: dts: qcom: kodiak: Disable Inline Crypto Engine by default

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:

Pre-existing issues:
- [High] UFS host controller probe fails completely if the attached ICE device is marked as disabled in the device tree.
--

commit d5ed75549915409ece5532bca3c5d000fa3bc031
Author: Abel Vesa <abel.vesa@oss.qualcomm.com>

arm64: dts: qcom: kodiak: Disable Inline Crypto Engine by default
    
Disable the Inline Crypto Engine by default in the SoC DTSI and enable
it only in board DTS files that use it. This prevents the UFS_PHY_GDSC
from remaining enabled while the device is idle on boards with no consumers.

> diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi
> index f2da3706d5c88..ffbf037b38386 100644
> --- a/arch/arm64/boot/dts/qcom/kodiak.dtsi
> +++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi
> @@ -2586,6 +2586,8 @@ ice: crypto@1d88000 {
>  			clock-names = "core",
>  				      "iface";
>  			power-domains = <&gcc GCC_UFS_PHY_GDSC>;
> +
> +			status = "disabled";

[Severity: High]
This is a pre-existing issue, but does disabling the ICE node by default cause
the UFS probe to fail completely for any board that leaves it disabled?

When a board's device tree disables the ICE node without deleting the qcom,ice
property from the UFS node, the ICE node is not populated as a platform
device. This causes of_find_device_by_node() to return NULL:

drivers/soc/qcom/ice.c:of_qcom_ice_get() {
	pdev = of_find_device_by_node(node);
	if (!pdev) {
		dev_err(dev, "Cannot find device node %s\n", node->name);
		return ERR_PTR(-ENODEV);
	}
...
}

This error is then returned to the UFS probe:

drivers/ufs/host/ufs-qcom.c:ufs_qcom_ice_init() {
	ice = devm_of_qcom_ice_get(dev);
	if (IS_ERR(ice)) {
		if (ice != ERR_PTR(-EOPNOTSUPP))
			return PTR_ERR(ice);

		dev_warn(dev, "Disabling inline encryption support\n");
		return 0;
	}
...
}

Because ufs_qcom_ice_init() treats -ENODEV as a fatal error rather than
gracefully falling back to disabled hardware encryption, the entire UFS driver
probe aborts and storage fails to initialize.

>  		};
>  
>  		cryptobam: dma-controller@1dc4000 {

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260828-b4-dts-qcom-disable-ice-by-default-v1-0-1d6e0c2f5a69@oss.qualcomm.com?part=9

Re: [PATCH 00/11] arm64: dts: qcom: Disable Inline Crypto Engine by default accross all SoCs

[Abel Vesa]

On 26-08-28 18:17:52, Kuldeep Singh wrote:
> 
> 
> On 28-08-2026 18:07, Abel Vesa wrote:
> > Since UFS_PHY_GDSC was attached to the Inline Crypto Engine and the driver
> > does not currently do runtime PM, the GDSC remains enabled while the
> > device is idle, even on boards where there are no consumers.
> > 
> > I'm working on getting runtime PM enabled in the ICE driver, but the
> > node should not be enabled on such boards anyways.
> > 
> > So disable the Inline Crypto Engine by default in the SoC DTSI and enable
> > it only in board DTS files that use it.
> > 
> > Do this accross the board, for all SoCs that have dedicated ICE DT node.
> > 
> > Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
> 
> Kindly check discussion happenend before on adding such implementation.
> 
> https://lore.kernel.org/all/56ab63c3-4288-45f7-bfea-d40046437a9f@oss.qualcomm.com/
> 
> The idea is to enable ice as default and independent of storage media
> and enable runtime PM enabled.

Yeah, just replied to that thread right now.