Re: [PATCH net-next 5/9] net: stmmac: qcom-ethqos: fix RGMII_ID mode to use DLL bypass

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] ethqos_set_clk_tx_rate() fails to double the TX clock rate for RGMII_RXID and RGMII_TXID at 10M/100M speeds, breaking MAC-side delay hardware.
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commit 0e659e67f69f5c33161dd3e01478dcbdaa1c7d6f
Author: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>

net: stmmac: qcom-ethqos: fix RGMII_ID mode to use DLL bypass

This commit powers down the DLL and sets DDR bypass mode for RGMII_ID,
and introduces ethqos_rgmii_id_macro_init() to program the IO_MACRO. It
also updates ethqos_set_clk_tx_rate() to skip doubling the clock rate for
100M/10M in bypass mode.

> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
[ ... ]
> @@ -183,7 +186,15 @@ static int ethqos_set_clk_tx_rate(void *bsp_priv, struct clk *clk_tx_i,
>  	if (rate < 0)
>  		return rate;
>  
> -	return clk_set_rate(ethqos->link_clk, rate * 2);
> +	/* Clock Rate Requirements:
> +	 * MAC added delay: 250/50/5 Mhz for 1G/100M/10M
> +	 * No MAC delay (DLL bypass): 250/25/2.5 Mhz for 1G/100M/10M
> +	 */
> +	if (ethqos->phy_mode == PHY_INTERFACE_MODE_RGMII ||
> +	    speed == SPEED_1000)
> +		rate *= 2;

[Severity: High]
Does this conditional exclude PHY_INTERFACE_MODE_RGMII_TXID and
PHY_INTERFACE_MODE_RGMII_RXID from having their TX clock rate doubled at 10M
and 100M speeds?

If the device tree configures the PHY mode as rgmii-txid or rgmii-rxid,
those modes fall through to the non-bypass DLL initialization path in
ethqos_fix_mac_speed_rgmii().

Since this logic only explicitly checks for PHY_INTERFACE_MODE_RGMII, will
it result in the MAC DLL receiving half the expected clock frequency? Could
this break ethernet connectivity or cause data corruption for these
configurations at 10M and 100M?

> +
> +	return clk_set_rate(ethqos->link_clk, rate);
>  }

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Sashiko AI review · https://sashiko.dev/#/patchset/20260904-shikra_ethernet-v1-0-a50765996035@oss.qualcomm.com?part=5