Re: [PATCH net-next 9/9] net: stmmac: qcom-ethqos: add Shikra EMAC support

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The PTP clock rate (`clk_ptp_rate`) is captured from the `stmmaceth` clock before its rate is updated to 120MHz, leading to incorrect PTP timestamp calculations if `ptp_ref` is omitted from the device tree.
--

commit 6df66dc49bfcbb8fca628cf4fea13cac0f605200
Author: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>

net: stmmac: qcom-ethqos: add Shikra EMAC support
    
Shikra integrates two Qualcomm ETHQOS controllers based on the Synopsys
GMAC IP, similar to previous platforms.  Register qcom,shikra-ethqos
backed by a new shikra_data descriptor that enables the three NOC clocks
required for DMA memory access (axi-noc, pcie-tile-axi-noc, stmmaceth)
all at 120 MHz, and the 36-bit DMA address width.

> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
> index a31541506a4c9..f96680456472d 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
> @@ -328,6 +328,36 @@ static const struct ethqos_emac_driver_data emac_v4_0_0_data = {
>  	},
>  };
>  
> +static const struct ethqos_noc_clk_cfg shikra_noc_clks[] = {
> +	{ "axi-noc", 120000000 },
> +	{ "pcie-tile-axi-noc", 120000000 },
> +	{ "stmmaceth", 120000000 },
> +};

[Severity: Medium]
Since the stmmaceth clock frequency is being set to 120MHz here, could this
lead to an incorrect PTP clock rate if the ptp_ref clock is omitted from
the device tree?

In qcom_ethqos_probe(), devm_stmmac_probe_config_dt() is called before the
noc_clks are initialized. If ptp_ref is missing, the driver falls back to
caching the main clock's initial rate:

stmmac_platform.c:stmmac_probe_config_dt() {
	...
	plat->clk_ptp_ref = devm_clk_get(&pdev->dev, "ptp_ref");
	if (IS_ERR(plat->clk_ptp_ref)) {
		plat->clk_ptp_rate = clk_get_rate(plat->stmmac_clk);
		plat->clk_ptp_ref = NULL;
	...
}

Later in qcom_ethqos_probe(), the noc_clks configuration updates the stmmaceth
clock to 120MHz. However, ethqos_ptp_clk_freq_config() returns early when
clk_ptp_ref is NULL, leaving the cached clk_ptp_rate at its original
boot-time value rather than 120MHz.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260904-shikra_ethernet-v1-0-a50765996035@oss.qualcomm.com?part=9