From: Petko Manolov <petko.manolov@konsulko.com>
To: linux-kernel@vger.kernel.org
Cc: devicetree@vger.kernel.org, robh@kernel.org, krzk+dt@kernel.org,
conor+dt@kernel.org, dinguyen@kernel.org,
Petko Manolov <petko.manolov@konsulko.com>
Subject: [PATCH v2 0/1] ARM: dts: draeger: Add socfpga devicetree for Draeger's M48 board.
Date: Tue, 8 Sep 2026 14:09:59 +0300 [thread overview]
Message-ID: <20260908111011.960876-1-petko.manolov@konsulko.com> (raw)
Adding the device trees for “Dräger M48 on NXP i.MX6 (Q) and Intel/Altera
SoCFPGA Cyclone V” board variant. It has both (the SoC and FPGA) on the same
carrier and they are cross-monitoring each other.
This is the SoCFPGA devicetree part.
Petko Manolov (1):
ARM: dts: draeger: Add socfpga devicetree for Draeger's M48 board.
.../devicetree/bindings/arm/altera.yaml | 1 +
arch/arm/boot/dts/intel/socfpga/Makefile | 1 +
.../socfpga/socfpga_cyclone5_draeger_m48.dts | 130 ++++++++++++++++++
3 files changed, 132 insertions(+)
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_draeger_m48.dts
--
2.47.3
next reply other threads:[~2026-09-08 11:10 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-08 11:09 Petko Manolov [this message]
2026-09-08 11:10 ` [PATCH v2 1/1] ARM: dts: draeger: Add socfpga devicetree for Draeger's M48 board Petko Manolov
2026-09-08 11:17 ` sashiko-bot
2026-09-09 6:36 ` Krzysztof Kozlowski
2026-09-09 6:50 ` Petko Manolov
2026-09-09 6:52 ` Krzysztof Kozlowski
2026-09-09 10:07 ` Petko Manolov
2026-09-09 10:14 ` Krzysztof Kozlowski
2026-09-09 11:16 ` Petko Manolov
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