[PATCH 0/5] Add ADC support for RZ/G3L TSU

[PATCH 0/5] Add ADC support for RZ/G3L TSU

[Biju Das]

On the RZ/G3L, ADC1 is connected to the TSU, whereas it is connected to
ADC0 on the RZ/G3S. There are no ADCR0 to ADCR7 registers on the RZ/G3L,
and the INTEN bits in the ADINT registers are also different. Add ADC
support for the TSU (a.k.a. ADC1).

The SoC dtsi patch depends on [1]
[1] https://lore.kernel.org/all/20260911131629.111564-2-biju.das.jz@bp.renesas.com/

Biju Das (5):
  dt-bindings: iio: adc: renesas,rzg2l-adc: Make '#io-channel-cells'
    required for R9A08G045
  dt-bindings: iio: adc: renesas,rzg2l-adc: Document RZ/G3L ADC for TSU
  iio: adc: rzg2l_adc: Add RZ/G3L ADC support for TSU
  clk: renesas: r9a08g046: Add TSU,ADC1 clocks and reset
  arm64: dts: renesas: r9a08g046: Enable TSU

 .../bindings/iio/adc/renesas,rzg2l-adc.yaml   | 28 +++++++-
 arch/arm64/boot/dts/renesas/r9a08g046.dtsi    | 66 +++++++++++++++++++
 drivers/clk/renesas/r9a08g046-cpg.c           | 10 +++
 drivers/iio/adc/rzg2l_adc.c                   |  9 +++
 4 files changed, 112 insertions(+), 1 deletion(-)

-- 
2.43.0

[PATCH 1/5] dt-bindings: iio: adc: renesas,rzg2l-adc: Make '#io-channel-cells' required for R9A08G045

[Biju Das]

Add a conditional schema constraint so that '#io-channel-cells' is
required when the compatible string is "renesas,r9a08g045-adc".

This is required because the R9A08G045 ADC serves as an IIO provider,
allowing external hardware consumer nodes (such as the TSU) to reference
its individual channels. The '#io-channel-cells' property must be present
so consumers can correctly specify the channel index in their 'io-channels'
phandle property.

Fixes: a3152e5c742c ("dt-bindings: thermal: r9a08g045-tsu: Document the TSU unit")
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 .../devicetree/bindings/iio/adc/renesas,rzg2l-adc.yaml   | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/Documentation/devicetree/bindings/iio/adc/renesas,rzg2l-adc.yaml b/Documentation/devicetree/bindings/iio/adc/renesas,rzg2l-adc.yaml
index 40341d541726..60fbc05acc1a 100644
--- a/Documentation/devicetree/bindings/iio/adc/renesas,rzg2l-adc.yaml
+++ b/Documentation/devicetree/bindings/iio/adc/renesas,rzg2l-adc.yaml
@@ -121,6 +121,15 @@ allOf:
             reg:
               maximum: 7
 
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: renesas,r9a08g045-adc
+    then:
+      required:
+        - '#io-channel-cells'
+
 additionalProperties: false
 
 examples:
-- 
2.43.0

[PATCH 2/5] dt-bindings: iio: adc: renesas,rzg2l-adc: Document RZ/G3L ADC for TSU

[Biju Das]

Add the renesas,r9a08g046-adc1 compatible string for the ADC1
instance on RZ/G3L, which is dedicated to the on-chip TSU (thermal
sensor unit). Unlike the other ADC instances, this one only exposes
a single channel (channel@8), so restrict the allowed channel nodes
accordingly.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 .../bindings/iio/adc/renesas,rzg2l-adc.yaml   | 21 +++++++++++++++++--
 1 file changed, 19 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/iio/adc/renesas,rzg2l-adc.yaml b/Documentation/devicetree/bindings/iio/adc/renesas,rzg2l-adc.yaml
index 60fbc05acc1a..f4705d5ca543 100644
--- a/Documentation/devicetree/bindings/iio/adc/renesas,rzg2l-adc.yaml
+++ b/Documentation/devicetree/bindings/iio/adc/renesas,rzg2l-adc.yaml
@@ -25,7 +25,9 @@ properties:
               - renesas,r9a07g054-adc   # RZ/V2L
           - const: renesas,rzg2l-adc
       - items:
-          - const: renesas,r9a08g045-adc  # RZ/G3S
+          - enum:
+              - renesas,r9a08g045-adc   # RZ/G3S
+              - renesas,r9a08g046-adc1  # RZ/G3L ADC for TSU
 
   reg:
     maxItems: 1
@@ -125,7 +127,22 @@ allOf:
       properties:
         compatible:
           contains:
-            const: renesas,r9a08g045-adc
+            const: renesas,r9a08g046-adc1
+    then:
+      patternProperties:
+        "^channel@[0-7]$": false
+        "^channel@[8]$":
+          properties:
+            reg:
+              const: 8
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - renesas,r9a08g045-adc
+              - renesas,r9a08g046-adc1
     then:
       required:
         - '#io-channel-cells'
-- 
2.43.0

[PATCH 5/5] arm64: dts: renesas: r9a08g046: Enable TSU

[Biju Das]

Add #cooling-cells to the CPU nodes, and describe the ADC1 (used
exclusively by the TSU) and TSU nodes along with a CPU thermal zone
using passive and critical trip points, with CPU frequency cooling
maps for thermal mitigation.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r9a08g046.dtsi | 66 ++++++++++++++++++++++
 1 file changed, 66 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
index 53e68b1c3258..29ce1ab2a57f 100644
--- a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
@@ -179,6 +179,7 @@ cpu0: cpu@0 {
 			next-level-cache = <&L3_CA55>;
 			enable-method = "psci";
 			clocks = <&cpg CPG_CORE R9A08G046_CLK_IC0>;
+			#cooling-cells = <2>;
 			operating-points-v2 = <&cluster0_opp>;
 		};
 
@@ -189,6 +190,7 @@ cpu1: cpu@100 {
 			next-level-cache = <&L3_CA55>;
 			enable-method = "psci";
 			clocks = <&cpg CPG_CORE R9A08G046_CLK_IC1>;
+			#cooling-cells = <2>;
 			operating-points-v2 = <&cluster0_opp>;
 		};
 
@@ -199,6 +201,7 @@ cpu2: cpu@200 {
 			next-level-cache = <&L3_CA55>;
 			enable-method = "psci";
 			clocks = <&cpg CPG_CORE R9A08G046_CLK_IC2>;
+			#cooling-cells = <2>;
 			operating-points-v2 = <&cluster0_opp>;
 		};
 
@@ -209,6 +212,7 @@ cpu3: cpu@300 {
 			next-level-cache = <&L3_CA55>;
 			enable-method = "psci";
 			clocks = <&cpg CPG_CORE R9A08G046_CLK_IC3>;
+			#cooling-cells = <2>;
 			operating-points-v2 = <&cluster0_opp>;
 		};
 
@@ -374,6 +378,37 @@ scif5: serial@1004e000 {
 			status = "disabled";
 		};
 
+		adc1: adc@108c0000 {
+			compatible = "renesas,r9a08g046-adc1";
+			reg = <0 0x108c0000 0 0x10000>;
+			interrupts = <GIC_SPI 378 IRQ_TYPE_EDGE_RISING>;
+			clocks = <&cpg CPG_MOD R9A08G046_ADC1_ADCLK>,
+				 <&cpg CPG_MOD R9A08G046_ADC1_PCLK>;
+			clock-names = "adclk", "pclk";
+			resets = <&cpg R9A08G046_ADC1_PRESETN>,
+				 <&cpg R9A08G046_ADC1_ADRST_N>;
+			reset-names = "presetn", "adrst-n";
+			power-domains = <&cpg>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			#io-channel-cells = <1>;
+
+			channel@8 {
+				reg = <8>;
+			};
+		};
+
+		tsu: thermal@108d0000 {
+			compatible = "renesas,r9a08g046-tsu";
+			reg = <0 0x108d0000 0 0x10000>;
+			clocks = <&cpg CPG_MOD R9A08G046_TSU_PCLK>;
+			resets = <&cpg R9A08G046_TSU_PRESETN>;
+			power-domains = <&cpg>;
+			#thermal-sensor-cells = <0>;
+			io-channels = <&adc1 0>;
+			io-channel-names = "tsu";
+		};
+
 		i2c0: i2c@100ae000 {
 			compatible = "renesas,riic-r9a08g046", "renesas,riic-r9a09g057";
 			reg = <0 0x100ae000 0 0x400>;
@@ -1570,6 +1605,37 @@ stmmac_axi_setup: stmmac-axi-config {
 		snps,blen = <16 8 4 0 0 0 0>;
 	};
 
+	thermal-zones {
+		cpu-thermal {
+			polling-delay = <1000>;
+			polling-delay-passive = <250>;
+			thermal-sensors = <&tsu>;
+
+			cooling-maps {
+				map0 {
+					trip = <&target>;
+					cooling-device = <&cpu0 0 3>, <&cpu1 0 3>,
+							 <&cpu2 0 3>, <&cpu3 0 3>;
+					contribution = <1024>;
+				};
+			};
+
+			trips {
+				sensor_crit: sensor-crit {
+					temperature = <120000>;
+					hysteresis = <1000>;
+					type = "critical";
+				};
+
+				target: trip-point {
+					temperature = <95000>;
+					hysteresis = <1000>;
+					type = "passive";
+				};
+			};
+		};
+	};
+
 	timer {
 		compatible = "arm,armv8-timer";
 		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
-- 
2.43.0

Re: [PATCH 5/5] arm64: dts: renesas: r9a08g046: Enable TSU

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] The TSU device tree node specifies a compatible string without a fallback, and no driver supports this string, breaking thermal mitigation.
--

commit c0610eba9fadf799fcb3bc01e18ea5baeb813435
Author: Biju Das <biju.das.jz@bp.renesas.com>

arm64: dts: renesas: r9a08g046: Enable TSU

Add #cooling-cells to the CPU nodes, and describe the ADC1 (used
exclusively by the TSU) and TSU nodes along with a CPU thermal zone
using passive and critical trip points, with CPU frequency cooling
maps for thermal mitigation.

> diff --git a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
> index c63a857f0e5b0..a2f6718c0043a 100644
> --- a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
[ ... ]
> @@ -270,6 +274,37 @@ scif5: serial@1004e000 {
>  			status = "disabled";
>  		};
>  
[ ... ]
> +		tsu: thermal@108d0000 {
> +			compatible = "renesas,r9a08g046-tsu";
[Severity: High]
Will the tsu node probe successfully with this compatible string?

Looking at the tsu node in arch/arm64/boot/dts/renesas/r9a08g046.dtsi, it
appears there is no thermal driver that matches renesas,r9a08g046-tsu, and
this node does not provide a generic fallback like renesas,rzg2l-tsu.

If the device cannot probe during system initialization, the cpu-thermal zone
will fail to attach to its thermal sensor and defer probing indefinitely. Could
this silently disable thermal mitigation entirely?

> +			reg = <0 0x108d0000 0 0x10000>;
> +			clocks = <&cpg CPG_MOD R9A08G046_TSU_PCLK>;

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260911133653.115553-1-biju.das.jz@bp.renesas.com?part=5

Re: [PATCH 0/5] Add ADC support for RZ/G3L TSU

[Jonathan Cameron]

On Fri, 11 Sep 2026 14:36:43 +0100
Biju Das <biju.das.jz@bp.renesas.com> wrote:

> On the RZ/G3L, ADC1 is connected to the TSU, whereas it is connected to
> ADC0 on the RZ/G3S. There are no ADCR0 to ADCR7 registers on the RZ/G3L,
> and the INTEN bits in the ADINT registers are also different. Add ADC
> support for the TSU (a.k.a. ADC1).

Too many TLA.  What is TSU?  In general write this for someone who
is not really that familiar with the particular part!

> 
> The SoC dtsi patch depends on [1]
> [1] https://lore.kernel.org/all/20260911131629.111564-2-biju.das.jz@bp.renesas.com/
> 
> Biju Das (5):
>   dt-bindings: iio: adc: renesas,rzg2l-adc: Make '#io-channel-cells'
>     required for R9A08G045
>   dt-bindings: iio: adc: renesas,rzg2l-adc: Document RZ/G3L ADC for TSU
>   iio: adc: rzg2l_adc: Add RZ/G3L ADC support for TSU
>   clk: renesas: r9a08g046: Add TSU,ADC1 clocks and reset
>   arm64: dts: renesas: r9a08g046: Enable TSU
> 
>  .../bindings/iio/adc/renesas,rzg2l-adc.yaml   | 28 +++++++-
>  arch/arm64/boot/dts/renesas/r9a08g046.dtsi    | 66 +++++++++++++++++++
>  drivers/clk/renesas/r9a08g046-cpg.c           | 10 +++
>  drivers/iio/adc/rzg2l_adc.c                   |  9 +++
>  4 files changed, 112 insertions(+), 1 deletion(-)
>