Re: [PATCH v6 2/4] arm64: dts: qcom: pm8005: Add temp alarm node

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] The critical trip temperature of 145000 mC exceeds the hardware's maximum Stage 2 shutdown threshold, causing a premature hard-power cut that bypasses OS software shutdown.
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commit 88b914c28016cf188fecbd155d9b9942de82bce0
Author: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>

arm64: dts: qcom: pm8005: Add temp alarm node
    
This commit adds a temperature alarm node along with a thermal zone used
for PMIC thermal mitigation on the PM8005.
    
> diff --git a/arch/arm64/boot/dts/qcom/pm8005.dtsi b/arch/arm64/boot/dts/qcom/pm8005.dtsi
> index 0f0ab2da83055..ce31a85450200 100644
> --- a/arch/arm64/boot/dts/qcom/pm8005.dtsi
> +++ b/arch/arm64/boot/dts/qcom/pm8005.dtsi
[ ... ]
> +				pm8005_trip1: trip1 {
> +					temperature = <125000>;
> +					hysteresis = <0>;
> +					type = "hot";
> +				};
> +
> +				pm8005_trip2: trip2 {
> +					temperature = <145000>;
> +					hysteresis = <0>;
> +					type = "critical";
> +				};

[Severity: High]
Does setting this temperature to 145000 mC exceed the hardware's maximum
Stage 2 shutdown threshold (typically 125000 mC or 140000 mC depending on the
generation)?

If this threshold is physically unattainable by the hardware without an ADC,
could this force an early, ungraceful hardware power cut before the OS is
able to reach the thermal framework's graceful shutdown procedure?

[ ... ]
>  &spmi_bus {
>  	pm8005_lsid0: pmic@4 {
>  		compatible = "qcom,pm8005", "qcom,spmi-pmic";
> @@ -11,6 +39,13 @@ pm8005_lsid0: pmic@4 {
>  		#address-cells = <1>;
>  		#size-cells = <0>;
>  
> +		pm8005_tz: temp-alarm@2400 {
> +			compatible = "qcom,spmi-temp-alarm";
> +			reg = <0x2400>;
> +			interrupts = <0x4 0x24 0x0 IRQ_TYPE_EDGE_BOTH>;
> +			#thermal-sensor-cells = <0>;
> +		};

[Severity: High]
Because there is no io-channels property defined here, it looks like the
qcom-spmi-temp-alarm driver will have to rely on the PMIC's internal hardware
comparators instead of an ADC.

When the driver attempts to configure the 145000 mC critical trip point from
above, will it find that it exceeds the hardware's maximum threshold, cap it
at the hardware maximum, and leave SHUTDOWN_CTRL1_OVERRIDE_STAGE2 disabled?

If so, would the PMIC abruptly power off when the temperature reaches the
lower Stage 2 hardware threshold? This bypasses the OS thermal framework's
graceful shutdown and can potentially lead to filesystem corruption on
overheating. Should an io-channels property be provided here to properly
delegate the critical trip to software?

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Sashiko AI review · https://sashiko.dev/#/patchset/20260911-shikra_adc_support-v6-0-e4b2da5cd55c@oss.qualcomm.com?part=2