Re: [PATCH v6 3/4] arm64: dts: qcom: Add PMIC thermal support for Shikra CQ2390M SoM platform

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
- [High] Hardware Configuration / Pin Muxing Error for ADC channels
- [High] Missing `polling-delay` in thermal zones disables thermal mitigation
- [Low] Undocumented and incomplete ADC channels (chgr_skin and gnss_therm)
--

commit 98fcf70dd02eac02e053cdcbc6ca2e2a21056370
Author: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>

arm64: dts: qcom: Add PMIC thermal support for Shikra CQ2390M SoM platform

Add ADC channels for pa, quiet and msm thermistors along with
their ADC thermal bridge nodes and thermal zones for PMIC
thermal mitigation.

> diff --git a/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi b/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi
> index fde7fc035bf5d..c7fb71675b793 100644
> --- a/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi
> +++ b/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi
[ ... ]
> @@ -32,6 +33,68 @@ key-volume-up {
[ ... ]
> +	thermal-zones {
> +		sys-1-thermal {
> +			polling-delay-passive = <2000>;
> +			thermal-sensors = <&pa_therm_bridge>;

[Severity: High]
Does this thermal zone require a polling-delay property?

When polling-delay is omitted, the Linux thermal framework disables baseline
polling timers. The generic-adc-thermal bridges over SPMI ADCs do not seem to
generate temperature threshold interrupts.

Without a polling-delay, it appears the temperature is never read and these
trips will not trigger.

This question also applies to sys-2-thermal and sys-3-thermal.

> +
> +			trips {
[ ... ]
> @@ -69,7 +132,64 @@ vreg_pmu_ch1: ldo4 {
>  	};
>  };
>  
> +&pm4125_adc {
> +	pinctrl-0 = <&pm4125_adc_gpio5_default>, <&pm4125_adc_gpio6_default>;
> +	pinctrl-names = "default";

[Severity: High]
Is this pin muxing correct for the channels defined below?

This assigns pinctrl-0 to gpio5 and gpio6, but the chgr_skin and
gnss_therm channels added below use ADC5_GPIO3_100K_PU and
ADC5_GPIO4_100K_PU, which map to physical GPIO3 and GPIO4.

If the wrong GPIO pins are set to high-impedance while the actual pins used
for ADC are left unconfigured, could this corrupt ADC readings or cause
unwanted power draw?

[ ... ]
> +
> +	channel@54 {
> +		reg = <ADC5_GPIO3_100K_PU>;
> +		label = "chgr_skin";
> +		qcom,ratiometric;
> +		qcom,hw-settle-time = <200>;
> +		qcom,pre-scaling = <1 1>;
> +	};
> +
> +	channel@55 {
> +		reg = <ADC5_GPIO4_100K_PU>;
> +		label = "gnss_therm";
> +		qcom,ratiometric;
> +		qcom,hw-settle-time = <200>;
> +		qcom,pre-scaling = <1 1>;
> +	};

[Severity: Low]
Are these two ADC channels intended to be included in this commit?

They are not mentioned in the commit message and are not connected to any
thermal zones, which might suggest they were accidentally copied over along
with the GPIO5/GPIO6 pin muxing defined above.

> +};

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260911-shikra_adc_support-v6-0-e4b2da5cd55c@oss.qualcomm.com?part=3