From: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
To: Bryan O'Donoghue <bod@kernel.org>,
Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>,
Loic Poulain <loic.poulain@oss.qualcomm.com>,
Mauro Carvalho Chehab <mchehab@kernel.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
Subject: [PATCH 6/6] media: qcom: camss: Add support for nord camss
Date: Tue, 15 Sep 2026 17:34:16 +0800 [thread overview]
Message-ID: <20260915-nord-v1-6-20db41a7f1ff@oss.qualcomm.com> (raw)
In-Reply-To: <20260915-nord-v1-0-20db41a7f1ff@oss.qualcomm.com>
Add support for the camera subsystem on the Qualcomm Nord platform.
Enumerate the module-level resources (clocks, register regions,
interrupts) and the bus bandwidth votes, and wire up the compatible.
Nord exposes 3 TPG, 3 CSID plus 10 CSID Lite (driven by csid_ops_900)
and 3 VFE plus 10 VFE Lite (driven by vfe_ops_gen4 with the VFE 900
variant).
Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
---
drivers/media/platform/qcom/camss/camss-vfe.c | 2 +
drivers/media/platform/qcom/camss/camss.c | 602 ++++++++++++++++++++++++++
2 files changed, 604 insertions(+)
diff --git a/drivers/media/platform/qcom/camss/camss-vfe.c b/drivers/media/platform/qcom/camss/camss-vfe.c
index 11f616ae035c1814e21ae2a01c5e1131022da236..d5077c502f04cf4e7677e86da1befeca0033e339 100644
--- a/drivers/media/platform/qcom/camss/camss-vfe.c
+++ b/drivers/media/platform/qcom/camss/camss-vfe.c
@@ -353,6 +353,7 @@ static u32 vfe_src_pad_code(struct vfe_line *line, u32 sink_code,
case CAMSS_8550:
case CAMSS_8650:
case CAMSS_8775P:
+ case CAMSS_NORD:
case CAMSS_X1E80100:
switch (sink_code) {
case MEDIA_BUS_FMT_YUYV8_1X16:
@@ -2016,6 +2017,7 @@ static int vfe_bpl_align_rdi(struct vfe_device *vfe)
case CAMSS_8550:
case CAMSS_8650:
case CAMSS_8775P:
+ case CAMSS_NORD:
case CAMSS_X1E80100:
ret = 16;
break;
diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c
index 2123f6388e3d7eafe669efd6b033e22d8eb5cf79..5899f64a3c0a2f7f6829d73636aae4deda42aaea 100644
--- a/drivers/media/platform/qcom/camss/camss.c
+++ b/drivers/media/platform/qcom/camss/camss.c
@@ -4536,6 +4536,594 @@ static const struct resources_wrapper csid_wrapper_res_x1e80100 = {
.reg = "csid_wrapper",
};
+static const struct camss_subdev_resources tpg_res_nord[] = {
+ /* TPG0 */
+ {
+ .clock = { "top_ahb", "tpg_csiphy_rx" },
+ .clock_rate = { { 0 },
+ { 400000000, 480000000 } },
+ .reg = { "csitpg0" },
+ .tpg = {
+ .lane_cnt = 4,
+ .formats = &tpg_formats_gen1,
+ .hw_ops = &tpg_ops_gen1
+ }
+ },
+ /* TPG1 */
+ {
+ .clock = { "top_ahb", "tpg_csiphy_rx" },
+ .clock_rate = { { 0 },
+ { 400000000, 480000000 } },
+ .reg = { "csitpg1" },
+ .tpg = {
+ .lane_cnt = 4,
+ .formats = &tpg_formats_gen1,
+ .hw_ops = &tpg_ops_gen1
+ }
+ },
+ /* TPG2 */
+ {
+ .clock = { "top_ahb", "tpg_csiphy_rx" },
+ .clock_rate = { { 0 },
+ { 400000000, 480000000 } },
+ .reg = { "csitpg2" },
+ .tpg = {
+ .lane_cnt = 4,
+ .formats = &tpg_formats_gen1,
+ .hw_ops = &tpg_ops_gen1
+ }
+ },
+};
+
+static const struct camss_subdev_resources csid_res_nord[] = {
+ /* CSID0 */
+ {
+ .clock = { "csid", "csid_csiphy_rx", "top_ahb" },
+ .clock_rate = { { 400000000, 480000000 },
+ { 400000000, 480000000 },
+ { 0 } },
+ .reg = { "csid0" },
+ .interrupt = { "csid0" },
+ .csid = {
+ .is_lite = false,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .hw_ops = &csid_ops_900,
+ .formats = &csid_formats_gen2
+ }
+ },
+ /* CSID1 */
+ {
+ .clock = { "csid", "csid_csiphy_rx", "top_ahb" },
+ .clock_rate = { { 400000000, 480000000 },
+ { 400000000, 480000000 },
+ { 0 } },
+ .reg = { "csid1" },
+ .interrupt = { "csid1" },
+ .csid = {
+ .is_lite = false,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .hw_ops = &csid_ops_900,
+ .formats = &csid_formats_gen2
+ }
+ },
+ /* CSID2 */
+ {
+ .clock = { "csid", "csid_csiphy_rx", "top_ahb" },
+ .clock_rate = { { 400000000, 480000000 },
+ { 400000000, 480000000 },
+ { 0 } },
+ .reg = { "csid2" },
+ .interrupt = { "csid2" },
+ .csid = {
+ .is_lite = false,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .hw_ops = &csid_ops_900,
+ .formats = &csid_formats_gen2
+ }
+ },
+ /* CSID_LITE0 */
+ {
+ .clock = { "vfe_lite_csid", "vfe_lite_cphy_rx", "top_ahb" },
+ .clock_rate = { { 400000000, 480000000 },
+ { 400000000, 480000000 },
+ { 0 } },
+ .reg = { "csid_lite0" },
+ .interrupt = { "csid_lite0" },
+ .csid = {
+ .is_lite = true,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .hw_ops = &csid_ops_900,
+ .formats = &csid_formats_gen2
+ }
+ },
+ /* CSID_LITE1 */
+ {
+ .clock = { "vfe_lite_csid", "vfe_lite_cphy_rx", "top_ahb" },
+ .clock_rate = { { 400000000, 480000000 },
+ { 400000000, 480000000 },
+ { 0 } },
+ .reg = { "csid_lite1" },
+ .interrupt = { "csid_lite1" },
+ .csid = {
+ .is_lite = true,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .hw_ops = &csid_ops_900,
+ .formats = &csid_formats_gen2
+ }
+ },
+ /* CSID_LITE2 */
+ {
+ .clock = { "vfe_lite_csid", "vfe_lite_cphy_rx", "top_ahb" },
+ .clock_rate = { { 400000000, 480000000 },
+ { 400000000, 480000000 },
+ { 0 } },
+ .reg = { "csid_lite2" },
+ .interrupt = { "csid_lite2" },
+ .csid = {
+ .is_lite = true,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .hw_ops = &csid_ops_900,
+ .formats = &csid_formats_gen2
+ }
+ },
+ /* CSID_LITE3 */
+ {
+ .clock = { "vfe_lite_csid", "vfe_lite_cphy_rx", "top_ahb" },
+ .clock_rate = { { 400000000, 480000000 },
+ { 400000000, 480000000 },
+ { 0 } },
+ .reg = { "csid_lite3" },
+ .interrupt = { "csid_lite3" },
+ .csid = {
+ .is_lite = true,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .hw_ops = &csid_ops_900,
+ .formats = &csid_formats_gen2
+ }
+ },
+ /* CSID_LITE4 */
+ {
+ .clock = { "vfe_lite_csid", "vfe_lite_cphy_rx", "top_ahb" },
+ .clock_rate = { { 400000000, 480000000 },
+ { 400000000, 480000000 },
+ { 0 } },
+ .reg = { "csid_lite4" },
+ .interrupt = { "csid_lite4" },
+ .csid = {
+ .is_lite = true,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .hw_ops = &csid_ops_900,
+ .formats = &csid_formats_gen2
+ }
+ },
+ /* CSID_LITE5 */
+ {
+ .clock = { "vfe_lite_csid", "vfe_lite_cphy_rx", "top_ahb" },
+ .clock_rate = { { 400000000, 480000000 },
+ { 400000000, 480000000 },
+ { 0 } },
+ .reg = { "csid_lite5" },
+ .interrupt = { "csid_lite5" },
+ .csid = {
+ .is_lite = true,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .hw_ops = &csid_ops_900,
+ .formats = &csid_formats_gen2
+ }
+ },
+ /* CSID_LITE6 */
+ {
+ .clock = { "vfe_lite_csid", "vfe_lite_cphy_rx", "top_ahb" },
+ .clock_rate = { { 400000000, 480000000 },
+ { 400000000, 480000000 },
+ { 0 } },
+ .reg = { "csid_lite6" },
+ .interrupt = { "csid_lite6" },
+ .csid = {
+ .is_lite = true,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .hw_ops = &csid_ops_900,
+ .formats = &csid_formats_gen2
+ }
+ },
+ /* CSID_LITE7 */
+ {
+ .clock = { "vfe_lite_csid", "vfe_lite_cphy_rx", "top_ahb" },
+ .clock_rate = { { 400000000, 480000000 },
+ { 400000000, 480000000 },
+ { 0 } },
+ .reg = { "csid_lite7" },
+ .interrupt = { "csid_lite7" },
+ .csid = {
+ .is_lite = true,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .hw_ops = &csid_ops_900,
+ .formats = &csid_formats_gen2
+ }
+ },
+ /* CSID_LITE8 */
+ {
+ .clock = { "vfe_lite_csid", "vfe_lite_cphy_rx", "top_ahb" },
+ .clock_rate = { { 400000000, 480000000 },
+ { 400000000, 480000000 },
+ { 0 } },
+ .reg = { "csid_lite8" },
+ .interrupt = { "csid_lite8" },
+ .csid = {
+ .is_lite = true,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .hw_ops = &csid_ops_900,
+ .formats = &csid_formats_gen2
+ }
+ },
+ /* CSID_LITE9 */
+ {
+ .clock = { "vfe_lite_csid", "vfe_lite_cphy_rx", "top_ahb" },
+ .clock_rate = { { 400000000, 480000000 },
+ { 400000000, 480000000 },
+ { 0 } },
+ .reg = { "csid_lite9" },
+ .interrupt = { "csid_lite9" },
+ .csid = {
+ .is_lite = true,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .hw_ops = &csid_ops_900,
+ .formats = &csid_formats_gen2
+ }
+ }
+};
+
+static const struct camss_subdev_resources vfe_res_nord[] = {
+ /* VFE0 - IFE Full */
+ {
+ .clock = { "gcc_axi_hf", "vfe0_fast_ahb", "vfe0",
+ "top_ahb", "top_fast_ahb",
+ "top_ife0", "camnoc_rt_axi",
+ "qdss_debug_xo" },
+ .clock_rate = { { 0 },
+ { 0 },
+ { 360280000, 480000000, 630000000, 716000000,
+ 833000000 },
+ { 0 },
+ { 0 },
+ { 0 },
+ { 200000000, 300000000, 400000000, 480000000 },
+ { 0 } },
+ .reg = { "vfe0" },
+ .interrupt = { "vfe0" },
+ .vfe = {
+ .line_num = 3,
+ .is_lite = false,
+ .reg_update_after_csid_config = true,
+ .has_pd = true,
+ .pd_name = "ife0",
+ .hw_ops = &vfe_ops_gen4,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ }
+ },
+ /* VFE1 - IFE Full */
+ {
+ .clock = { "gcc_axi_hf", "vfe1_fast_ahb", "vfe1",
+ "top_ahb", "top_fast_ahb",
+ "top_ife1", "camnoc_rt_axi",
+ "qdss_debug_xo" },
+ .clock_rate = { { 0 },
+ { 0 },
+ { 360280000, 480000000, 630000000, 716000000,
+ 833000000 },
+ { 0 },
+ { 0 },
+ { 0 },
+ { 200000000, 300000000, 400000000, 480000000 },
+ { 0 } },
+ .reg = { "vfe1" },
+ .interrupt = { "vfe1" },
+ .vfe = {
+ .line_num = 3,
+ .is_lite = false,
+ .reg_update_after_csid_config = true,
+ .has_pd = true,
+ .pd_name = "ife1",
+ .hw_ops = &vfe_ops_gen4,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ }
+ },
+ /* VFE2 - IFE Full */
+ {
+ .clock = { "gcc_axi_hf", "vfe2_fast_ahb", "vfe2",
+ "top_ahb", "top_fast_ahb",
+ "top_ife2", "camnoc_rt_axi",
+ "qdss_debug_xo" },
+ .clock_rate = { { 0 },
+ { 0 },
+ { 360280000, 480000000, 630000000, 716000000,
+ 833000000 },
+ { 0 },
+ { 0 },
+ { 0 },
+ { 200000000, 300000000, 400000000, 480000000 },
+ { 0 } },
+ .reg = { "vfe2" },
+ .interrupt = { "vfe2" },
+ .vfe = {
+ .line_num = 3,
+ .is_lite = false,
+ .reg_update_after_csid_config = true,
+ .has_pd = true,
+ .pd_name = "ife2",
+ .hw_ops = &vfe_ops_gen4,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ }
+ },
+ /* VFE_LITE0 - IFE Lite */
+ {
+ .clock = { "gcc_axi_hf", "vfe_lite_ahb", "vfe_lite",
+ "top_ahb", "top_fast_ahb",
+ "top_ife_lite", "camnoc_rt_axi",
+ "qdss_debug_xo" },
+ .clock_rate = { { 0 },
+ { 0 },
+ { 266666667, 400000000, 480000000 },
+ { 0 },
+ { 0 },
+ { 0 },
+ { 200000000, 300000000, 400000000, 480000000 },
+ { 0 } },
+ .reg = { "vfe_lite0" },
+ .interrupt = { "vfe_lite0" },
+ .vfe = {
+ .line_num = 4,
+ .is_lite = true,
+ .reg_update_after_csid_config = true,
+ .hw_ops = &vfe_ops_gen4,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ }
+ },
+ /* VFE_LITE1 - IFE Lite */
+ {
+ .clock = { "gcc_axi_hf", "vfe_lite_ahb", "vfe_lite",
+ "top_ahb", "top_fast_ahb",
+ "top_ife_lite", "camnoc_rt_axi",
+ "qdss_debug_xo" },
+ .clock_rate = { { 0 },
+ { 0 },
+ { 266666667, 400000000, 480000000 },
+ { 0 },
+ { 0 },
+ { 0 },
+ { 200000000, 300000000, 400000000, 480000000 },
+ { 0 } },
+ .reg = { "vfe_lite1" },
+ .interrupt = { "vfe_lite1" },
+ .vfe = {
+ .line_num = 4,
+ .is_lite = true,
+ .reg_update_after_csid_config = true,
+ .hw_ops = &vfe_ops_gen4,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ }
+ },
+ /* VFE_LITE2 - IFE Lite */
+ {
+ .clock = { "gcc_axi_hf", "vfe_lite_ahb", "vfe_lite",
+ "top_ahb", "top_fast_ahb",
+ "top_ife_lite", "camnoc_rt_axi",
+ "qdss_debug_xo" },
+ .clock_rate = { { 0 },
+ { 0 },
+ { 266666667, 400000000, 480000000 },
+ { 0 },
+ { 0 },
+ { 0 },
+ { 200000000, 300000000, 400000000, 480000000 },
+ { 0 } },
+ .reg = { "vfe_lite2" },
+ .interrupt = { "vfe_lite2" },
+ .vfe = {
+ .line_num = 4,
+ .is_lite = true,
+ .reg_update_after_csid_config = true,
+ .hw_ops = &vfe_ops_gen4,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ }
+ },
+ /* VFE_LITE3 - IFE Lite */
+ {
+ .clock = { "gcc_axi_hf", "vfe_lite_ahb", "vfe_lite",
+ "top_ahb", "top_fast_ahb",
+ "top_ife_lite", "camnoc_rt_axi",
+ "qdss_debug_xo" },
+ .clock_rate = { { 0 },
+ { 0 },
+ { 266666667, 400000000, 480000000 },
+ { 0 },
+ { 0 },
+ { 0 },
+ { 200000000, 300000000, 400000000, 480000000 },
+ { 0 } },
+ .reg = { "vfe_lite3" },
+ .interrupt = { "vfe_lite3" },
+ .vfe = {
+ .line_num = 4,
+ .is_lite = true,
+ .reg_update_after_csid_config = true,
+ .hw_ops = &vfe_ops_gen4,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ }
+ },
+ /* VFE_LITE4 - IFE Lite */
+ {
+ .clock = { "gcc_axi_hf", "vfe_lite_ahb", "vfe_lite",
+ "top_ahb", "top_fast_ahb",
+ "top_ife_lite", "camnoc_rt_axi",
+ "qdss_debug_xo" },
+ .clock_rate = { { 0 },
+ { 0 },
+ { 266666667, 400000000, 480000000 },
+ { 0 },
+ { 0 },
+ { 0 },
+ { 200000000, 300000000, 400000000, 480000000 },
+ { 0 } },
+ .reg = { "vfe_lite4" },
+ .interrupt = { "vfe_lite4" },
+ .vfe = {
+ .line_num = 4,
+ .is_lite = true,
+ .reg_update_after_csid_config = true,
+ .hw_ops = &vfe_ops_gen4,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ }
+ },
+ /* VFE_LITE5 - IFE Lite */
+ {
+ .clock = { "gcc_axi_hf", "vfe_lite_ahb", "vfe_lite",
+ "top_ahb", "top_fast_ahb",
+ "top_ife_lite", "camnoc_rt_axi",
+ "qdss_debug_xo" },
+ .clock_rate = { { 0 },
+ { 0 },
+ { 266666667, 400000000, 480000000 },
+ { 0 },
+ { 0 },
+ { 0 },
+ { 200000000, 300000000, 400000000, 480000000 },
+ { 0 } },
+ .reg = { "vfe_lite5" },
+ .interrupt = { "vfe_lite5" },
+ .vfe = {
+ .line_num = 4,
+ .is_lite = true,
+ .reg_update_after_csid_config = true,
+ .hw_ops = &vfe_ops_gen4,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ }
+ },
+ /* VFE_LITE6 - IFE Lite */
+ {
+ .clock = { "gcc_axi_hf", "vfe_lite_ahb", "vfe_lite",
+ "top_ahb", "top_fast_ahb",
+ "top_ife_lite", "camnoc_rt_axi",
+ "qdss_debug_xo" },
+ .clock_rate = { { 0 },
+ { 0 },
+ { 266666667, 400000000, 480000000 },
+ { 0 },
+ { 0 },
+ { 0 },
+ { 200000000, 300000000, 400000000, 480000000 },
+ { 0 } },
+ .reg = { "vfe_lite6" },
+ .interrupt = { "vfe_lite6" },
+ .vfe = {
+ .line_num = 4,
+ .is_lite = true,
+ .reg_update_after_csid_config = true,
+ .hw_ops = &vfe_ops_gen4,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ }
+ },
+ /* VFE_LITE7 - IFE Lite */
+ {
+ .clock = { "gcc_axi_hf", "vfe_lite_ahb", "vfe_lite",
+ "top_ahb", "top_fast_ahb",
+ "top_ife_lite", "camnoc_rt_axi",
+ "qdss_debug_xo" },
+ .clock_rate = { { 0 },
+ { 0 },
+ { 266666667, 400000000, 480000000 },
+ { 0 },
+ { 0 },
+ { 0 },
+ { 200000000, 300000000, 400000000, 480000000 },
+ { 0 } },
+ .reg = { "vfe_lite7" },
+ .interrupt = { "vfe_lite7" },
+ .vfe = {
+ .line_num = 4,
+ .is_lite = true,
+ .reg_update_after_csid_config = true,
+ .hw_ops = &vfe_ops_gen4,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ }
+ },
+ /* VFE_LITE8 - IFE Lite */
+ {
+ .clock = { "gcc_axi_hf", "vfe_lite_ahb", "vfe_lite",
+ "top_ahb", "top_fast_ahb",
+ "top_ife_lite", "camnoc_rt_axi",
+ "qdss_debug_xo" },
+ .clock_rate = { { 0 },
+ { 0 },
+ { 266666667, 400000000, 480000000 },
+ { 0 },
+ { 0 },
+ { 0 },
+ { 200000000, 300000000, 400000000, 480000000 },
+ { 0 } },
+ .reg = { "vfe_lite8" },
+ .interrupt = { "vfe_lite8" },
+ .vfe = {
+ .line_num = 4,
+ .is_lite = true,
+ .reg_update_after_csid_config = true,
+ .hw_ops = &vfe_ops_gen4,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ }
+ },
+ /* VFE_LITE9 - IFE Lite */
+ {
+ .clock = { "gcc_axi_hf", "vfe_lite_ahb", "vfe_lite",
+ "top_ahb", "top_fast_ahb",
+ "top_ife_lite", "camnoc_rt_axi",
+ "qdss_debug_xo" },
+ .clock_rate = { { 0 },
+ { 0 },
+ { 266666667, 400000000, 480000000 },
+ { 0 },
+ { 0 },
+ { 0 },
+ { 200000000, 300000000, 400000000, 480000000 },
+ { 0 } },
+ .reg = { "vfe_lite9" },
+ .interrupt = { "vfe_lite9" },
+ .vfe = {
+ .line_num = 4,
+ .is_lite = true,
+ .reg_update_after_csid_config = true,
+ .hw_ops = &vfe_ops_gen4,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ }
+ }
+};
+
+static const struct resources_icc icc_res_nord[] = {
+ {
+ .name = "ahb",
+ .icc_bw_tbl.avg = 150000,
+ .icc_bw_tbl.peak = 300000,
+ },
+ /* Based on 4096 x 3072 30 FPS 2496 Mbps mode */
+ {
+ .name = "hf_mnoc",
+ .icc_bw_tbl.avg = 471860,
+ .icc_bw_tbl.peak = 925857,
+ },
+};
+
/*
* camss_add_clock_margin - Add margin to clock frequency rate
* @rate: Clock frequency rate
@@ -5553,6 +6141,19 @@ static const struct camss_resources msm8996_resources = {
.vfe_num = ARRAY_SIZE(vfe_res_8x96),
};
+static const struct camss_resources nord_resources = {
+ .version = CAMSS_NORD,
+ .pd_name = "top",
+ .tpg_res = tpg_res_nord,
+ .csid_res = csid_res_nord,
+ .vfe_res = vfe_res_nord,
+ .icc_res = icc_res_nord,
+ .icc_path_num = ARRAY_SIZE(icc_res_nord),
+ .tpg_num = ARRAY_SIZE(tpg_res_nord),
+ .csid_num = ARRAY_SIZE(csid_res_nord),
+ .vfe_num = ARRAY_SIZE(vfe_res_nord),
+};
+
static const struct camss_resources qcm2290_resources = {
.version = CAMSS_2290,
.csiphy_res = csiphy_res_2290,
@@ -5744,6 +6345,7 @@ static const struct of_device_id camss_dt_match[] = {
{ .compatible = "qcom,msm8939-camss", .data = &msm8939_resources },
{ .compatible = "qcom,msm8953-camss", .data = &msm8953_resources },
{ .compatible = "qcom,msm8996-camss", .data = &msm8996_resources },
+ { .compatible = "qcom,nord-camss", .data = &nord_resources },
{ .compatible = "qcom,qcm2290-camss", .data = &qcm2290_resources },
{ .compatible = "qcom,qcs8300-camss", .data = &qcs8300_resources },
{ .compatible = "qcom,sa8775p-camss", .data = &sa8775p_resources },
--
2.34.1
prev parent reply other threads:[~2026-09-15 9:34 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-15 9:34 [PATCH 0/6] media: qcom: camss: Add support for Nord CAMSS Wenmeng Liu
2026-09-15 9:34 ` [PATCH 1/6] dt-bindings: media: Add bindings for qcom,nord-camss Wenmeng Liu
2026-09-15 9:45 ` sashiko-bot
2026-09-17 10:13 ` Krzysztof Kozlowski
2026-09-17 12:37 ` Wenmeng Liu
2026-09-18 6:47 ` Krzysztof Kozlowski
2026-09-18 7:08 ` Wenmeng Liu
2026-09-15 9:34 ` [PATCH 2/6] media: qcom: camss: csid: Add support for CSID 900 Wenmeng Liu
2026-09-15 9:50 ` sashiko-bot
2026-09-20 7:01 ` Shawn Guo
2026-09-15 9:34 ` [PATCH 3/6] media: qcom: camss: vfe: Add support for VFE gen4 Wenmeng Liu
2026-09-15 9:53 ` sashiko-bot
2026-09-20 7:19 ` Shawn Guo
2026-09-15 9:34 ` [PATCH 4/6] media: qcom: camss: vfe: Add support for VFE 900 Wenmeng Liu
2026-09-15 9:43 ` sashiko-bot
2026-09-20 7:17 ` Shawn Guo
2026-09-15 9:34 ` [PATCH 5/6] media: qcom: camss: tpg: Add support for TPG v2.5.0 Wenmeng Liu
2026-09-15 9:34 ` Wenmeng Liu [this message]
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