[PATCH v2 0/4] arm: sunplus: add SP7021 LTPP3G2 board support

[PATCH v2 0/4] arm: sunplus: add SP7021 LTPP3G2 board support

[Andrew Gaylard]

The Tibbo LTPP3G2 is a board based on the Sunplus SP7021 SoC:
https://tibbo.com/store/tps/ltpp3g2.html
It is the platform that underpins Tibbo's IoT products.

This series adds board support to linux-next:

 - Patch 1: vendor prefix for Tibbo Technology Inc.
 - Patch 2: device tree nodes for SP7021 peripherals that have upstream
             drivers (PWM, watchdog, eMMC), plus a label on the
             gpio-leds node so board DTS files can override it.
 - Patch 3: board DTS for the LTPP3G2, covering eMMC, SPI, RTC,
             a bit-banged I2C EEPROM, PWM, watchdog, and two GPIO LEDs.
 - Patch 4: sp7021_defconfig updates to enable the drivers used by the
             LTPP3G2 and correct a few defaults.

Tested on a LTPP3G2, booting via eMMC, on linux-next-20260915.

Changes in v2:
 - fix issues spotted by sashiko-bot.

Andrew Gaylard (4):
  dt-bindings: vendor-prefixes: Add Tibbo
  arm: dts: sunplus: add PWM, watchdog and MMC nodes to SP7021 DTSI
  arm: dts: sunplus: add Tibbo LTPP3G2 board
  configs: sp7021: fix defaults and enable existing device drivers

 .../devicetree/bindings/vendor-prefixes.yaml  |   2 +
 MAINTAINERS                                   |   6 +
 arch/arm/boot/dts/sunplus/Makefile            |   5 +-
 .../dts/sunplus/sunplus-sp7021-ltpp3g2.dts    | 182 ++++++++++++++++++
 arch/arm/boot/dts/sunplus/sunplus-sp7021.dtsi |  37 +++-
 arch/arm/configs/sp7021_defconfig             |  33 +++-
 6 files changed, 260 insertions(+), 5 deletions(-)
 create mode 100644 arch/arm/boot/dts/sunplus/sunplus-sp7021-ltpp3g2.dts

-- 
2.53.0

[PATCH 1/4] dt-bindings: vendor-prefixes: Add Tibbo

[Andrew Gaylard]

Add the vendor prefix for Tibbo Technology Inc., manufacturer of the LTPP3G2 board.

Signed-off-by: Andrew Gaylard <ag@ffroot.co.za>
---
 Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index 4a5cf436eb14..caf07095144c 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -1724,6 +1724,8 @@ patternProperties:
     description: Thundercomm Technology Co., Ltd.
   "^thwc,.*":
     description: Shenzhen Tong Heng Wei Chuang Technology Co., Ltd.
+  "^tibbo,.*":
+    description: Tibbo Technology Inc.
   "^ti,.*":
     description: Texas Instruments
   "^tianma,.*":
-- 
2.53.0

Re: [PATCH 1/4] dt-bindings: vendor-prefixes: Add Tibbo

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] dt-bindings: vendor-prefixes: vendor prefix '^tibbo,.*' is not in alphabetical order
--

commit 82f70f6fee71fff5d4d4526f6ffdde8383c90112
Author: Andrew Gaylard <ag@ffroot.co.za>

dt-bindings: vendor-prefixes: Add Tibbo

This commit adds the vendor prefix for Tibbo Technology Inc., manufacturer
of the LTPP3G2 board, to the vendor-prefixes schema.

> diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
> index 396044f368e7c..bee050d59baa6 100644
> --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
> +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml

[ ... ]

> @@ -1692,6 +1692,8 @@ patternProperties:
>      description: Thundercomm Technology Co., Ltd.
>    "^thwc,.*":
>      description: Shenzhen Tong Heng Wei Chuang Technology Co., Ltd.
> +  "^tibbo,.*":
> +    description: Tibbo Technology Inc.
>    "^ti,.*":

[Severity: Low]
This isn't a bug, but does this insertion break the alphabetical ordering
requirement of the patternProperties list? Alphabetically, "tibbo" should
be placed after both "ti" and "tianma" rather than before them.

>      description: Texas Instruments
>    "^tianma,.*":

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260917082632.626614-1-ag@ffroot.co.za?part=1

Re: [PATCH 1/4] dt-bindings: vendor-prefixes: Add Tibbo

[Krzysztof Kozlowski]

On Thu, Sep 17, 2026 at 10:26:29AM +0200, Andrew Gaylard wrote:
> Add the vendor prefix for Tibbo Technology Inc., manufacturer of the LTPP3G2 board.
> 
> Signed-off-by: Andrew Gaylard <ag@ffroot.co.za>

Wrong order.

Best regards,
Krzysztof

Re: [PATCH 1/4] dt-bindings: vendor-prefixes: Add Tibbo

[Krzysztof Kozlowski]

On 18/09/2026 13:29, Krzysztof Kozlowski wrote:
> On Thu, Sep 17, 2026 at 10:26:29AM +0200, Andrew Gaylard wrote:
>> Add the vendor prefix for Tibbo Technology Inc., manufacturer of the LTPP3G2 board.
>>
>> Signed-off-by: Andrew Gaylard <ag@ffroot.co.za>
> 
> Wrong order.

Also:

Please run scripts/checkpatch.pl on the patches and fix reported
warnings. After that, run also 'scripts/checkpatch.pl --strict' on the
patches and (probably) fix more warnings. Some warnings can be ignored,
especially from --strict run, but the code here looks like it needs a
fix. Feel free to get in touch if the warning is not clear.

Best regards,
Krzysztof

[PATCH 2/4] arm: dts: sunplus: add PWM, watchdog and MMC nodes to SP7021 DTSI

[Andrew Gaylard]

Add device nodes for the peripherals that have upstream drivers:
- PWM controller
- Watchdog controller
- eMMC controller

Also add a label to the gpio-leds node so board DTS files can override it.

Signed-off-by: Andrew Gaylard <ag@ffroot.co.za>
---
 arch/arm/boot/dts/sunplus/sunplus-sp7021.dtsi | 37 ++++++++++++++++++-
 1 file changed, 36 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/sunplus/sunplus-sp7021.dtsi b/arch/arm/boot/dts/sunplus/sunplus-sp7021.dtsi
index ae9bbe0320b8..40dc92a05f0e 100644
--- a/arch/arm/boot/dts/sunplus/sunplus-sp7021.dtsi
+++ b/arch/arm/boot/dts/sunplus/sunplus-sp7021.dtsi
@@ -291,9 +291,44 @@ uart4: serial@8780 {
 			pinctrl-0 = <&uart4_pins>;
 			status = "disabled";
 		};
+
+		pwm: pwm@7a00 {
+			#pwm-cells = <2>;
+			compatible = "sunplus,sp7021-pwm";
+			reg = <0x7a00 0x80>;
+			clocks = <&clkc CLK_DISP_PWM>;
+			status = "disabled";
+		};
+
+		wdt: watchdog@630 {
+			compatible = "sunplus,sp7021-wdt";
+			reg = <0x630 0x08>, <0x274 0x04>;
+			clocks = <&clkc CLK_STC0>;
+			resets = <&rstc RST_STC0>;
+			status = "disabled";
+		};
+
+		mmc0: mmc@3b00 {
+			compatible = "sunplus,sp7021-mmc";
+			reg = <0x3b00 0x180>;
+			interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clkc CLK_CARD_CTL0>;
+			resets = <&rstc RST_CARD_CTL0>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&emmc_pins>;
+			bus-width = <8>;
+			max-frequency = <52000000>;
+			non-removable;
+			disable-wp;
+			cap-mmc-highspeed;
+			mmc-ddr-3_3v;
+			no-sdio;
+			no-sd;
+			status = "disabled";
+		};
 	};
 
-	leds {
+	leds: leds {
 		compatible = "gpio-leds";
 		pinctrl-names = "default";
 		pinctrl-0 = <&leds_pins>;
-- 
2.53.0

[PATCH 3/4] arm: dts: sunplus: add Tibbo LTPP3G2 board

[Andrew Gaylard]

Add a DTS for the Tibbo LTPP3G2 board, which uses the Sunplus SP7021
SoC. The initial DTS was provided by Sunplus Technology Co. and has
been adapted for upstream with permission.

The board features eMMC, SPI, a bit-banged I2C EEPROM (Atmel 24C16),
PWM output to a buzzer, a watchdog, RTC, and two GPIO LEDs (heartbeat
and MMC activity).

Signed-off-by: Andrew Gaylard <ag@ffroot.co.za>
---
 MAINTAINERS                                   |   6 +
 arch/arm/boot/dts/sunplus/Makefile            |   5 +-
 .../dts/sunplus/sunplus-sp7021-ltpp3g2.dts    | 182 ++++++++++++++++++
 3 files changed, 190 insertions(+), 3 deletions(-)
 create mode 100644 arch/arm/boot/dts/sunplus/sunplus-sp7021-ltpp3g2.dts

diff --git a/MAINTAINERS b/MAINTAINERS
index a53620839407..f54a833484a0 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3737,6 +3737,12 @@ F:	drivers/reset/reset-sunplus.c
 F:	include/dt-bindings/clock/sunplus,sp7021-clkc.h
 F:	include/dt-bindings/reset/sunplus,sp7021-reset.h
 
+ARM/TIBBO LTPP3G2 BOARD
+M:	Andrew Gaylard <ag@ffroot.co.za>
+L:	linux-arm-kernel@lists.infradead.org
+S:	Maintained
+F:	arch/arm/boot/dts/sunplus/sunplus-sp7021-ltpp3g2.dts
+
 ARM/Synaptics SoC support
 M:	Jisheng Zhang <jszhang@kernel.org>
 M:	Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
diff --git a/arch/arm/boot/dts/sunplus/Makefile b/arch/arm/boot/dts/sunplus/Makefile
index 868f2ea0c127..25ba2e530c35 100644
--- a/arch/arm/boot/dts/sunplus/Makefile
+++ b/arch/arm/boot/dts/sunplus/Makefile
@@ -1,5 +1,4 @@
 # SPDX-License-Identifier: GPL-2.0
 dtb-$(CONFIG_SOC_SP7021) += \
-	sunplus-sp7021-demo-v3.dtb
-dtb-$(CONFIG_SOC_SP7021) += \
-	sunplus-sp7021-demo-v3.dtb
+	sunplus-sp7021-demo-v3.dtb \
+	sunplus-sp7021-ltpp3g2.dtb
diff --git a/arch/arm/boot/dts/sunplus/sunplus-sp7021-ltpp3g2.dts b/arch/arm/boot/dts/sunplus/sunplus-sp7021-ltpp3g2.dts
new file mode 100644
index 000000000000..f91b0de79c3d
--- /dev/null
+++ b/arch/arm/boot/dts/sunplus/sunplus-sp7021-ltpp3g2.dts
@@ -0,0 +1,182 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for Tibbo LTPP board G2
+ *
+ * Copyright (C) 2021 Sunplus Technology Co.
+ */
+
+/dts-v1/;
+
+#include "sunplus-sp7021-achip.dtsi"
+
+/ {
+	compatible = "tibbo,ltpp3g2", "sunplus,sp7021";
+	model = "Tibbo LTPP3G2";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		bootargs = "console=ttySUP0,115200 earlycon root=/dev/mmcblk0p8 rootwait";
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x00000000 0x20000000>; /* 512MB */
+	};
+
+	i2c_tps: i2c-tps { /* eeprom */
+		compatible = "i2c-gpio";
+		sda-gpios = <&pctl 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+		scl-gpios = <&pctl 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+		i2c-gpio,delay-us = <1>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pins_i2ctps>;
+		eeprom: eeprom@50 {
+			compatible = "atmel,24c16";
+			reg = <0x50>;
+			pagesize = <16>;
+		};
+	};
+};
+
+&leds {
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&gpio_leds_pins>;
+	pinctrl-1 = <&leds_s0_slp>;
+	system-led {
+		label = "system-led";
+		gpios = <&pctl 6 GPIO_ACTIVE_HIGH>;
+		default-state = "off";
+		linux,default-trigger = "heartbeat";
+	};
+	sg-led {
+		label = "SG";
+		gpios = <&pctl 7 GPIO_ACTIVE_HIGH>;
+		linux,default-trigger = "mmc0";
+		default-state = "off";
+	};
+};
+
+&pwm {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pins_pwm>;
+	status = "okay";
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pins_uart1>;
+	status = "disabled";
+};
+
+&uart2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pins_uart2>;
+	status = "disabled";
+};
+
+&uart3 {
+	status = "disabled";
+};
+
+&uart4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pins_btuart &pins_bt_reset>;
+	status = "disabled";
+};
+
+&mmc0 {
+	status = "okay";
+};
+
+&wdt {
+	status = "okay";
+};
+
+&pctl {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pins_gpio_nobinded>;
+
+	pins_pwm: pinmux_pwm-pins {
+		sunplus,pins = <
+			SPPCTL_IOPAD(48, SPPCTL_PCTL_G_PMUX, MUXF_PWM0, 0)
+		>;
+	};
+
+	pins_gpio_nobinded: pinmux_gpio_nobinded-pins {
+		sunplus,pins = <
+			SPPCTL_IOPAD(30, SPPCTL_PCTL_G_GPIO, 0, 0)   /* was L2SW_LED_FLASH1 */
+			SPPCTL_IOPAD(39, SPPCTL_PCTL_G_GPIO, 0, 0)   /* was L2SW_LED_ON1  */
+		>;
+	};
+
+	pins_i2ctps: pinmux_i2ctps-pins {
+		sunplus,pins = <
+			SPPCTL_IOPAD(1, SPPCTL_PCTL_G_GPIO, 0,
+				     SPPCTL_PCTL_L_OUT | SPPCTL_PCTL_L_ONV | SPPCTL_PCTL_L_ODR)
+			SPPCTL_IOPAD(2, SPPCTL_PCTL_G_GPIO, 0,
+				     SPPCTL_PCTL_L_OUT | SPPCTL_PCTL_L_ONV | SPPCTL_PCTL_L_ODR)
+		>;
+	};
+
+	gpio_leds_pins: pinmux_gpio_leds-pins {
+		sunplus,pins = <
+			SPPCTL_IOPAD(6, SPPCTL_PCTL_G_GPIO, 0, SPPCTL_PCTL_L_OUT)
+			SPPCTL_IOPAD(7, SPPCTL_PCTL_G_GPIO, 0, SPPCTL_PCTL_L_OUT)
+		>;
+	};
+
+	leds_s0_slp: pinmux_user_leds_s0_slp-pins {
+		sunplus,pins = <
+			SPPCTL_IOPAD(6, SPPCTL_PCTL_G_GPIO, 0, 0)
+			SPPCTL_IOPAD(7, SPPCTL_PCTL_G_GPIO, 0, 0)
+		>;
+	};
+
+	pins_uart1: pinmux_uart1-pins {
+		sunplus,pins = <
+			SPPCTL_IOPAD(8, SPPCTL_PCTL_G_PMUX, MUXF_UA1_TX, 0)
+			SPPCTL_IOPAD(9, SPPCTL_PCTL_G_PMUX, MUXF_UA1_RX, 0)
+			SPPCTL_IOPAD(10, SPPCTL_PCTL_G_PMUX, MUXF_UA1_RTS, 0)
+			SPPCTL_IOPAD(11, SPPCTL_PCTL_G_PMUX, MUXF_UA1_CTS, 0)
+		>;
+	};
+
+	pins_uart2: pinmux_uart2-pins {
+		sunplus,pins = <
+			SPPCTL_IOPAD(12, SPPCTL_PCTL_G_PMUX, MUXF_UA2_TX, 0)
+			SPPCTL_IOPAD(13, SPPCTL_PCTL_G_PMUX, MUXF_UA2_RX, 0)
+			SPPCTL_IOPAD(14, SPPCTL_PCTL_G_PMUX, MUXF_UA2_RTS, 0)
+			SPPCTL_IOPAD(15, SPPCTL_PCTL_G_PMUX, MUXF_UA2_CTS, 0)
+		>;
+	};
+
+	pins_uart3: pinmux_uart3-pins {
+		sunplus,pins = <
+			SPPCTL_IOPAD(16, SPPCTL_PCTL_G_PMUX, MUXF_UA3_TX, 0)
+			SPPCTL_IOPAD(17, SPPCTL_PCTL_G_PMUX, MUXF_UA3_RX, 0)
+			SPPCTL_IOPAD(18, SPPCTL_PCTL_G_PMUX, MUXF_UA3_RTS, 0)
+			SPPCTL_IOPAD(19, SPPCTL_PCTL_G_PMUX, MUXF_UA3_CTS, 0)
+		>;
+	};
+
+	/* AP6256 Bluetooth */
+	pins_btuart: pinmux_btuart-pins {
+		sunplus,pins = <
+			SPPCTL_IOPAD(40, SPPCTL_PCTL_G_PMUX, MUXF_UA4_RX, 0)
+			SPPCTL_IOPAD(41, SPPCTL_PCTL_G_PMUX, MUXF_UA4_TX, 0)
+			SPPCTL_IOPAD(56, SPPCTL_PCTL_G_PMUX, MUXF_UA4_RTS, SPPCTL_PCTL_L_ONV)
+			SPPCTL_IOPAD(49, SPPCTL_PCTL_G_PMUX, MUXF_UA4_CTS, 0)
+		>;
+	};
+
+	pins_bt_reset: pinmux_bt_reset-pins {
+		sunplus,pins = < SPPCTL_IOPAD(82, SPPCTL_PCTL_G_GPIO, 0, 0) >;
+	};
+
+};
-- 
2.53.0

Re: [PATCH 3/4] arm: dts: sunplus: add Tibbo LTPP3G2 board

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 6 potential issue(s) to consider:
- [High] i2c: open-drain bus stuck LOW due to hardware output inversion
- [Medium] pinctrl: requested RTS output inversion is silently ignored for PMUX pins
- [Low] dts: hardcoded OS-specific root partition in bootargs
- [Low] dts: non-generic device tree node names for I2C and LEDs
- [Low] dts: unused pinctrl definition for UART3 (dead code)
- [Low] dt-bindings: missing compatible string documentation for tibbo,ltpp3g2
--

commit 10e32790a2e05cfde60226acde658b3dc19b67ab
Author: Andrew Gaylard <ag@ffroot.co.za>
Subject: arm: dts: sunplus: add Tibbo LTPP3G2 board

This adds a device tree for the Tibbo LTPP3G2 board based on the Sunplus
SP7021 SoC. The hardware description includes eMMC, SPI, bit-banged I2C
EEPROM, PWM, a watchdog, RTC, and two GPIO LEDs.

> diff --git a/arch/arm/boot/dts/sunplus/sunplus-sp7021-ltpp3g2.dts b/arch/arm/boot/dts/sunplus/sunplus-sp7021-ltpp3g2.dts
> new file mode 100644
> index 0000000000000..f91b0de79c3d0
> --- /dev/null
> +++ b/arch/arm/boot/dts/sunplus/sunplus-sp7021-ltpp3g2.dts
> @@ -0,0 +1,182 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Device Tree Source for Tibbo LTPP board G2
> + *
> + * Copyright (C) 2021 Sunplus Technology Co.
> + */
> +
> +/dts-v1/;
> +
> +#include "sunplus-sp7021-achip.dtsi"
> +
> +/ {
> +	compatible = "tibbo,ltpp3g2", "sunplus,sp7021";

[Severity: Low]
Is the tibbo,ltpp3g2 compatible string documented in the YAML bindings?
Running dtbs_check will likely fail since this board string does not
appear to be documented.

[ ... ]

> +	chosen {
> +		bootargs = "console=ttySUP0,115200 earlycon root=/dev/mmcblk0p8 rootwait";

[Severity: Low]
Does hardcoding root=/dev/mmcblk0p8 tie the device tree to a highly specific
OS partitioning scheme? Booting a standard kernel image that expects the root
filesystem on a different partition will fail to mount root without overriding
bootargs. Could this be removed to better separate the hardware description
from software configuration?

[ ... ]

> +	i2c_tps: i2c-tps { /* eeprom */

[Severity: Low]
Does the i2c-tps node name violate standard Devicetree naming schemas?
Node names should typically be generic, such as i2c.

[ ... ]

> +&leds {
> +	pinctrl-names = "default", "sleep";
> +	pinctrl-0 = <&gpio_leds_pins>;
> +	pinctrl-1 = <&leds_s0_slp>;
> +	system-led {

[Severity: Low]
Should this node use a generic name like led-0 to comply with standard
validation schemas?

[ ... ]

> +&uart3 {
> +	status = "disabled";
> +};

[Severity: Low]
Should uart3 claim the pins_uart3 pinctrl configuration here, similar to
uart1, uart2, and uart4? If a user enables uart3 via an overlay, the
hardware pins will remain unconfigured.

[ ... ]

> +	pins_i2ctps: pinmux_i2ctps-pins {
> +		sunplus,pins = <
> +			SPPCTL_IOPAD(1, SPPCTL_PCTL_G_GPIO, 0,
> +				     SPPCTL_PCTL_L_OUT | SPPCTL_PCTL_L_ONV | SPPCTL_PCTL_L_ODR)
> +			SPPCTL_IOPAD(2, SPPCTL_PCTL_G_GPIO, 0,
> +				     SPPCTL_PCTL_L_OUT | SPPCTL_PCTL_L_ONV | SPPCTL_PCTL_L_ODR)
> +		>;
> +	};

[Severity: High]
Will applying SPPCTL_PCTL_L_ONV to these pins break open-drain signaling
and persistently hold the bus LOW?

When the i2c-gpio driver requests the bus to float HIGH by writing 1, the
SPPCTL_PCTL_L_ONV configuration bit hardware-inverts this 1 into a 0,
pulling the open-drain line strongly LOW.

Should SPPCTL_PCTL_L_OU1 be used instead of combining SPPCTL_PCTL_L_OUT
with SPPCTL_PCTL_L_ONV to set an initial HIGH output without breaking logic?

[ ... ]

> +	/* AP6256 Bluetooth */
> +	pins_btuart: pinmux_btuart-pins {
> +		sunplus,pins = <
> +			SPPCTL_IOPAD(40, SPPCTL_PCTL_G_PMUX, MUXF_UA4_RX, 0)
> +			SPPCTL_IOPAD(41, SPPCTL_PCTL_G_PMUX, MUXF_UA4_TX, 0)
> +			SPPCTL_IOPAD(56, SPPCTL_PCTL_G_PMUX, MUXF_UA4_RTS, SPPCTL_PCTL_L_ONV)

[Severity: Medium]
Is the SPPCTL_PCTL_L_ONV inversion request actually taking effect for this
PMUX pin?

Looking at the SP7021 pinctrl driver in sppctl_dt_node_to_map(), it generates
a PIN_MAP_TYPE_MUX_GROUP for SPPCTL_PCTL_G_PMUX pin types and explicitly
discards configuration bits.

As a result, the requested inversion will be silently ignored, potentially
causing UART flow control failure if the AP6256 module actually requires an
inverted signal.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260917082632.626614-1-ag@ffroot.co.za?part=3

Re: [PATCH 3/4] arm: dts: sunplus: add Tibbo LTPP3G2 board

[Krzysztof Kozlowski]

On Thu, Sep 17, 2026 at 10:26:31AM +0200, Andrew Gaylard wrote:
> Add a DTS for the Tibbo LTPP3G2 board, which uses the Sunplus SP7021
> SoC. The initial DTS was provided by Sunplus Technology Co. and has
> been adapted for upstream with permission.
> 
> The board features eMMC, SPI, a bit-banged I2C EEPROM (Atmel 24C16),
> PWM output to a buzzer, a watchdog, RTC, and two GPIO LEDs (heartbeat
> and MMC activity).
> 
> Signed-off-by: Andrew Gaylard <ag@ffroot.co.za>
> ---
>  MAINTAINERS                                   |   6 +
>  arch/arm/boot/dts/sunplus/Makefile            |   5 +-
>  .../dts/sunplus/sunplus-sp7021-ltpp3g2.dts    | 182 ++++++++++++++++++
>  3 files changed, 190 insertions(+), 3 deletions(-)
>  create mode 100644 arch/arm/boot/dts/sunplus/sunplus-sp7021-ltpp3g2.dts
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index a53620839407..f54a833484a0 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -3737,6 +3737,12 @@ F:	drivers/reset/reset-sunplus.c
>  F:	include/dt-bindings/clock/sunplus,sp7021-clkc.h
>  F:	include/dt-bindings/reset/sunplus,sp7021-reset.h
>  
> +ARM/TIBBO LTPP3G2 BOARD
> +M:	Andrew Gaylard <ag@ffroot.co.za>
> +L:	linux-arm-kernel@lists.infradead.org
> +S:	Maintained
> +F:	arch/arm/boot/dts/sunplus/sunplus-sp7021-ltpp3g2.dts
> +
>  ARM/Synaptics SoC support
>  M:	Jisheng Zhang <jszhang@kernel.org>
>  M:	Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
> diff --git a/arch/arm/boot/dts/sunplus/Makefile b/arch/arm/boot/dts/sunplus/Makefile
> index 868f2ea0c127..25ba2e530c35 100644
> --- a/arch/arm/boot/dts/sunplus/Makefile
> +++ b/arch/arm/boot/dts/sunplus/Makefile
> @@ -1,5 +1,4 @@
>  # SPDX-License-Identifier: GPL-2.0
>  dtb-$(CONFIG_SOC_SP7021) += \
> -	sunplus-sp7021-demo-v3.dtb
> -dtb-$(CONFIG_SOC_SP7021) += \
> -	sunplus-sp7021-demo-v3.dtb
> +	sunplus-sp7021-demo-v3.dtb \
> +	sunplus-sp7021-ltpp3g2.dtb
> diff --git a/arch/arm/boot/dts/sunplus/sunplus-sp7021-ltpp3g2.dts b/arch/arm/boot/dts/sunplus/sunplus-sp7021-ltpp3g2.dts
> new file mode 100644
> index 000000000000..f91b0de79c3d
> --- /dev/null
> +++ b/arch/arm/boot/dts/sunplus/sunplus-sp7021-ltpp3g2.dts
> @@ -0,0 +1,182 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Device Tree Source for Tibbo LTPP board G2
> + *
> + * Copyright (C) 2021 Sunplus Technology Co.
> + */
> +
> +/dts-v1/;
> +
> +#include "sunplus-sp7021-achip.dtsi"
> +
> +/ {
> +	compatible = "tibbo,ltpp3g2", "sunplus,sp7021";
> +	model = "Tibbo LTPP3G2";
> +
> +	aliases {
> +		serial0 = &uart0;
> +	};
> +
> +	chosen {
> +		bootargs = "console=ttySUP0,115200 earlycon root=/dev/mmcblk0p8 rootwait";

None of above should be here. earlycon is for debugging. Console is
below. root - why booting is fixed to mmc? Why none of other boot
methods are suitable or allowed?

> +		stdout-path = "serial0:115200n8";
> +	};

...

> +	pins_btuart: pinmux_btuart-pins {
> +		sunplus,pins = <
> +			SPPCTL_IOPAD(40, SPPCTL_PCTL_G_PMUX, MUXF_UA4_RX, 0)
> +			SPPCTL_IOPAD(41, SPPCTL_PCTL_G_PMUX, MUXF_UA4_TX, 0)
> +			SPPCTL_IOPAD(56, SPPCTL_PCTL_G_PMUX, MUXF_UA4_RTS, SPPCTL_PCTL_L_ONV)
> +			SPPCTL_IOPAD(49, SPPCTL_PCTL_G_PMUX, MUXF_UA4_CTS, 0)
> +		>;
> +	};
> +
> +	pins_bt_reset: pinmux_bt_reset-pins {

Please follow DTS coding style for naming.

Best regards,
Krzysztof

Re: [PATCH 3/4] arm: dts: sunplus: add Tibbo LTPP3G2 board

[Andrew Gaylard]

Krzysztof Kozlowski <krzk@kernel.org> writes:

> On Thu, Sep 17, 2026 at 10:26:31AM +0200, Andrew Gaylard wrote:
>> +		bootargs = "console=ttySUP0,115200 earlycon root=/dev/mmcblk0p8 rootwait";
>
> None of above should be here. earlycon is for debugging. Console is
> below. root - why booting is fixed to mmc? Why none of other boot
> methods are suitable or allowed?

Because as of linux-next 20260915, ethernet does not work (crashes the
chip hard; I have a patch series coming that will fix this), and the SD
and USB drivers are not yet upstream.  That leaves only the eMMC for a
rootfs.

Nonetheless, you're right, none of this belongs in the DTS.
I'll remove the whole line.

>> +	pins_bt_reset: pinmux_bt_reset-pins {
>
> Please follow DTS coding style for naming.

Will do.

-- 
Andrew

[PATCH 4/4] configs: sp7021: fix defaults and enable existing device drivers

[Andrew Gaylard]

The LTPP3G2 is based on a SP7021 and has a Cortex-A7 CPU, Ethernet,
eMMC, SPI, EEPROM via I2C via GPIO, watchdog, RTC, NVMEM, and LEDs.

Apply these settings:
- ARM_ERRATA_814220=y	# needed for Cortex-A7
- SMP is not set        # SMP is not yet implemented for this SoC
- CGROUP=y
  SECURITY=y
  CGROUP_SCHED=y
  MEMCG=y
  NET=y
  UNIX=y
  INET=y
  NETDEVICES=y
  SECURITY=y
  SECURITY_NETWORK=y    # needed to boot the shipped rootfs

Enable these drivers:
- SP7021_EMAC
- SPI_SUNPLUS_SP7021
- I2C_GPIO
- EEPROM_AT24
- MMC_SUNPLUS
- SUNPLUS_WATCHDOG
- RTC_DRV_SUNPLUS
- NVMEM_SUNPLUS_OCOTP
- LEDS_GPIO

Signed-off-by: Andrew Gaylard <ag@ffroot.co.za>
---
 arch/arm/configs/sp7021_defconfig | 33 ++++++++++++++++++++++++++++++-
 1 file changed, 32 insertions(+), 1 deletion(-)

diff --git a/arch/arm/configs/sp7021_defconfig b/arch/arm/configs/sp7021_defconfig
index ec723401b440..e6a2debab8d4 100644
--- a/arch/arm/configs/sp7021_defconfig
+++ b/arch/arm/configs/sp7021_defconfig
@@ -1,4 +1,7 @@
 CONFIG_SYSVIPC=y
+CONFIG_CGROUPS=y
+CONFIG_CGROUP_SCHED=y
+CONFIG_MEMCG=y
 CONFIG_NO_HZ_IDLE=y
 CONFIG_HIGH_RES_TIMERS=y
 CONFIG_PREEMPT=y
@@ -15,7 +18,8 @@ CONFIG_CC_OPTIMIZE_FOR_SIZE=y
 CONFIG_PERF_EVENTS=y
 CONFIG_ARCH_SUNPLUS=y
 # CONFIG_VDSO is not set
-CONFIG_SMP=y
+# CONFIG_SMP is not set
+CONFIG_ARM_ERRATA_814220=y
 CONFIG_THUMB2_KERNEL=y
 CONFIG_ARCH_FORCE_MAX_ORDER=11
 CONFIG_VFP=y
@@ -24,11 +28,16 @@ CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 CONFIG_MODVERSIONS=y
 # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_NET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
 CONFIG_UEVENT_HELPER=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_DEVTMPFS=y
 CONFIG_DEVTMPFS_MOUNT=y
 CONFIG_BLK_DEV_LOOP=y
+CONFIG_NETDEVICES=y
+CONFIG_SP7021_EMAC=y
 CONFIG_INPUT_SPARSEKMAP=y
 CONFIG_INPUT_EVDEV=y
 # CONFIG_INPUT_KEYBOARD is not set
@@ -36,6 +45,26 @@ CONFIG_INPUT_EVDEV=y
 # CONFIG_LEGACY_PTYS is not set
 # CONFIG_HW_RANDOM is not set
 # CONFIG_HWMON is not set
+CONFIG_SPI=y
+CONFIG_SPI_SUNPLUS_SP7021=y
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_GPIO=y
+CONFIG_EEPROM_AT24=y
+CONFIG_MMC=y
+CONFIG_MMC_SUNPLUS=y
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_SYSFS=y
+CONFIG_SUNPLUS_WATCHDOG=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_SUNPLUS=y
+CONFIG_NVMEM=y
+CONFIG_NVMEM_SUNPLUS_OCOTP=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
 # CONFIG_IOMMU_SUPPORT is not set
 CONFIG_RESET_CONTROLLER=y
 CONFIG_EXT4_FS=y
@@ -51,6 +80,8 @@ CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_ASCII=y
 CONFIG_NLS_ISO8859_1=y
 CONFIG_NLS_UTF8=y
+CONFIG_SECURITY=y
+CONFIG_SECURITY_NETWORK=y
 CONFIG_PRINTK_TIME=y
 CONFIG_DYNAMIC_DEBUG=y
 CONFIG_MAGIC_SYSRQ=y
-- 
2.53.0