* [PATCH] arm64: dts: qcom: nord: Add LLCC node
@ 2026-09-22 9:17 Shawn Guo
2026-09-22 9:27 ` sashiko-bot
` (4 more replies)
0 siblings, 5 replies; 6+ messages in thread
From: Shawn Guo @ 2026-09-22 9:17 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Bartosz Golaszewski, devicetree, linux-arm-msm, linux-kernel,
Anurag Pateriya, Shawn Guo
From: Anurag Pateriya <anurag.pateriya@oss.qualcomm.com>
Add the system cache controller. All sixteen banks are listed, four per
DDR slice at 0x100000 strides from slice + 0x800000, followed by the
global broadcast OR/AND regions, which the driver expects at the reg
indices right after the last bank.
No ECC interrupt is described, as the Nord interrupt map does not expose
one for the LLCC. The driver treats it as optional.
Signed-off-by: Anurag Pateriya <anurag.pateriya@oss.qualcomm.com>
Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
---
Dependencies:
- LLCC driver: https://lore.kernel.org/all/20260910-nord_llcc-v1-0-30fd1cca65fe@oss.qualcomm.com/
arch/arm64/boot/dts/qcom/nord.dtsi | 40 ++++++++++++++++++++++++++++++
1 file changed, 40 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/nord.dtsi b/arch/arm64/boot/dts/qcom/nord.dtsi
index e0496fd40c30..6896bda14ef3 100644
--- a/arch/arm64/boot/dts/qcom/nord.dtsi
+++ b/arch/arm64/boot/dts/qcom/nord.dtsi
@@ -2071,6 +2071,46 @@ watchdog@17826000 {
clocks = <&sleep_clk>;
interrupts = <GIC_ESPI 848 IRQ_TYPE_EDGE_RISING>;
};
+
+ llcc: system-cache-controller@21800000 {
+ compatible = "qcom,nord-llcc";
+ reg = <0x0 0x21800000 0x0 0x100000>,
+ <0x0 0x21a00000 0x0 0x100000>,
+ <0x0 0x21c00000 0x0 0x100000>,
+ <0x0 0x21e00000 0x0 0x100000>,
+ <0x0 0x22800000 0x0 0x100000>,
+ <0x0 0x22a00000 0x0 0x100000>,
+ <0x0 0x22c00000 0x0 0x100000>,
+ <0x0 0x22e00000 0x0 0x100000>,
+ <0x0 0x23800000 0x0 0x100000>,
+ <0x0 0x23a00000 0x0 0x100000>,
+ <0x0 0x23c00000 0x0 0x100000>,
+ <0x0 0x23e00000 0x0 0x100000>,
+ <0x0 0x24800000 0x0 0x100000>,
+ <0x0 0x24a00000 0x0 0x100000>,
+ <0x0 0x24c00000 0x0 0x100000>,
+ <0x0 0x24e00000 0x0 0x100000>,
+ <0x0 0x20400000 0x0 0x100000>,
+ <0x0 0x20600000 0x0 0x100000>;
+ reg-names = "llcc0_base",
+ "llcc1_base",
+ "llcc2_base",
+ "llcc3_base",
+ "llcc4_base",
+ "llcc5_base",
+ "llcc6_base",
+ "llcc7_base",
+ "llcc8_base",
+ "llcc9_base",
+ "llcc10_base",
+ "llcc11_base",
+ "llcc12_base",
+ "llcc13_base",
+ "llcc14_base",
+ "llcc15_base",
+ "llcc_broadcast_base",
+ "llcc_broadcast_and_base";
+ };
};
arch_timer: timer {
--
2.43.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH] arm64: dts: qcom: nord: Add LLCC node
2026-09-22 9:17 [PATCH] arm64: dts: qcom: nord: Add LLCC node Shawn Guo
@ 2026-09-22 9:27 ` sashiko-bot
2026-09-23 7:08 ` Bartosz Golaszewski
` (3 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: sashiko-bot @ 2026-09-22 9:27 UTC (permalink / raw)
To: Shawn Guo; +Cc: conor+dt, devicetree, robh
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] dts: qcom: mismatch between DT reg addresses and commit message stride
--
commit 0675a08212d643f9f31ddc67dcf4a44b377036e9
Author: Anurag Pateriya <anurag.pateriya@oss.qualcomm.com>
arm64: dts: qcom: nord: Add LLCC node
This commit adds the system cache controller to the Nord device tree. It
defines sixteen banks across four DDR slices, along with the global broadcast
regions.
> diff --git a/arch/arm64/boot/dts/qcom/nord.dtsi b/arch/arm64/boot/dts/qcom/nord.dtsi
> index e0496fd40c308..6896bda14ef3c 100644
> --- a/arch/arm64/boot/dts/qcom/nord.dtsi
> +++ b/arch/arm64/boot/dts/qcom/nord.dtsi
[ ... ]
> @@ -2071,6 +2071,46 @@ watchdog@17826000 {
> clocks = <&sleep_clk>;
> interrupts = <GIC_ESPI 848 IRQ_TYPE_EDGE_RISING>;
> };
> +
> + llcc: system-cache-controller@21800000 {
> + compatible = "qcom,nord-llcc";
> + reg = <0x0 0x21800000 0x0 0x100000>,
> + <0x0 0x21a00000 0x0 0x100000>,
> + <0x0 0x21c00000 0x0 0x100000>,
> + <0x0 0x21e00000 0x0 0x100000>,
[Severity: Medium]
The commit message states the LLCC banks are placed at 0x100000 strides, but
the bank addresses here show a 0x200000 stride (e.g., 0x21a00000 - 0x21800000
equals 0x200000). Could there be a typo in the commit message, or should these
physical addresses use a 0x100000 stride?
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260922091735.491481-1-shengchao.guo@oss.qualcomm.com?part=1
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] arm64: dts: qcom: nord: Add LLCC node
2026-09-22 9:17 [PATCH] arm64: dts: qcom: nord: Add LLCC node Shawn Guo
2026-09-22 9:27 ` sashiko-bot
@ 2026-09-23 7:08 ` Bartosz Golaszewski
2026-09-23 9:08 ` Pankaj Patil
` (2 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Bartosz Golaszewski @ 2026-09-23 7:08 UTC (permalink / raw)
To: Shawn Guo
Cc: Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Bartosz Golaszewski, devicetree, linux-arm-msm, linux-kernel,
Anurag Pateriya, Bjorn Andersson
On Tue, 22 Sep 2026 11:17:35 +0200, Shawn Guo
<shengchao.guo@oss.qualcomm.com> said:
> From: Anurag Pateriya <anurag.pateriya@oss.qualcomm.com>
>
> Add the system cache controller. All sixteen banks are listed, four per
> DDR slice at 0x100000 strides from slice + 0x800000, followed by the
> global broadcast OR/AND regions, which the driver expects at the reg
> indices right after the last bank.
>
> No ECC interrupt is described, as the Nord interrupt map does not expose
> one for the LLCC. The driver treats it as optional.
>
> Signed-off-by: Anurag Pateriya <anurag.pateriya@oss.qualcomm.com>
> Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
> ---
Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] arm64: dts: qcom: nord: Add LLCC node
2026-09-22 9:17 [PATCH] arm64: dts: qcom: nord: Add LLCC node Shawn Guo
2026-09-22 9:27 ` sashiko-bot
2026-09-23 7:08 ` Bartosz Golaszewski
@ 2026-09-23 9:08 ` Pankaj Patil
2026-09-24 11:28 ` Abel Vesa
2026-09-25 12:14 ` Konrad Dybcio
4 siblings, 0 replies; 6+ messages in thread
From: Pankaj Patil @ 2026-09-23 9:08 UTC (permalink / raw)
To: Shawn Guo, Bjorn Andersson
Cc: Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Bartosz Golaszewski, devicetree, linux-arm-msm, linux-kernel,
Anurag Pateriya
On 9/22/2026 2:47 PM, Shawn Guo wrote:
> From: Anurag Pateriya <anurag.pateriya@oss.qualcomm.com>
>
> Add the system cache controller. All sixteen banks are listed, four per
> DDR slice at 0x100000 strides from slice + 0x800000, followed by the
> global broadcast OR/AND regions, which the driver expects at the reg
> indices right after the last bank.
>
> No ECC interrupt is described, as the Nord interrupt map does not expose
> one for the LLCC. The driver treats it as optional.
>
> Signed-off-by: Anurag Pateriya <anurag.pateriya@oss.qualcomm.com>
> Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
> ---
> Dependencies:
> - LLCC driver: https://lore.kernel.org/all/20260910-nord_llcc-v1-0-30fd1cca65fe@oss.qualcomm.com/
>
> arch/arm64/boot/dts/qcom/nord.dtsi | 40 ++++++++++++++++++++++++++++++
> 1 file changed, 40 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/nord.dtsi b/arch/arm64/boot/dts/qcom/nord.dtsi
> index e0496fd40c30..6896bda14ef3 100644
> --- a/arch/arm64/boot/dts/qcom/nord.dtsi
> +++ b/arch/arm64/boot/dts/qcom/nord.dtsi
> @@ -2071,6 +2071,46 @@ watchdog@17826000 {
> clocks = <&sleep_clk>;
> interrupts = <GIC_ESPI 848 IRQ_TYPE_EDGE_RISING>;
> };
> +
> + llcc: system-cache-controller@21800000 {
> + compatible = "qcom,nord-llcc";
> + reg = <0x0 0x21800000 0x0 0x100000>,
> + <0x0 0x21a00000 0x0 0x100000>,
> + <0x0 0x21c00000 0x0 0x100000>,
> + <0x0 0x21e00000 0x0 0x100000>,
> + <0x0 0x22800000 0x0 0x100000>,
> + <0x0 0x22a00000 0x0 0x100000>,
> + <0x0 0x22c00000 0x0 0x100000>,
> + <0x0 0x22e00000 0x0 0x100000>,
> + <0x0 0x23800000 0x0 0x100000>,
> + <0x0 0x23a00000 0x0 0x100000>,
> + <0x0 0x23c00000 0x0 0x100000>,
> + <0x0 0x23e00000 0x0 0x100000>,
> + <0x0 0x24800000 0x0 0x100000>,
> + <0x0 0x24a00000 0x0 0x100000>,
> + <0x0 0x24c00000 0x0 0x100000>,
> + <0x0 0x24e00000 0x0 0x100000>,
> + <0x0 0x20400000 0x0 0x100000>,
> + <0x0 0x20600000 0x0 0x100000>;
> + reg-names = "llcc0_base",
> + "llcc1_base",
> + "llcc2_base",
> + "llcc3_base",
> + "llcc4_base",
> + "llcc5_base",
> + "llcc6_base",
> + "llcc7_base",
> + "llcc8_base",
> + "llcc9_base",
> + "llcc10_base",
> + "llcc11_base",
> + "llcc12_base",
> + "llcc13_base",
> + "llcc14_base",
> + "llcc15_base",
> + "llcc_broadcast_base",
> + "llcc_broadcast_and_base";
> + };
> };
>
> arch_timer: timer {
Reviewed-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] arm64: dts: qcom: nord: Add LLCC node
2026-09-22 9:17 [PATCH] arm64: dts: qcom: nord: Add LLCC node Shawn Guo
` (2 preceding siblings ...)
2026-09-23 9:08 ` Pankaj Patil
@ 2026-09-24 11:28 ` Abel Vesa
2026-09-25 12:14 ` Konrad Dybcio
4 siblings, 0 replies; 6+ messages in thread
From: Abel Vesa @ 2026-09-24 11:28 UTC (permalink / raw)
To: Shawn Guo
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bartosz Golaszewski, devicetree, linux-arm-msm,
linux-kernel, Anurag Pateriya
On 26-09-22 17:17:35, Shawn Guo wrote:
> From: Anurag Pateriya <anurag.pateriya@oss.qualcomm.com>
>
> Add the system cache controller. All sixteen banks are listed, four per
> DDR slice at 0x100000 strides from slice + 0x800000, followed by the
> global broadcast OR/AND regions, which the driver expects at the reg
> indices right after the last bank.
>
> No ECC interrupt is described, as the Nord interrupt map does not expose
> one for the LLCC. The driver treats it as optional.
>
> Signed-off-by: Anurag Pateriya <anurag.pateriya@oss.qualcomm.com>
> Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] arm64: dts: qcom: nord: Add LLCC node
2026-09-22 9:17 [PATCH] arm64: dts: qcom: nord: Add LLCC node Shawn Guo
` (3 preceding siblings ...)
2026-09-24 11:28 ` Abel Vesa
@ 2026-09-25 12:14 ` Konrad Dybcio
4 siblings, 0 replies; 6+ messages in thread
From: Konrad Dybcio @ 2026-09-25 12:14 UTC (permalink / raw)
To: Shawn Guo, Bjorn Andersson
Cc: Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Bartosz Golaszewski, devicetree, linux-arm-msm, linux-kernel,
Anurag Pateriya
On 9/22/26 11:17 AM, Shawn Guo wrote:
> From: Anurag Pateriya <anurag.pateriya@oss.qualcomm.com>
>
> Add the system cache controller. All sixteen banks are listed, four per
> DDR slice at 0x100000 strides from slice + 0x800000, followed by the
> global broadcast OR/AND regions, which the driver expects at the reg
> indices right after the last bank.
>
> No ECC interrupt is described, as the Nord interrupt map does not expose
> one for the LLCC. The driver treats it as optional.
>
> Signed-off-by: Anurag Pateriya <anurag.pateriya@oss.qualcomm.com>
> Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
^ permalink raw reply [flat|nested] 6+ messages in thread
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2026-09-22 9:17 [PATCH] arm64: dts: qcom: nord: Add LLCC node Shawn Guo
2026-09-22 9:27 ` sashiko-bot
2026-09-23 7:08 ` Bartosz Golaszewski
2026-09-23 9:08 ` Pankaj Patil
2026-09-24 11:28 ` Abel Vesa
2026-09-25 12:14 ` Konrad Dybcio
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