[PATCH 0/2] ARM: dts: phyCORE-i.MX6 custom OPP table

[PATCH 0/2] ARM: dts: phyCORE-i.MX6 custom OPP table

[Primoz Fiser]

This is a revival of a series originally posted by Yunus Bas in
February 2022 [1][2]. It adds a label to the imx6dl cpu1 node and
introduces phyCORE-i.MX6 SOM specific operating-points tables, since
the phyCORE modules run at slightly different voltage/frequency values
than the generic i.MX6Q/DL tables.

[1] https://lore.kernel.org/all/20220209223258.1672425-1-y.bas@phytec.de/
[2] https://lore.kernel.org/all/20220209223258.1672425-2-y.bas@phytec.de/

Changes to original series:

Patch #1:
 - update path to nxp/imx
 
Patch #2:
 - update path to nxp/imx
 - reformat operating-points/fsl,soc-operating-points as a proper
   uint32-matrix, addressing Shawn Guo's review original remark.

Yunus Bas (2):
  ARM: dts: imx6dl: Add a label to cpu1 node
  ARM: dts: imx6qdl: phycore-som: Add custom volt/freq table

 .../nxp/imx/imx6dl-phytec-mira-rdk-nand.dts   |  2 +-
 .../nxp/imx/imx6dl-phytec-phycore-som.dtsi    | 23 ++++++
 arch/arm/boot/dts/nxp/imx/imx6dl.dtsi         |  2 +-
 .../nxp/imx/imx6q-phytec-mira-rdk-emmc.dts    |  2 +-
 .../nxp/imx/imx6q-phytec-mira-rdk-nand.dts    |  2 +-
 .../dts/nxp/imx/imx6q-phytec-phycore-som.dtsi | 75 +++++++++++++++++++
 6 files changed, 102 insertions(+), 4 deletions(-)
 create mode 100644 arch/arm/boot/dts/nxp/imx/imx6dl-phytec-phycore-som.dtsi
 create mode 100644 arch/arm/boot/dts/nxp/imx/imx6q-phytec-phycore-som.dtsi

-- 
2.34.1

[PATCH 1/2] ARM: dts: imx6dl: Add a label to cpu1 node

[Primoz Fiser]

From: Yunus Bas <y.bas@phytec.de>

The cpu1 is missing a label for further reference. Since cpu0 has
already a label, add also one for cpu1 node, so it can be referenced to
add or modify cpu specific properties the same way as cpu0.

Signed-off-by: Yunus Bas <y.bas@phytec.de>
Signed-off-by: Primoz Fiser <primoz.fiser@norik.com>
---
 arch/arm/boot/dts/nxp/imx/imx6dl.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl.dtsi b/arch/arm/boot/dts/nxp/imx/imx6dl.dtsi
index dc919e09a505..78092d94f265 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6dl.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx6dl.dtsi
@@ -48,7 +48,7 @@ cpu0: cpu@0 {
 			nvmem-cell-names = "speed_grade";
 		};
 
-		cpu@1 {
+		cpu1: cpu@1 {
 			compatible = "arm,cortex-a9";
 			device_type = "cpu";
 			reg = <1>;
-- 
2.34.1

[PATCH 2/2] ARM: dts: imx6qdl: phycore-som: Add custom volt/freq table

[Primoz Fiser]

From: Yunus Bas <y.bas@phytec.de>

The PHYTEC phyCORE-i.MX6QDL SOM-modules are operating with a slightly
different voltage and frequency values in contrast to the generic
i.MX6Q/DL tables. The values have been adjusted to achieve the most
stable condition for the PHYTEC-modules. Introduce imx6q- and
imx6dl-phycore dtsi files with the modified power tables.

Signed-off-by: Yunus Bas <y.bas@phytec.de>
Signed-off-by: Primoz Fiser <primoz.fiser@norik.com>
---
 .../nxp/imx/imx6dl-phytec-mira-rdk-nand.dts   |  2 +-
 .../nxp/imx/imx6dl-phytec-phycore-som.dtsi    | 23 ++++++
 .../nxp/imx/imx6q-phytec-mira-rdk-emmc.dts    |  2 +-
 .../nxp/imx/imx6q-phytec-mira-rdk-nand.dts    |  2 +-
 .../dts/nxp/imx/imx6q-phytec-phycore-som.dtsi | 75 +++++++++++++++++++
 5 files changed, 101 insertions(+), 3 deletions(-)
 create mode 100644 arch/arm/boot/dts/nxp/imx/imx6dl-phytec-phycore-som.dtsi
 create mode 100644 arch/arm/boot/dts/nxp/imx/imx6q-phytec-phycore-som.dtsi

diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-phytec-mira-rdk-nand.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-phytec-mira-rdk-nand.dts
index d906a7f05aaa..8ec27080ca1e 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6dl-phytec-mira-rdk-nand.dts
+++ b/arch/arm/boot/dts/nxp/imx/imx6dl-phytec-mira-rdk-nand.dts
@@ -6,7 +6,7 @@
 
 /dts-v1/;
 #include "imx6dl.dtsi"
-#include "imx6qdl-phytec-phycore-som.dtsi"
+#include "imx6dl-phytec-phycore-som.dtsi"
 #include "imx6qdl-phytec-mira.dtsi"
 #include "imx6qdl-phytec-mira-peb-eval-01.dtsi"
 #include "imx6qdl-phytec-mira-peb-av-02.dtsi"
diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-phytec-phycore-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6dl-phytec-phycore-som.dtsi
new file mode 100644
index 000000000000..de85c084ac8d
--- /dev/null
+++ b/arch/arm/boot/dts/nxp/imx/imx6dl-phytec-phycore-som.dtsi
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2021 PHYTEC Messtechnik GmbH
+ * Author: Yunus Bas <y.bas@phytec.de>
+ */
+
+#include "imx6qdl-phytec-phycore-som.dtsi"
+
+&cpu0 {
+	operating-points =
+		/* kHz    uV */
+		<996000 1275000>,
+		<792000 1175000>,
+		<396000 1150000>;
+};
+
+&cpu1 {
+	operating-points =
+		/* kHz    uV */
+		<996000 1275000>,
+		<792000 1175000>,
+		<396000 1150000>;
+};
diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-phytec-mira-rdk-emmc.dts b/arch/arm/boot/dts/nxp/imx/imx6q-phytec-mira-rdk-emmc.dts
index 322f071d972f..7d947762f3b9 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6q-phytec-mira-rdk-emmc.dts
+++ b/arch/arm/boot/dts/nxp/imx/imx6q-phytec-mira-rdk-emmc.dts
@@ -6,7 +6,7 @@
 
 /dts-v1/;
 #include "imx6q.dtsi"
-#include "imx6qdl-phytec-phycore-som.dtsi"
+#include "imx6q-phytec-phycore-som.dtsi"
 #include "imx6qdl-phytec-mira.dtsi"
 #include "imx6qdl-phytec-mira-peb-eval-01.dtsi"
 #include "imx6qdl-phytec-mira-peb-av-02.dtsi"
diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-phytec-mira-rdk-nand.dts b/arch/arm/boot/dts/nxp/imx/imx6q-phytec-mira-rdk-nand.dts
index 3f13726c8058..afbb6681a6b5 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6q-phytec-mira-rdk-nand.dts
+++ b/arch/arm/boot/dts/nxp/imx/imx6q-phytec-mira-rdk-nand.dts
@@ -6,7 +6,7 @@
 
 /dts-v1/;
 #include "imx6q.dtsi"
-#include "imx6qdl-phytec-phycore-som.dtsi"
+#include "imx6q-phytec-phycore-som.dtsi"
 #include "imx6qdl-phytec-mira.dtsi"
 #include "imx6qdl-phytec-mira-peb-eval-01.dtsi"
 #include "imx6qdl-phytec-mira-peb-av-02.dtsi"
diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-phytec-phycore-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6q-phytec-phycore-som.dtsi
new file mode 100644
index 000000000000..ebe05d764357
--- /dev/null
+++ b/arch/arm/boot/dts/nxp/imx/imx6q-phytec-phycore-som.dtsi
@@ -0,0 +1,75 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2021 PHYTEC Messtechnik GmbH
+ * Author: Yunus Bas <y.bas@phytec.de>
+ */
+
+#include "imx6qdl-phytec-phycore-som.dtsi"
+
+&cpu0 {
+	operating-points =
+		/* kHz    uV */
+		<1200000 1300000>,
+		<996000  1250000>,
+		<852000  1250000>,
+		<792000  1175000>,
+		<396000  1075000>;
+	fsl,soc-operating-points =
+		/* ARM kHz  SOC-PU uV */
+		<1200000 1275000>,
+		<996000  1250000>,
+		<852000  1250000>,
+		<792000  1250000>,
+		<396000  1250000>;
+};
+
+&cpu1 {
+	operating-points =
+		/* kHz    uV */
+		<1200000 1300000>,
+		<996000  1250000>,
+		<852000  1250000>,
+		<792000  1175000>,
+		<396000  1075000>;
+	fsl,soc-operating-points =
+		/* ARM kHz  SOC-PU uV */
+		<1200000 1275000>,
+		<996000  1250000>,
+		<852000  1250000>,
+		<792000  1250000>,
+		<396000  1250000>;
+};
+
+&cpu2 {
+	operating-points =
+		/* kHz    uV */
+		<1200000 1300000>,
+		<996000  1250000>,
+		<852000  1250000>,
+		<792000  1175000>,
+		<396000  1075000>;
+	fsl,soc-operating-points =
+		/* ARM kHz  SOC-PU uV */
+		<1200000 1275000>,
+		<996000  1250000>,
+		<852000  1250000>,
+		<792000  1250000>,
+		<396000  1250000>;
+};
+
+&cpu3 {
+	operating-points =
+		/* kHz    uV */
+		<1200000 1300000>,
+		<996000  1250000>,
+		<852000  1250000>,
+		<792000  1175000>,
+		<396000  1075000>;
+	fsl,soc-operating-points =
+		/* ARM kHz  SOC-PU uV */
+		<1200000 1275000>,
+		<996000  1250000>,
+		<852000  1250000>,
+		<792000  1250000>,
+		<396000  1250000>;
+};
-- 
2.34.1

Re: [PATCH 2/2] ARM: dts: imx6qdl: phycore-som: Add custom volt/freq table

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] dts: imx6dl: missing fsl,soc-operating-points violates hardware constraint
--

commit a3b6d4e5af39862c78043d8917ba381472b78ee4
Author: Yunus Bas <y.bas@phytec.de>

    ARM: dts: imx6qdl: phycore-som: Add custom volt/freq table

The PHYTEC phyCORE-i.MX6QDL SOM-modules are operating with slightly different
voltage and frequency values. Introduce imx6q- and imx6dl-phycore dtsi files
with the modified power tables to achieve stable condition.

> diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-phytec-phycore-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6dl-phytec-phycore-som.dtsi
> new file mode 100644
> index 0000000000000..de85c084ac8d3
> --- /dev/null
> +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-phytec-phycore-som.dtsi
> @@ -0,0 +1,23 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (C) 2021 PHYTEC Messtechnik GmbH
> + * Author: Yunus Bas <y.bas@phytec.de>
> + */
> +
> +#include "imx6qdl-phytec-phycore-som.dtsi"
> +
> +&cpu0 {
> +	operating-points =
> +		/* kHz    uV */
> +		<996000 1275000>,
                ^^^^^^^^^^^^^^^^
[Severity: High]
This overrides the operating-points to increase VDD_ARM to 1.275V for the
996MHz tier, but lacks a corresponding fsl,soc-operating-points override.

Without it, VDD_SOC will inherit the default 1.175V from imx6dl.dtsi.

The NXP i.MX6 DualLite hardware datasheet specifies that VDD_ARM_IN must not
exceed VDD_SOC_IN by more than 50mV to prevent latch-up and instability.

Does this 100mV gap risk system instability or hardware damage by violating
this constraint? Note that the newly added imx6q-phytec-phycore-som.dtsi
correctly includes the fsl,soc-operating-points property.

> +		<792000 1175000>,
> +		<396000 1150000>;
> +};

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260923070505.494949-1-primoz.fiser@norik.com?part=2

Re: [PATCH 2/2] ARM: dts: imx6qdl: phycore-som: Add custom volt/freq table

[Primoz Fiser]

On 9/23/26 09:45, sashiko-bot@kernel.org wrote:
> Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
> - [High] dts: imx6dl: missing fsl,soc-operating-points violates hardware constraint
> --
> 
> commit a3b6d4e5af39862c78043d8917ba381472b78ee4
> Author: Yunus Bas <y.bas@phytec.de>
> 
>     ARM: dts: imx6qdl: phycore-som: Add custom volt/freq table
> 
> The PHYTEC phyCORE-i.MX6QDL SOM-modules are operating with slightly different
> voltage and frequency values. Introduce imx6q- and imx6dl-phycore dtsi files
> with the modified power tables to achieve stable condition.
> 
>> diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-phytec-phycore-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6dl-phytec-phycore-som.dtsi
>> new file mode 100644
>> index 0000000000000..de85c084ac8d3
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-phytec-phycore-som.dtsi
>> @@ -0,0 +1,23 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>> +/*
>> + * Copyright (C) 2021 PHYTEC Messtechnik GmbH
>> + * Author: Yunus Bas <y.bas@phytec.de>
>> + */
>> +
>> +#include "imx6qdl-phytec-phycore-som.dtsi"
>> +
>> +&cpu0 {
>> +	operating-points =
>> +		/* kHz    uV */
>> +		<996000 1275000>,
>                 ^^^^^^^^^^^^^^^^
> [Severity: High]
> This overrides the operating-points to increase VDD_ARM to 1.275V for the
> 996MHz tier, but lacks a corresponding fsl,soc-operating-points override.
> 
> Without it, VDD_SOC will inherit the default 1.175V from imx6dl.dtsi.
> 
> The NXP i.MX6 DualLite hardware datasheet specifies that VDD_ARM_IN must not
> exceed VDD_SOC_IN by more than 50mV to prevent latch-up and instability.
> 
> Does this 100mV gap risk system instability or hardware damage by violating
> this constraint? Note that the newly added imx6q-phytec-phycore-som.dtsi
> correctly includes the fsl,soc-operating-points property.

From the i.MX6DL datasheet:

footnote 4:

"In LDO enabled mode, the internal LDO output set points must be
configured such that the VDD_ARM LDO output set point does not exceed
the VDD_SOC LDO output set point by more than 100 mV"

footnote 6:

"In LDO bypassed mode, the external power supply must ensure that
VDD_ARM_IN does not exceed VDD_SOC_IN by more than 100 mV."

The actual limit is thus 100 mV, not 50 mV! Can you provide quote
regarding your 50 mV?

With this override, the only affected tier is the top one (996 MHz):
VDD_ARM = 1.275 V, VDD_SOC (inherited from imx6dl.dtsi's default
fsl,soc-operating-points) = 1.175 V, a gap of exactly 100 mV...

So this is still within limits hence no fsl,soc-operating-points
override is required here IMHO.

Moreover, PHYTEC boards using downstream kernel with this patch applied
have been operating with such settings for years now without issues.

BR,
Primoz


> 
>> +		<792000 1175000>,
>> +		<396000 1150000>;
>> +};
> 

-- 
Primoz Fiser
phone: +386-41-390-545
email: primoz.fiser@norik.com
--
Norik systems d.o.o.
Your embedded software partner
Slovenia, EU
phone: +386-41-540-545
email: info@norik.com

Re: [PATCH 0/2] ARM: dts: phyCORE-i.MX6 custom OPP table

[Frank.Li]

From: Frank Li <Frank.Li@nxp.com>


On Wed, 23 Sep 2026 09:05:03 +0200, Primoz Fiser wrote:
> This is a revival of a series originally posted by Yunus Bas in
> February 2022 [1][2]. It adds a label to the imx6dl cpu1 node and
> introduces phyCORE-i.MX6 SOM specific operating-points tables, since
> the phyCORE modules run at slightly different voltage/frequency values
> than the generic i.MX6Q/DL tables.
> 
> [1] https://lore.kernel.org/all/20220209223258.1672425-1-y.bas@phytec.de/
> [2] https://lore.kernel.org/all/20220209223258.1672425-2-y.bas@phytec.de/
> 
> [...]

Applied, thanks!

[1/2] ARM: dts: imx6dl: Add a label to cpu1 node
      commit: dcbe9b512afacb9a6ee8966b8129861e02256a8f
[2/2] ARM: dts: imx6qdl: phycore-som: Add custom volt/freq table
      commit: bf2f5dba1ff19d575eb9917c7722bf095724f4a6

Best regards,
-- 
Frank Li <Frank.Li@nxp.com>