* [PATCH v2] arm64: dts: qcom: nord: Add adreno SMMU nodes
@ 2026-09-24 8:48 Shawn Guo
2026-09-24 8:53 ` sashiko-bot
2026-09-24 9:54 ` Shawn Guo
0 siblings, 2 replies; 3+ messages in thread
From: Shawn Guo @ 2026-09-24 8:48 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Bartosz Golaszewski, devicetree, linux-arm-msm, linux-kernel,
Bibek Kumar Patro, Bartosz Golaszewski, Konrad Dybcio, Shawn Guo
From: Bibek Kumar Patro <bibek.patro@oss.qualcomm.com>
Add the Adreno GPU SMMMUs (MMU-500) for both GPU instances.
Wire up the gpucc clock and power domain on both adreno SMMU nodes in
nord-embedded.dtsi for embedded Nord variants where gpucc is available.
Signed-off-by: Bibek Kumar Patro <bibek.patro@oss.qualcomm.com>
Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
---
Dependencies:
- SMMU binding: https://lore.kernel.org/all/20260902013858.130887-1-shengchao.guo@oss.qualcomm.com/
Changes for v2:
- Fix adreno_smmu_0 interrupts, 673 -> 674 (Thanks Konrad!)
- Link to v1: https://lore.kernel.org/all/20260922111354.533902-1-shengchao.guo@oss.qualcomm.com/
arch/arm64/boot/dts/qcom/nord.dtsi | 74 ++++++++++++++++++++++++++++++
1 file changed, 74 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/nord.dtsi b/arch/arm64/boot/dts/qcom/nord.dtsi
index e0496fd40c30..376ae1604175 100644
--- a/arch/arm64/boot/dts/qcom/nord.dtsi
+++ b/arch/arm64/boot/dts/qcom/nord.dtsi
@@ -1518,6 +1518,80 @@ tcsr: syscon@1f60000 {
reg = <0x0 0x01f60000 0x0 0xa0000>;
};
+ adreno_smmu_0: iommu@3da0000 {
+ compatible = "qcom,nord-smmu-500",
+ "qcom,adreno-smmu",
+ "qcom,smmu-500",
+ "arm,mmu-500";
+ reg = <0x0 0x03da0000 0x0 0x40000>;
+ #iommu-cells = <2>;
+ #global-interrupts = <1>;
+ interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 660 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 662 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 667 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 670 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 700 IRQ_TYPE_LEVEL_HIGH>;
+ dma-coherent;
+ };
+
+ adreno_smmu_1: iommu@98a0000 {
+ compatible = "qcom,nord-smmu-500",
+ "qcom,adreno-smmu",
+ "qcom,smmu-500",
+ "arm,mmu-500";
+ reg = <0x0 0x098a0000 0x0 0x40000>;
+ #iommu-cells = <2>;
+ #global-interrupts = <1>;
+ interrupts = <GIC_SPI 932 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 936 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 937 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 938 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 939 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 940 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 941 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 942 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 924 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 925 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 926 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 927 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 928 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 929 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 920 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 921 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 922 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 851 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 854 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 855 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 857 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 859 IRQ_TYPE_LEVEL_HIGH>;
+ dma-coherent;
+ };
+
pdc: interrupt-controller@b220000 {
compatible = "qcom,nord-pdc",
"qcom,pdc";
--
2.43.0
^ permalink raw reply related [flat|nested] 3+ messages in thread* Re: [PATCH v2] arm64: dts: qcom: nord: Add adreno SMMU nodes
2026-09-24 8:48 [PATCH v2] arm64: dts: qcom: nord: Add adreno SMMU nodes Shawn Guo
@ 2026-09-24 8:53 ` sashiko-bot
2026-09-24 9:54 ` Shawn Guo
1 sibling, 0 replies; 3+ messages in thread
From: sashiko-bot @ 2026-09-24 8:53 UTC (permalink / raw)
To: Shawn Guo; +Cc: devicetree, conor+dt, robh
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] dts: missing nord-embedded.dtsi changes for adreno SMMU nodes
--
commit a2c0ee3a850e499db0187f8a73a66cb5ce9ccf9c
Author: Bibek Kumar Patro <bibek.patro@oss.qualcomm.com>
arm64: dts: qcom: nord: Add adreno SMMU nodes
Add the Adreno GPU SMMMUs (MMU-500) for both GPU instances.
> diff --git a/arch/arm64/boot/dts/qcom/nord.dtsi b/arch/arm64/boot/dts/qcom/nord.dtsi
> index e0496fd40c308..376ae16041752 100644
> --- a/arch/arm64/boot/dts/qcom/nord.dtsi
> +++ b/arch/arm64/boot/dts/qcom/nord.dtsi
> @@ -1518,6 +1518,80 @@ tcsr: syscon@1f60000 {
> reg = <0x0 0x01f60000 0x0 0xa0000>;
> };
>
> + adreno_smmu_0: iommu@3da0000 {
> + compatible = "qcom,nord-smmu-500",
> + "qcom,adreno-smmu",
> + "qcom,smmu-500",
> + "arm,mmu-500";
> + reg = <0x0 0x03da0000 0x0 0x40000>;
[Severity: Medium]
The commit message states that the gpucc clock and power domain are wired up
in nord-embedded.dtsi for these adreno SMMU nodes.
However, this patch only modifies nord.dtsi and omits the intended changes
to nord-embedded.dtsi. When probing the adreno SMMU on embedded Nord variants
that rely on gpucc, are the clock and power domain properties missing for
adreno_smmu_0 in arch/arm64/boot/dts/qcom/nord.dtsi?
Could this lead to driver probe failures or hardware aborts?
[ ... ]
> + adreno_smmu_1: iommu@98a0000 {
> + compatible = "qcom,nord-smmu-500",
[Severity: Medium]
Similarly, when probing adreno_smmu_1 in arch/arm64/boot/dts/qcom/nord.dtsi,
is this base node also missing the clock and power domain properties that
were intended to be specified in nord-embedded.dtsi?
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260924084805.1021758-1-shengchao.guo@oss.qualcomm.com?part=1
^ permalink raw reply [flat|nested] 3+ messages in thread* Re: [PATCH v2] arm64: dts: qcom: nord: Add adreno SMMU nodes
2026-09-24 8:48 [PATCH v2] arm64: dts: qcom: nord: Add adreno SMMU nodes Shawn Guo
2026-09-24 8:53 ` sashiko-bot
@ 2026-09-24 9:54 ` Shawn Guo
1 sibling, 0 replies; 3+ messages in thread
From: Shawn Guo @ 2026-09-24 9:54 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Bartosz Golaszewski, devicetree, linux-arm-msm, linux-kernel,
Bibek Kumar Patro, Bartosz Golaszewski, Konrad Dybcio
On Thu, Sep 24, 2026 at 04:48:05PM +0800, Shawn Guo wrote:
> From: Bibek Kumar Patro <bibek.patro@oss.qualcomm.com>
>
> Add the Adreno GPU SMMMUs (MMU-500) for both GPU instances.
>
> Wire up the gpucc clock and power domain on both adreno SMMU nodes in
> nord-embedded.dtsi for embedded Nord variants where gpucc is available.
Oops! The nord-embedded.dtsi changes got lost. Will fix in v3.
Shawn
>
> Signed-off-by: Bibek Kumar Patro <bibek.patro@oss.qualcomm.com>
> Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
^ permalink raw reply [flat|nested] 3+ messages in thread
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2026-09-24 8:48 [PATCH v2] arm64: dts: qcom: nord: Add adreno SMMU nodes Shawn Guo
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