* [PATCH v5 1/6] dt-bindings: vendor-prefixes: Add Tibbo
2026-09-24 16:49 [PATCH v5 0/6] arm: sunplus: add Tibbo LTPP3G2 board support Andrew Gaylard
@ 2026-09-24 16:49 ` Andrew Gaylard
2026-09-25 16:49 ` Conor Dooley
2026-09-24 16:49 ` [PATCH v5 2/6] dt-bindings: arm: sunplus: add Tibbo LTPP3G2 board compatible string Andrew Gaylard
` (4 subsequent siblings)
5 siblings, 1 reply; 9+ messages in thread
From: Andrew Gaylard @ 2026-09-24 16:49 UTC (permalink / raw)
To: linux-arm-kernel
Cc: devicetree, qinjian, robh, krzk+dt, conor+dt, linux,
Andrew Gaylard
Add the vendor prefix for Tibbo Technology, the LTPP3G2 board manufacturer.
Signed-off-by: Andrew Gaylard <ag@ffroot.co.za>
---
Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index 4a5cf436eb14..8a984fea11c3 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -1728,6 +1728,8 @@ patternProperties:
description: Texas Instruments
"^tianma,.*":
description: Tianma Micro-electronics Co., Ltd.
+ "^tibbo,.*":
+ description: Tibbo Technology Inc.
"^tlm,.*":
description: Trusted Logic Mobility
"^tmt,.*":
--
2.53.0
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH v5 1/6] dt-bindings: vendor-prefixes: Add Tibbo
2026-09-24 16:49 ` [PATCH v5 1/6] dt-bindings: vendor-prefixes: Add Tibbo Andrew Gaylard
@ 2026-09-25 16:49 ` Conor Dooley
0 siblings, 0 replies; 9+ messages in thread
From: Conor Dooley @ 2026-09-25 16:49 UTC (permalink / raw)
To: Andrew Gaylard
Cc: linux-arm-kernel, devicetree, qinjian, robh, krzk+dt, conor+dt,
linux
[-- Attachment #1: Type: text/plain, Size: 1040 bytes --]
On Thu, Sep 24, 2026 at 06:49:17PM +0200, Andrew Gaylard wrote:
> Add the vendor prefix for Tibbo Technology, the LTPP3G2 board manufacturer.
>
> Signed-off-by: Andrew Gaylard <ag@ffroot.co.za>
Link: https://tibbo.com/
Acked-by: Conor Dooley <conor.dooley@microchip.com>
pw-bot: not-applicable
> ---
> Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
> index 4a5cf436eb14..8a984fea11c3 100644
> --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
> +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
> @@ -1728,6 +1728,8 @@ patternProperties:
> description: Texas Instruments
> "^tianma,.*":
> description: Tianma Micro-electronics Co., Ltd.
> + "^tibbo,.*":
> + description: Tibbo Technology Inc.
> "^tlm,.*":
> description: Trusted Logic Mobility
> "^tmt,.*":
> --
> 2.53.0
>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v5 2/6] dt-bindings: arm: sunplus: add Tibbo LTPP3G2 board compatible string
2026-09-24 16:49 [PATCH v5 0/6] arm: sunplus: add Tibbo LTPP3G2 board support Andrew Gaylard
2026-09-24 16:49 ` [PATCH v5 1/6] dt-bindings: vendor-prefixes: Add Tibbo Andrew Gaylard
@ 2026-09-24 16:49 ` Andrew Gaylard
2026-09-25 16:50 ` Conor Dooley
2026-09-24 16:49 ` [PATCH v5 3/6] arm: dts: sunplus: add PWM, watchdog and MMC nodes to SP7021 DTSI Andrew Gaylard
` (3 subsequent siblings)
5 siblings, 1 reply; 9+ messages in thread
From: Andrew Gaylard @ 2026-09-24 16:49 UTC (permalink / raw)
To: linux-arm-kernel
Cc: devicetree, qinjian, robh, krzk+dt, conor+dt, linux,
Andrew Gaylard
Add tibbo,ltpp3g2 to the list of compatible boards for the Sunplus
SP7021 SoC binding.
Signed-off-by: Andrew Gaylard <ag@ffroot.co.za>
---
Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml b/Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml
index def7d0cfeb31..8ec006576f74 100644
--- a/Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml
+++ b/Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml
@@ -9,6 +9,7 @@ title: Sunplus SP7021 Boards
maintainers:
- qinjian <qinjian@cqplus1.com>
+ - Andrew Gaylard <ag@ffroot.co.za>
description: |
ARM platforms using Sunplus SP7021, an ARM Cortex A7 (4-cores) based SoC.
@@ -22,6 +23,7 @@ properties:
- enum:
- sunplus,sp7021-achip
- sunplus,sp7021-demo-v3
+ - tibbo,ltpp3g2
- const: sunplus,sp7021
additionalProperties: true
--
2.53.0
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH v5 3/6] arm: dts: sunplus: add PWM, watchdog and MMC nodes to SP7021 DTSI
2026-09-24 16:49 [PATCH v5 0/6] arm: sunplus: add Tibbo LTPP3G2 board support Andrew Gaylard
2026-09-24 16:49 ` [PATCH v5 1/6] dt-bindings: vendor-prefixes: Add Tibbo Andrew Gaylard
2026-09-24 16:49 ` [PATCH v5 2/6] dt-bindings: arm: sunplus: add Tibbo LTPP3G2 board compatible string Andrew Gaylard
@ 2026-09-24 16:49 ` Andrew Gaylard
2026-09-24 16:49 ` [PATCH v5 4/6] arm: sunplus: enable SMP via PSCI on SP7021 Andrew Gaylard
` (2 subsequent siblings)
5 siblings, 0 replies; 9+ messages in thread
From: Andrew Gaylard @ 2026-09-24 16:49 UTC (permalink / raw)
To: linux-arm-kernel
Cc: devicetree, qinjian, robh, krzk+dt, conor+dt, linux,
Andrew Gaylard
Add device nodes for the peripherals that have upstream drivers:
- PWM controller
- Watchdog controller
- eMMC controller
Add a label to the gpio-leds node so board DTS files can override it.
Move the memory node from the DTS into the DTSI; this chip has the RAM
integrated and it's not possible to add external RAM.
Remove three board-specific pinmux nodes that do not belong in the DTSI:
- emmc_pins: eMMC pinmux, moved to the LTPP3G2 board DTS.
- sdcard_pins: SD card pinmux; the SD driver is not yet implemented.
- emac_pins: Ethernet pinmux, will be defined in board DTS files that
enable ethernet.
Signed-off-by: Andrew Gaylard <ag@ffroot.co.za>
---
.../dts/sunplus/sunplus-sp7021-demo-v3.dts | 4 -
arch/arm/boot/dts/sunplus/sunplus-sp7021.dtsi | 74 ++++++++-----------
2 files changed, 32 insertions(+), 46 deletions(-)
diff --git a/arch/arm/boot/dts/sunplus/sunplus-sp7021-demo-v3.dts b/arch/arm/boot/dts/sunplus/sunplus-sp7021-demo-v3.dts
index d5c5ffc20565..d764fc1f946e 100644
--- a/arch/arm/boot/dts/sunplus/sunplus-sp7021-demo-v3.dts
+++ b/arch/arm/boot/dts/sunplus/sunplus-sp7021-demo-v3.dts
@@ -23,8 +23,4 @@ chosen {
stdout-path = "serial0:115200n8";
};
- memory@0 {
- device_type = "memory";
- reg = <0x00000000 0x20000000>;
- };
};
diff --git a/arch/arm/boot/dts/sunplus/sunplus-sp7021.dtsi b/arch/arm/boot/dts/sunplus/sunplus-sp7021.dtsi
index ae9bbe0320b8..9963501b6a41 100644
--- a/arch/arm/boot/dts/sunplus/sunplus-sp7021.dtsi
+++ b/arch/arm/boot/dts/sunplus/sunplus-sp7021.dtsi
@@ -17,6 +17,11 @@ / {
compatible = "sunplus,sp7021";
model = "Sunplus SP7021";
+ memory@0 {
+ device_type = "memory";
+ reg = <0x00000000 0x20000000>; /* 512MB integrated */
+ };
+
clocks {
extclk: osc0 {
compatible = "fixed-clock";
@@ -84,50 +89,10 @@ pctl: pinctrl@100 {
clocks = <&clkc CLK_GPIO>;
resets = <&rstc RST_GPIO>;
- emac_pins: pinmux-emac-pins {
- sunplus,pins = <
- SPPCTL_IOPAD(49,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_CLK_OUT,0)
- SPPCTL_IOPAD(44,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_MAC_SMI_MDC,0)
- SPPCTL_IOPAD(43,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_MAC_SMI_MDIO,0)
- SPPCTL_IOPAD(52,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_TXEN,0)
- SPPCTL_IOPAD(50,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_TXD0,0)
- SPPCTL_IOPAD(51,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_TXD1,0)
- SPPCTL_IOPAD(46,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_CRSDV,0)
- SPPCTL_IOPAD(47,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_RXD0,0)
- SPPCTL_IOPAD(48,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_RXD1,0)
- SPPCTL_IOPAD(45,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_RXER,0)
- SPPCTL_IOPAD(59,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P1_MAC_RMII_TXEN,0)
- SPPCTL_IOPAD(57,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P1_MAC_RMII_TXD0,0)
- SPPCTL_IOPAD(58,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P1_MAC_RMII_TXD1,0)
- SPPCTL_IOPAD(54,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P1_MAC_RMII_CRSDV,0)
- SPPCTL_IOPAD(55,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P1_MAC_RMII_RXD0,0)
- SPPCTL_IOPAD(56,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P1_MAC_RMII_RXD1,0)
- SPPCTL_IOPAD(53,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P1_MAC_RMII_RXER,0)
- >;
- sunplus,zerofunc = <
- MUXF_L2SW_LED_FLASH0
- MUXF_L2SW_LED_FLASH1
- MUXF_L2SW_LED_ON0
- MUXF_L2SW_LED_ON1
- MUXF_DAISY_MODE
- >;
- };
-
- emmc_pins: pinmux-emmc-pins {
- function = "CARD0_EMMC";
- groups = "CARD0_EMMC";
- };
-
leds_pins: pinmux-leds-pins {
sunplus,pins = < SPPCTL_IOPAD(0,SPPCTL_PCTL_G_GPIO,0,SPPCTL_PCTL_L_OUT) >;
};
- sdcard_pins: pinmux-sdcard-pins {
- function = "SD_CARD";
- groups = "SD_CARD";
- sunplus,pins = < SPPCTL_IOPAD(91, SPPCTL_PCTL_G_GPIO, 0, 0) >;
- };
-
spi0_pins: pinmux-spi0-pins {
sunplus,pins = <
SPPCTL_IOPAD(26,SPPCTL_PCTL_G_GPIO,0,0)
@@ -291,13 +256,38 @@ uart4: serial@8780 {
pinctrl-0 = <&uart4_pins>;
status = "disabled";
};
+
+ pwm: pwm@7a00 {
+ #pwm-cells = <2>;
+ compatible = "sunplus,sp7021-pwm";
+ reg = <0x7a00 0x80>;
+ clocks = <&clkc CLK_DISP_PWM>;
+ status = "disabled";
+ };
+
+ wdt: watchdog@630 {
+ compatible = "sunplus,sp7021-wdt";
+ reg = <0x630 0x08>, <0x274 0x04>;
+ clocks = <&clkc CLK_STC0>;
+ resets = <&rstc RST_STC0>;
+ status = "disabled";
+ };
+
+ mmc0: mmc@3b00 {
+ compatible = "sunplus,sp7021-mmc";
+ reg = <0x3b00 0x180>;
+ interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clkc CLK_CARD_CTL0>;
+ resets = <&rstc RST_CARD_CTL0>;
+ status = "disabled";
+ };
};
- leds {
+ leds: leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&leds_pins>;
- system-led {
+ led-0 {
label = "system-led";
gpios = <&pctl 0 GPIO_ACTIVE_HIGH>;
default-state = "off";
--
2.53.0
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH v5 4/6] arm: sunplus: enable SMP via PSCI on SP7021
2026-09-24 16:49 [PATCH v5 0/6] arm: sunplus: add Tibbo LTPP3G2 board support Andrew Gaylard
` (2 preceding siblings ...)
2026-09-24 16:49 ` [PATCH v5 3/6] arm: dts: sunplus: add PWM, watchdog and MMC nodes to SP7021 DTSI Andrew Gaylard
@ 2026-09-24 16:49 ` Andrew Gaylard
2026-09-24 16:49 ` [PATCH v5 5/6] arm: dts: sunplus: add Tibbo LTPP3G2 board Andrew Gaylard
2026-09-24 16:49 ` [PATCH v5 6/6] configs: sp7021: fix defaults and enable existing device drivers Andrew Gaylard
5 siblings, 0 replies; 9+ messages in thread
From: Andrew Gaylard @ 2026-09-24 16:49 UTC (permalink / raw)
To: linux-arm-kernel
Cc: devicetree, qinjian, robh, krzk+dt, conor+dt, linux,
Andrew Gaylard
The SP7021 firmware implements PSCI 0.2 via SMC. Add the psci node
and enable-method = "psci" on each CPU node to allow the kernel to
bring up all four Cortex-A7 cores.
Verified by boot log: "psci: SMC Calling Convention v1.0" and
"smp: Brought up 1 node, 4 CPUs".
Signed-off-by: Andrew Gaylard <ag@ffroot.co.za>
---
arch/arm/boot/dts/sunplus/sunplus-sp7021-achip.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/sunplus/sunplus-sp7021-achip.dtsi b/arch/arm/boot/dts/sunplus/sunplus-sp7021-achip.dtsi
index 493d32357e4e..b73cfde7ace4 100644
--- a/arch/arm/boot/dts/sunplus/sunplus-sp7021-achip.dtsi
+++ b/arch/arm/boot/dts/sunplus/sunplus-sp7021-achip.dtsi
@@ -24,27 +24,36 @@ cpu0: cpu@0 {
device_type = "cpu";
reg = <0>;
clock-frequency = <931000000>;
+ enable-method = "psci";
};
cpu1: cpu@1 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <1>;
clock-frequency = <931000000>;
+ enable-method = "psci";
};
cpu2: cpu@2 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <2>;
clock-frequency = <931000000>;
+ enable-method = "psci";
};
cpu3: cpu@3 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <3>;
clock-frequency = <931000000>;
+ enable-method = "psci";
};
};
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
gic: interrupt-controller@9f101000 {
compatible = "arm,cortex-a7-gic";
interrupt-controller;
--
2.53.0
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH v5 5/6] arm: dts: sunplus: add Tibbo LTPP3G2 board
2026-09-24 16:49 [PATCH v5 0/6] arm: sunplus: add Tibbo LTPP3G2 board support Andrew Gaylard
` (3 preceding siblings ...)
2026-09-24 16:49 ` [PATCH v5 4/6] arm: sunplus: enable SMP via PSCI on SP7021 Andrew Gaylard
@ 2026-09-24 16:49 ` Andrew Gaylard
2026-09-24 16:49 ` [PATCH v5 6/6] configs: sp7021: fix defaults and enable existing device drivers Andrew Gaylard
5 siblings, 0 replies; 9+ messages in thread
From: Andrew Gaylard @ 2026-09-24 16:49 UTC (permalink / raw)
To: linux-arm-kernel
Cc: devicetree, qinjian, robh, krzk+dt, conor+dt, linux,
Andrew Gaylard
Add a DTS for the Tibbo LTPP3G2 board, which uses the Sunplus SP7021
SoC. The initial DTS was provided by Sunplus Technology Co. and has
been adapted for upstream with permission.
The board features eMMC, SPI, a bit-banged I2C EEPROM (Atmel 24C16),
PWM output to a buzzer, a watchdog, RTC, and two GPIO LEDs (heartbeat
and MMC activity).
Signed-off-by: Andrew Gaylard <ag@ffroot.co.za>
---
MAINTAINERS | 6 +
arch/arm/boot/dts/sunplus/Makefile | 5 +-
.../dts/sunplus/sunplus-sp7021-ltpp3g2.dts | 193 ++++++++++++++++++
3 files changed, 201 insertions(+), 3 deletions(-)
create mode 100644 arch/arm/boot/dts/sunplus/sunplus-sp7021-ltpp3g2.dts
diff --git a/MAINTAINERS b/MAINTAINERS
index 6e50747a621c..313107bea748 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3737,6 +3737,12 @@ F: drivers/reset/reset-sunplus.c
F: include/dt-bindings/clock/sunplus,sp7021-clkc.h
F: include/dt-bindings/reset/sunplus,sp7021-reset.h
+ARM/TIBBO LTPP3G2 BOARD
+M: Andrew Gaylard <ag@ffroot.co.za>
+L: linux-arm-kernel@lists.infradead.org
+S: Maintained
+F: arch/arm/boot/dts/sunplus/sunplus-sp7021-ltpp3g2.dts
+
ARM/Synaptics SoC support
M: Jisheng Zhang <jszhang@kernel.org>
M: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
diff --git a/arch/arm/boot/dts/sunplus/Makefile b/arch/arm/boot/dts/sunplus/Makefile
index 868f2ea0c127..25ba2e530c35 100644
--- a/arch/arm/boot/dts/sunplus/Makefile
+++ b/arch/arm/boot/dts/sunplus/Makefile
@@ -1,5 +1,4 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_SOC_SP7021) += \
- sunplus-sp7021-demo-v3.dtb
-dtb-$(CONFIG_SOC_SP7021) += \
- sunplus-sp7021-demo-v3.dtb
+ sunplus-sp7021-demo-v3.dtb \
+ sunplus-sp7021-ltpp3g2.dtb
diff --git a/arch/arm/boot/dts/sunplus/sunplus-sp7021-ltpp3g2.dts b/arch/arm/boot/dts/sunplus/sunplus-sp7021-ltpp3g2.dts
new file mode 100644
index 000000000000..2d321c41067c
--- /dev/null
+++ b/arch/arm/boot/dts/sunplus/sunplus-sp7021-ltpp3g2.dts
@@ -0,0 +1,193 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for Tibbo LTPP board G2
+ *
+ * Copyright (C) 2021 Sunplus Technology Co.
+ */
+
+/dts-v1/;
+
+#include "sunplus-sp7021-achip.dtsi"
+
+/ {
+ compatible = "tibbo,ltpp3g2", "sunplus,sp7021";
+ model = "Tibbo LTPP3G2";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ i2c_tps: i2c {
+ compatible = "i2c-gpio";
+ sda-gpios = <&pctl 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&pctl 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ i2c-gpio,delay-us = <5>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pins_i2ctps>;
+ eeprom: eeprom@50 {
+ compatible = "atmel,24c16";
+ reg = <0x50>;
+ pagesize = <16>;
+ };
+ };
+};
+
+&leds {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&gpio_leds_pins>;
+ pinctrl-1 = <&leds_s0_slp>;
+ led-0 {
+ label = "system-led";
+ gpios = <&pctl 6 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ linux,default-trigger = "heartbeat";
+ };
+ led-1 {
+ label = "SG";
+ gpios = <&pctl 7 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "mmc0";
+ default-state = "off";
+ };
+};
+
+&pwm {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pins_pwm>;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pins_uart1>;
+ status = "disabled";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pins_uart2>;
+ status = "disabled";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pins_uart3>;
+ status = "disabled";
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pins_btuart &pins_bt_reset>;
+ status = "disabled";
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_pins>;
+ bus-width = <8>;
+ max-frequency = <52000000>;
+ non-removable;
+ disable-wp;
+ cap-mmc-highspeed;
+ mmc-ddr-3_3v;
+ no-sdio;
+ no-sd;
+ status = "okay";
+};
+
+&wdt {
+ status = "okay";
+};
+
+&pctl {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pins_gpio_nobinded>;
+
+ emmc_pins: pinmux-emmc-pins {
+ function = "CARD0_EMMC";
+ groups = "CARD0_EMMC";
+ };
+
+ pins_pwm: pinmux-pwm-pins {
+ sunplus,pins = <
+ SPPCTL_IOPAD(48, SPPCTL_PCTL_G_PMUX, MUXF_PWM0, 0)
+ >;
+ };
+
+ pins_gpio_nobinded: pinmux-gpio-nobinded-pins {
+ sunplus,pins = <
+ SPPCTL_IOPAD(30, SPPCTL_PCTL_G_GPIO, 0, 0) /* was L2SW_LED_FLASH1 */
+ SPPCTL_IOPAD(39, SPPCTL_PCTL_G_GPIO, 0, 0) /* was L2SW_LED_ON1 */
+ >;
+ };
+
+ pins_i2ctps: pinmux-i2c-pins {
+ sunplus,pins = <
+ SPPCTL_IOPAD(1, SPPCTL_PCTL_G_GPIO, 0,
+ SPPCTL_PCTL_L_OU1 | SPPCTL_PCTL_L_ODR)
+ SPPCTL_IOPAD(2, SPPCTL_PCTL_G_GPIO, 0,
+ SPPCTL_PCTL_L_OU1 | SPPCTL_PCTL_L_ODR)
+ >;
+ };
+
+ gpio_leds_pins: pinmux-gpio-leds-pins {
+ sunplus,pins = <
+ SPPCTL_IOPAD(6, SPPCTL_PCTL_G_GPIO, 0, SPPCTL_PCTL_L_OUT)
+ SPPCTL_IOPAD(7, SPPCTL_PCTL_G_GPIO, 0, SPPCTL_PCTL_L_OUT)
+ >;
+ };
+
+ leds_s0_slp: pinmux-user-leds-s0-slp-pins {
+ sunplus,pins = <
+ SPPCTL_IOPAD(6, SPPCTL_PCTL_G_GPIO, 0, 0)
+ SPPCTL_IOPAD(7, SPPCTL_PCTL_G_GPIO, 0, 0)
+ >;
+ };
+
+ pins_uart1: pinmux-uart1-pins {
+ sunplus,pins = <
+ SPPCTL_IOPAD(8, SPPCTL_PCTL_G_PMUX, MUXF_UA1_TX, 0)
+ SPPCTL_IOPAD(9, SPPCTL_PCTL_G_PMUX, MUXF_UA1_RX, 0)
+ SPPCTL_IOPAD(10, SPPCTL_PCTL_G_PMUX, MUXF_UA1_RTS, 0)
+ SPPCTL_IOPAD(11, SPPCTL_PCTL_G_PMUX, MUXF_UA1_CTS, 0)
+ >;
+ };
+
+ pins_uart2: pinmux-uart2-pins {
+ sunplus,pins = <
+ SPPCTL_IOPAD(12, SPPCTL_PCTL_G_PMUX, MUXF_UA2_TX, 0)
+ SPPCTL_IOPAD(13, SPPCTL_PCTL_G_PMUX, MUXF_UA2_RX, 0)
+ SPPCTL_IOPAD(14, SPPCTL_PCTL_G_PMUX, MUXF_UA2_RTS, 0)
+ SPPCTL_IOPAD(15, SPPCTL_PCTL_G_PMUX, MUXF_UA2_CTS, 0)
+ >;
+ };
+
+ pins_uart3: pinmux-uart3-pins {
+ sunplus,pins = <
+ SPPCTL_IOPAD(16, SPPCTL_PCTL_G_PMUX, MUXF_UA3_TX, 0)
+ SPPCTL_IOPAD(17, SPPCTL_PCTL_G_PMUX, MUXF_UA3_RX, 0)
+ SPPCTL_IOPAD(18, SPPCTL_PCTL_G_PMUX, MUXF_UA3_RTS, 0)
+ SPPCTL_IOPAD(19, SPPCTL_PCTL_G_PMUX, MUXF_UA3_CTS, 0)
+ >;
+ };
+
+ /* AP6256 Bluetooth */
+ pins_btuart: pinmux-btuart-pins {
+ sunplus,pins = <
+ SPPCTL_IOPAD(40, SPPCTL_PCTL_G_PMUX, MUXF_UA4_RX, 0)
+ SPPCTL_IOPAD(41, SPPCTL_PCTL_G_PMUX, MUXF_UA4_TX, 0)
+ SPPCTL_IOPAD(56, SPPCTL_PCTL_G_PMUX, MUXF_UA4_RTS, 0)
+ SPPCTL_IOPAD(49, SPPCTL_PCTL_G_PMUX, MUXF_UA4_CTS, 0)
+ >;
+ };
+
+ pins_bt_reset: pinmux-bt-reset-pins {
+ sunplus,pins = < SPPCTL_IOPAD(82, SPPCTL_PCTL_G_GPIO, 0, 0) >;
+ };
+
+};
--
2.53.0
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH v5 6/6] configs: sp7021: fix defaults and enable existing device drivers
2026-09-24 16:49 [PATCH v5 0/6] arm: sunplus: add Tibbo LTPP3G2 board support Andrew Gaylard
` (4 preceding siblings ...)
2026-09-24 16:49 ` [PATCH v5 5/6] arm: dts: sunplus: add Tibbo LTPP3G2 board Andrew Gaylard
@ 2026-09-24 16:49 ` Andrew Gaylard
5 siblings, 0 replies; 9+ messages in thread
From: Andrew Gaylard @ 2026-09-24 16:49 UTC (permalink / raw)
To: linux-arm-kernel
Cc: devicetree, qinjian, robh, krzk+dt, conor+dt, linux,
Andrew Gaylard
The LTPP3G2 is based on a SP7021 and has a Cortex-A7 CPU, Ethernet,
eMMC, SPI, EEPROM via I2C via GPIO, watchdog, RTC, NVMEM, and LEDs.
Apply these settings:
- ARM_ERRATA_814220=y # needed for Cortex-A7
- ARM_PSCI=y # needed to boot SMP
- CGROUPS=y
CGROUP_SCHED=y
MEMCG=y
NET=y
UNIX=y
INET=y
NETDEVICES=y
SECURITY=y
SECURITY_NETWORK=y # needed to boot the shipped rootfs
Enable these drivers:
- SP7021_EMAC
- SPI_SUNPLUS_SP7021
- I2C_GPIO
- EEPROM_AT24
- MMC_SUNPLUS
- SUNPLUS_WATCHDOG
- RTC_DRV_SUNPLUS
- NVMEM_SUNPLUS_OCOTP
- LEDS_GPIO
Signed-off-by: Andrew Gaylard <ag@ffroot.co.za>
---
arch/arm/configs/sp7021_defconfig | 32 +++++++++++++++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/arch/arm/configs/sp7021_defconfig b/arch/arm/configs/sp7021_defconfig
index ec723401b440..29c200d2bdb7 100644
--- a/arch/arm/configs/sp7021_defconfig
+++ b/arch/arm/configs/sp7021_defconfig
@@ -1,4 +1,7 @@
CONFIG_SYSVIPC=y
+CONFIG_CGROUPS=y
+CONFIG_CGROUP_SCHED=y
+CONFIG_MEMCG=y
CONFIG_NO_HZ_IDLE=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_PREEMPT=y
@@ -16,6 +19,8 @@ CONFIG_PERF_EVENTS=y
CONFIG_ARCH_SUNPLUS=y
# CONFIG_VDSO is not set
CONFIG_SMP=y
+CONFIG_ARM_PSCI=y
+CONFIG_ARM_ERRATA_814220=y
CONFIG_THUMB2_KERNEL=y
CONFIG_ARCH_FORCE_MAX_ORDER=11
CONFIG_VFP=y
@@ -24,11 +29,16 @@ CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_MODVERSIONS=y
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_NET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
CONFIG_UEVENT_HELPER=y
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
CONFIG_BLK_DEV_LOOP=y
+CONFIG_NETDEVICES=y
+CONFIG_SP7021_EMAC=y
CONFIG_INPUT_SPARSEKMAP=y
CONFIG_INPUT_EVDEV=y
# CONFIG_INPUT_KEYBOARD is not set
@@ -36,6 +46,26 @@ CONFIG_INPUT_EVDEV=y
# CONFIG_LEGACY_PTYS is not set
# CONFIG_HW_RANDOM is not set
# CONFIG_HWMON is not set
+CONFIG_SPI=y
+CONFIG_SPI_SUNPLUS_SP7021=y
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_GPIO=y
+CONFIG_EEPROM_AT24=y
+CONFIG_MMC=y
+CONFIG_MMC_SUNPLUS=y
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_SYSFS=y
+CONFIG_SUNPLUS_WATCHDOG=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_SUNPLUS=y
+CONFIG_NVMEM=y
+CONFIG_NVMEM_SUNPLUS_OCOTP=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
# CONFIG_IOMMU_SUPPORT is not set
CONFIG_RESET_CONTROLLER=y
CONFIG_EXT4_FS=y
@@ -51,6 +81,8 @@ CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ASCII=y
CONFIG_NLS_ISO8859_1=y
CONFIG_NLS_UTF8=y
+CONFIG_SECURITY=y
+CONFIG_SECURITY_NETWORK=y
CONFIG_PRINTK_TIME=y
CONFIG_DYNAMIC_DEBUG=y
CONFIG_MAGIC_SYSRQ=y
--
2.53.0
^ permalink raw reply related [flat|nested] 9+ messages in thread