[PATCH v2 0/2] arm64: dts: allwinner: x96qpro+: enable Ethernet support

[PATCH v2 0/2] arm64: dts: allwinner: x96qpro+: enable Ethernet support

[Andre Przywara]

This is an update of the X96QPro+ Ethernet series, but just the DT
patches:
The X96QPro+ TV box uses the second GMAC in the Allwinner H728 SoC, and
connects its RGMII pins to a Maxio MAE0621-Q2C Ethernet PHY. That PHY
is clocked not by a crystal oscillator, but by a clock fanout pin, so by
the SoC.

Patch 1 in this series adds the two 25MHz PHY clock fanout pins to the
pincontroller node in the SoC .dtsi file, which patch 2 uses to describe
the Ethernet setup on this device.

Functionality-wise this series depends on the MAXIO PHY driver series,
though only the DT binding patch from there is required to make a build
pass, so apart from that binding patch they can be merged independently.

Please have a look and test. Based on v7.3-rc1 and this patch:
https://lore.kernel.org/netdev/20260926225625.25969-2-andre.przywara@arm.com/T/#u

Cheers,
Andre

Changes in v2:
- split of from MAXIO PHY patches (they go to netdev separately)
- fix misspelt pin label

Andre Przywara (2):
  arm64: dts: allwinner: a523: add EPHY 25MHz clock fanout pins
  arm64: dts: allwinner: a523: x96qpro+: enable Ethernet support

 .../arm64/boot/dts/allwinner/sun55i-a523.dtsi | 14 ++++++++++
 .../dts/allwinner/sun55i-h728-x96qpro+.dts    | 28 +++++++++++++++++++
 2 files changed, 42 insertions(+)


base-commit: cee9395acd8043be0644b25c34bfa86623f2b935
prerequisite-patch-id: ded31e4869f9628e1af7f9676c718a17cb4f7c88
-- 
2.46.4

[PATCH v2 1/2] arm64: dts: allwinner: a523: add EPHY 25MHz clock fanout pins

[Andre Przywara]

The Allwinner A523 SoC family provides two clock fanout pins, which are
backed by gated clocks fixed to 25 MHz, divided down from the main
peripheral PLL. Those are meant to clock an Ethernet PHY, and allow to
save an external crystal oscillator typically employed for that purpose.

Add the pin descriptions of the two pins for those clocks, one is within
the RGMII0 pins, the other within the RGMII1 pins, although the clock
fanout works completely independently from the two MACs.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi
index 85ef492ffeae7..ce01fad22b469 100644
--- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi
@@ -147,6 +147,20 @@ pio: pinctrl@2000000 {
 			interrupt-controller;
 			#interrupt-cells = <3>;
 
+			/omit-if-no-ref/
+			ephy0_25m_pin: ephy0-25m-pin {
+				pins = "PH13";
+				allwinner,pinmux = <5>;
+				function = "ephy_25m";
+			};
+
+			/omit-if-no-ref/
+			ephy1_25m_pin: ephy1-25m-pin {
+				pins = "PJ10";
+				allwinner,pinmux = <5>;
+				function = "ephy_25m";
+			};
+
 			/omit-if-no-ref/
 			i2s2_pi_pins: i2s2-pi-pins {
 				pins = "PI2", "PI3", "PI4", "PI5";
-- 
2.46.4

[PATCH v2 2/2] arm64: dts: allwinner: a523: x96qpro+: enable Ethernet support

[Andre Przywara]

The X96QPro+ TV Box features a Gigabit Ethernet capable port, which is
driven by the secondary EMAC, and supported by a Maxio MAE0621A PHY.

Add the required devicetree nodes to enable that port.

The PHY is not clocked by an external crystal oscillator, but relies on a
SoC-provided clock fanout pin for its 25 MHz reference input clock. The
clock is referenced in the PHY DT node, which not all systems might enable
before scanning the MDIO bus. To help with that problem, the PHY compatible
string is using the PHY ID, which means the MDIO bus scanning can be
skipped.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Tested-by: Per Larsson <per@palvencia.se>
---
 .../dts/allwinner/sun55i-h728-x96qpro+.dts    | 28 +++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun55i-h728-x96qpro+.dts b/arch/arm64/boot/dts/allwinner/sun55i-h728-x96qpro+.dts
index eb9fd0a65b41c..8015473ecb7ae 100644
--- a/arch/arm64/boot/dts/allwinner/sun55i-h728-x96qpro+.dts
+++ b/arch/arm64/boot/dts/allwinner/sun55i-h728-x96qpro+.dts
@@ -13,6 +13,7 @@ / {
 
 	aliases {
 		serial0 = &uart0;
+		ethernet0 = &gmac1;
 	};
 
 	chosen {
@@ -72,11 +73,38 @@ &ehci1 {
 	status = "okay";
 };
 
+&gmac1 {
+	clocks = <&ccu CLK_BUS_EMAC1>, <&ccu CLK_MBUS_EMAC1>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&rgmii1_pins>;
+	phy-mode = "rgmii-id";
+	phy-handle = <&ext_rgmii_phy>;
+	phy-supply = <&reg_cldo3>;
+
+	tx-internal-delay-ps = <200>;
+	rx-internal-delay-ps = <500>;
+
+	status = "okay";
+};
+
 &gpu {
 	mali-supply = <&reg_dcdc2>;
 	status = "okay";
 };
 
+&mdio1 {
+	ext_rgmii_phy: ethernet-phy@1 {
+		compatible = "ethernet-phy-id7b74.4411";
+		reg = <1>;
+		clocks = <&ccu CLK_EMAC1_25M>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&ephy1_25m_pin>;
+		reset-gpios = <&pio 9 16 GPIO_ACTIVE_LOW>;
+		reset-assert-us = <10000>;
+		reset-deassert-us = <150000>;
+	};
+};
+
 &mmc0 {
 	vmmc-supply = <&reg_vcc3v3>;
 	cd-gpios = <&pio 5 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PF6 */
-- 
2.46.4

Re: [PATCH v2 2/2] arm64: dts: allwinner: a523: x96qpro+: enable Ethernet support

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
- [High] arm64: dts: misplaced PHY clock and pinctrl prevents PHY initialization
- [Medium] arm64: dts: incorrect regulator assigned to phy-supply
- [Low] arm64: dts: redundant clocks property in gmac1 node
--

commit 96eb11f77a00f58bb3ba2189cfd9ad8f4d670b8d
Author: Andre Przywara <andre.przywara@arm.com>

arm64: dts: allwinner: a523: x96qpro+: enable Ethernet support

The X96QPro+ TV Box features a Gigabit Ethernet capable port, which is
driven by the secondary EMAC, and supported by a Maxio MAE0621A PHY.
This commit adds the required devicetree nodes to enable that port.

> diff --git a/arch/arm64/boot/dts/allwinner/sun55i-h728-x96qpro+.dts b/arch/arm64/boot/dts/allwinner/sun55i-h728-x96qpro+.dts
> index eb9fd0a65b41c..8015473ecb7ae 100644
> --- a/arch/arm64/boot/dts/allwinner/sun55i-h728-x96qpro+.dts
> +++ b/arch/arm64/boot/dts/allwinner/sun55i-h728-x96qpro+.dts
[ ... ]
> @@ -72,11 +73,38 @@ &ehci1 {
>  	status = "okay";
>  };
>  
> +&gmac1 {
> +	clocks = <&ccu CLK_BUS_EMAC1>, <&ccu CLK_MBUS_EMAC1>;

[Severity: Low]
Are these clock definitions needed here? It looks like they exactly
duplicate the clocks property already defined for gmac1 in the base
sun55i-a523.dtsi without changing the values.

> +	pinctrl-names = "default";
> +	pinctrl-0 = <&rgmii1_pins>;
> +	phy-mode = "rgmii-id";
> +	phy-handle = <&ext_rgmii_phy>;
> +	phy-supply = <&reg_cldo3>;

[Severity: Medium]
Should this use reg_cldo4 instead of reg_cldo3?

Other sibling A523 boards use reg_cldo4 for gmac1, and reg_cldo4 is
explicitly named vcc-eth-phy in the PMIC definitions. If reg_cldo4 is
the actual PHY power rail, it will be disabled late in the boot process
by the regulator core since it is unreferenced, which would cause the PHY
to lose power.

> +
> +	tx-internal-delay-ps = <200>;
> +	rx-internal-delay-ps = <500>;
> +
> +	status = "okay";
> +};
> +
[ ... ]
> +&mdio1 {
> +	ext_rgmii_phy: ethernet-phy@1 {
> +		compatible = "ethernet-phy-id7b74.4411";
> +		reg = <1>;
> +		clocks = <&ccu CLK_EMAC1_25M>;

[Severity: High]
Since there is no specific Maxio MAE0621A PHY driver, won't this PHY
bind to the generic PHY driver (genphy) which does not parse or enable
clocks?

If so, the 25MHz reference clock will never be enabled by the kernel,
which would prevent the Ethernet PHY from initializing.

> +		pinctrl-names = "default";
> +		pinctrl-0 = <&ephy1_25m_pin>;
> +		reset-gpios = <&pio 9 16 GPIO_ACTIVE_LOW>;

[Severity: High]
Does placing the pinctrl here alongside the reset-gpios cause the hardware
reset to execute before the clock pin is muxed?

The MDIO bus core (mdiobus_register_device()) pulses reset-gpios before
device_add() and driver binding. Because pinctrl is applied during driver
probe, the reset is pulsed before the clock pin is muxed and active, meaning
the PHY undergoes hardware reset without its clock running.

Could this leave the PHY in an undefined state?

> +		reset-assert-us = <10000>;
> +		reset-deassert-us = <150000>;
> +	};
> +};

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260926232142.5244-1-andre.przywara@arm.com?part=2

Re: [PATCH v2 1/2] arm64: dts: allwinner: a523: add EPHY 25MHz clock fanout pins

[Jernej Škrabec]

Dne nedelja, 27. september 2026 ob 01:21:41 Srednjeevropski poletni čas je Andre Przywara napisal(a):
> The Allwinner A523 SoC family provides two clock fanout pins, which are
> backed by gated clocks fixed to 25 MHz, divided down from the main
> peripheral PLL. Those are meant to clock an Ethernet PHY, and allow to
> save an external crystal oscillator typically employed for that purpose.
> 
> Add the pin descriptions of the two pins for those clocks, one is within
> the RGMII0 pins, the other within the RGMII1 pins, although the clock
> fanout works completely independently from the two MACs.
> 
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>

Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>

Best regards,
Jernej