* [PATCH] arm64: dts: renesas: r8a78000: Add I2C nodes
@ 2026-09-27 15:09 Wolfram Sang
2026-09-27 15:22 ` sashiko-bot
2026-09-28 9:11 ` Geert Uytterhoeven
0 siblings, 2 replies; 3+ messages in thread
From: Wolfram Sang @ 2026-09-27 15:09 UTC (permalink / raw)
To: linux-renesas-soc
Cc: Wolfram Sang, Geert Uytterhoeven, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, devicetree
Add device nodes for the I2C controllers of the Renesas R-Car X5H
(R8A78000) SoC.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---
Based on -next as of 20260925. Depends on "[PATCH] clk: renesas:
r8a78000: Add SGASYNCD8_PERW_BUS". DMA nodes to be added together with
the DMA controller once its dependencies are upstream. DT check has
passed.
arch/arm64/boot/dts/renesas/r8a78000.dtsi | 112 ++++++++++++++++++++++
1 file changed, 112 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a78000.dtsi b/arch/arm64/boot/dts/renesas/r8a78000.dtsi
index 9a07753b2215..fbca02da6184 100644
--- a/arch/arm64/boot/dts/renesas/r8a78000.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a78000.dtsi
@@ -862,6 +862,118 @@ gic: interrupt-controller@39000000 {
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
+ i2c1: i2c@c06c0000 {
+ compatible = "renesas,i2c-r8a78000",
+ "renesas,rcar-gen5-i2c";
+ reg = <0 0xc06c0000 0 0x40>;
+ interrupts = <GIC_SPI 956 IRQ_TYPE_LEVEL_HIGH>;
+ i2c-scl-internal-delay-ns = <110>;
+ clocks = <&cpg R8A78000_CPG_SGASYNCD8_PERW_BUS>;
+ power-domains = <&mdlc_perw R8A78000_MDLC_PD_APL 0x44>;
+ resets = <&mdlc_perw 0x44>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@c06c8000 {
+ compatible = "renesas,i2c-r8a78000",
+ "renesas,rcar-gen5-i2c";
+ reg = <0 0xc06c8000 0 0x40>;
+ interrupts = <GIC_SPI 957 IRQ_TYPE_LEVEL_HIGH>;
+ i2c-scl-internal-delay-ns = <110>;
+ clocks = <&cpg R8A78000_CPG_SGASYNCD8_PERW_BUS>;
+ power-domains = <&mdlc_perw R8A78000_MDLC_PD_APL 0x45>;
+ resets = <&mdlc_perw 0x45>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@c06d0000 {
+ compatible = "renesas,i2c-r8a78000",
+ "renesas,rcar-gen5-i2c";
+ reg = <0 0xc06d0000 0 0x40>;
+ interrupts = <GIC_SPI 958 IRQ_TYPE_LEVEL_HIGH>;
+ i2c-scl-internal-delay-ns = <110>;
+ clocks = <&cpg R8A78000_CPG_SGASYNCD8_PERW_BUS>;
+ power-domains = <&mdlc_perw R8A78000_MDLC_PD_APL 0x46>;
+ resets = <&mdlc_perw 0x46>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@c06d8000 {
+ compatible = "renesas,i2c-r8a78000",
+ "renesas,rcar-gen5-i2c";
+ reg = <0 0xc06d8000 0 0x40>;
+ interrupts = <GIC_SPI 959 IRQ_TYPE_LEVEL_HIGH>;
+ i2c-scl-internal-delay-ns = <110>;
+ clocks = <&cpg R8A78000_CPG_SGASYNCD8_PERW_BUS>;
+ power-domains = <&mdlc_perw R8A78000_MDLC_PD_APL 0x47>;
+ resets = <&mdlc_perw 0x47>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c5: i2c@c06e0000 {
+ compatible = "renesas,i2c-r8a78000",
+ "renesas,rcar-gen5-i2c";
+ reg = <0 0xc06e0000 0 0x40>;
+ interrupts = <GIC_ESPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ i2c-scl-internal-delay-ns = <110>;
+ clocks = <&cpg R8A78000_CPG_SGASYNCD8_PERW_BUS>;
+ power-domains = <&mdlc_perw R8A78000_MDLC_PD_APL 0x48>;
+ resets = <&mdlc_perw 0x48>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c6: i2c@c06e8000 {
+ compatible = "renesas,i2c-r8a78000",
+ "renesas,rcar-gen5-i2c";
+ reg = <0 0xc06e8000 0 0x40>;
+ interrupts = <GIC_ESPI 1 IRQ_TYPE_LEVEL_HIGH>;
+ i2c-scl-internal-delay-ns = <110>;
+ clocks = <&cpg R8A78000_CPG_SGASYNCD8_PERW_BUS>;
+ power-domains = <&mdlc_perw R8A78000_MDLC_PD_APL 0x49>;
+ resets = <&mdlc_perw 0x49>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c7: i2c@c06f0000 {
+ compatible = "renesas,i2c-r8a78000",
+ "renesas,rcar-gen5-i2c";
+ reg = <0 0xc06f0000 0 0x40>;
+ interrupts = <GIC_ESPI 2 IRQ_TYPE_LEVEL_HIGH>;
+ i2c-scl-internal-delay-ns = <110>;
+ clocks = <&cpg R8A78000_CPG_SGASYNCD8_PERW_BUS>;
+ power-domains = <&mdlc_perw R8A78000_MDLC_PD_APL 0x4a>;
+ resets = <&mdlc_perw 0x4a>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c8: i2c@c06f8000 {
+ compatible = "renesas,i2c-r8a78000",
+ "renesas,rcar-gen5-i2c";
+ reg = <0 0xc06f8000 0 0x40>;
+ interrupts = <GIC_ESPI 3 IRQ_TYPE_LEVEL_HIGH>;
+ i2c-scl-internal-delay-ns = <110>;
+ clocks = <&cpg R8A78000_CPG_SGASYNCD8_PERW_BUS>;
+ power-domains = <&mdlc_perw R8A78000_MDLC_PD_APL 0x4b>;
+ resets = <&mdlc_perw 0x4b>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
scif0: serial@c0700000 {
compatible = "renesas,scif-r8a78000",
"renesas,rcar-gen5-scif", "renesas,scif";
--
2.53.0
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH] arm64: dts: renesas: r8a78000: Add I2C nodes
2026-09-27 15:09 [PATCH] arm64: dts: renesas: r8a78000: Add I2C nodes Wolfram Sang
@ 2026-09-27 15:22 ` sashiko-bot
2026-09-28 9:11 ` Geert Uytterhoeven
1 sibling, 0 replies; 3+ messages in thread
From: sashiko-bot @ 2026-09-27 15:22 UTC (permalink / raw)
To: Wolfram Sang; +Cc: conor+dt, wsa+renesas, robh, devicetree
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] dts: missing prerequisite includes and nodes for i2c controllers
--
commit 3f7801bb0ea0ac6eb4aa58321a3d66e8c5413897
Author: Wolfram Sang <wsa+renesas@sang-engineering.com>
arm64: dts: renesas: r8a78000: Add I2C nodes
Add device nodes for the I2C controllers of the Renesas R-Car X5H (R8A78000)
SoC.
> diff --git a/arch/arm64/boot/dts/renesas/r8a78000.dtsi b/arch/arm64/boot/dts/renesas/r8a78000.dtsi
> index fb71974ef3905..a6a60d8930dec 100644
> --- a/arch/arm64/boot/dts/renesas/r8a78000.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a78000.dtsi
> @@ -877,6 +877,118 @@ gic: interrupt-controller@39000000 {
> interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> };
>
> + i2c1: i2c@c06c0000 {
> + compatible = "renesas,i2c-r8a78000",
> + "renesas,rcar-gen5-i2c";
> + reg = <0 0xc06c0000 0 0x40>;
> + interrupts = <GIC_SPI 956 IRQ_TYPE_LEVEL_HIGH>;
> + i2c-scl-internal-delay-ns = <110>;
> + clocks = <&cpg R8A78000_CPG_SGASYNCD8_PERW_BUS>;
> + power-domains = <&mdlc_perw R8A78000_MDLC_PD_APL 0x44>;
> + resets = <&mdlc_perw 0x44>;
[Severity: Low]
Will this device tree compile cleanly on the current baseline?
It looks like the R8A78000_CPG_SGASYNCD8_PERW_BUS and R8A78000_MDLC_PD_APL
macros, as well as the &cpg and &mdlc_perw phandles, are not yet defined in
the current tree.
Could this cause syntax errors and unresolved phandle references during the
build?
[ ... ]
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260927151133.45845-3-wsa+renesas@sang-engineering.com?part=1
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] arm64: dts: renesas: r8a78000: Add I2C nodes
2026-09-27 15:09 [PATCH] arm64: dts: renesas: r8a78000: Add I2C nodes Wolfram Sang
2026-09-27 15:22 ` sashiko-bot
@ 2026-09-28 9:11 ` Geert Uytterhoeven
1 sibling, 0 replies; 3+ messages in thread
From: Geert Uytterhoeven @ 2026-09-28 9:11 UTC (permalink / raw)
To: Wolfram Sang
Cc: linux-renesas-soc, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, devicetree
On Sun, 27 Sept 2026 at 17:12, Wolfram Sang
<wsa+renesas@sang-engineering.com> wrote:
> Add device nodes for the I2C controllers of the Renesas R-Car X5H
> (R8A78000) SoC.
>
> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v7.4.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
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2026-09-27 15:22 ` sashiko-bot
2026-09-28 9:11 ` Geert Uytterhoeven
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