From: Sai Sree Kartheek Adivi <s-adivi@ti.com>
To: <peter.ujfalusi@gmail.com>, <vkoul@kernel.org>, <robh@kernel.org>,
<krzk+dt@kernel.org>, <conor+dt@kernel.org>, <nm@ti.com>,
<ssantosh@kernel.org>, <dmaengine@vger.kernel.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>, <vigneshr@ti.com>,
<Frank.li@nxp.com>, <s-adivi@ti.com>
Cc: <r-sharma3@ti.com>, <gehariprasath@ti.com>
Subject: [PATCH v10 18/19] dmaengine: ti: k3-udma-v2: Update glue layer to support PKTDMA V2
Date: Mon, 28 Sep 2026 08:26:24 +0530 [thread overview]
Message-ID: <20260928025749.1055383-19-s-adivi@ti.com> (raw)
In-Reply-To: <20260928025749.1055383-1-s-adivi@ti.com>
Update glue layer to support PKTDMA V2 for non DMAengine users.
The updates include
- Handling absence of TISCI
- Direct IRQs
- Autopair: Lack of PSIL pair.
Signed-off-by: Sai Sree Kartheek Adivi <s-adivi@ti.com>
---
drivers/dma/ti/Kconfig | 2 +-
drivers/dma/ti/k3-udma-glue.c | 190 ++++++++++++++++++++++++-------
drivers/dma/ti/k3-udma-private.c | 5 +
drivers/dma/ti/k3-udma.h | 13 +++
4 files changed, 169 insertions(+), 41 deletions(-)
diff --git a/drivers/dma/ti/Kconfig b/drivers/dma/ti/Kconfig
index 595fdf3ecbc9d..3d001f2e3f040 100644
--- a/drivers/dma/ti/Kconfig
+++ b/drivers/dma/ti/Kconfig
@@ -67,7 +67,7 @@ config TI_K3_UDMA_COMMON
config TI_K3_UDMA_GLUE_LAYER
tristate "Texas Instruments UDMA Glue layer for non DMAengine users"
depends on ARCH_K3 || COMPILE_TEST
- depends on TI_K3_UDMA
+ depends on TI_K3_UDMA || TI_K3_UDMA_V2
help
Say y here to support the K3 NAVSS DMA glue interface
If unsure, say N.
diff --git a/drivers/dma/ti/k3-udma-glue.c b/drivers/dma/ti/k3-udma-glue.c
index 996c130b10f4a..309a74a0b2a67 100644
--- a/drivers/dma/ti/k3-udma-glue.c
+++ b/drivers/dma/ti/k3-udma-glue.c
@@ -12,6 +12,7 @@
#include <linux/dma-mapping.h>
#include <linux/io.h>
#include <linux/init.h>
+#include <linux/iopoll.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/soc/ti/k3-ringacc.h>
@@ -267,6 +268,23 @@ static int k3_udma_glue_cfg_tx_chn(struct k3_udma_glue_tx_channel *tx_chn)
const struct udma_tisci_rm *tisci_rm = tx_chn->common.tisci_rm;
struct ti_sci_msg_rm_udmap_tx_ch_cfg req;
+ if (!tisci_rm->tisci) {
+ u32 val = 0;
+
+ if (tx_chn->tx_pause_on_err)
+ val |= UDMA_CHAN_CFG_PAUSE_ON_ERR;
+ if (tx_chn->tx_filt_einfo)
+ val |= UDMA_CHAN_CFG_FILT_EINFO;
+ if (tx_chn->tx_filt_pswords)
+ val |= UDMA_CHAN_CFG_FILT_PSWORDS;
+ if (tx_chn->tx_supr_tdpkt)
+ val |= UDMA_CHAN_CFG_TX_SUPR_TDPKT;
+
+ xudma_tchanrt_write(tx_chn->udma_tchanx, UDMA_CHAN_RT_CFG_REG, val);
+
+ return 0;
+ }
+
memset(&req, 0, sizeof(req));
req.valid_params = TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID |
@@ -525,21 +543,39 @@ int k3_udma_glue_enable_tx_chn(struct k3_udma_glue_tx_channel *tx_chn)
{
int ret;
- ret = xudma_navss_psil_pair(tx_chn->common.udmax,
- tx_chn->common.src_thread,
- tx_chn->common.dst_thread);
- if (ret) {
- dev_err(tx_chn->common.dev, "PSI-L request err %d\n", ret);
- return ret;
- }
+ if (tx_chn->common.udmax->match_data->version == K3_UDMA_V1) {
+ ret = xudma_navss_psil_pair(tx_chn->common.udmax,
+ tx_chn->common.src_thread,
+ tx_chn->common.dst_thread);
+ if (ret) {
+ dev_err(tx_chn->common.dev, "PSI-L request err %d\n", ret);
+ return ret;
+ }
- tx_chn->psil_paired = true;
+ tx_chn->psil_paired = true;
- xudma_tchanrt_write(tx_chn->udma_tchanx, UDMA_CHAN_RT_PEER_RT_EN_REG,
- UDMA_PEER_RT_EN_ENABLE);
+ xudma_tchanrt_write(tx_chn->udma_tchanx, UDMA_CHAN_RT_PEER_RT_EN_REG,
+ UDMA_PEER_RT_EN_ENABLE);
- xudma_tchanrt_write(tx_chn->udma_tchanx, UDMA_CHAN_RT_CTL_REG,
- UDMA_CHAN_RT_CTL_EN);
+ xudma_tchanrt_write(tx_chn->udma_tchanx, UDMA_CHAN_RT_CTL_REG,
+ UDMA_CHAN_RT_CTL_EN);
+ } else {
+ u32 val;
+
+ xudma_tchanrt_write(tx_chn->udma_tchanx, UDMA_CHAN_RT_CTL_REG,
+ UDMA_CHAN_RT_CTL_AUTOPAIR | UDMA_CHAN_RT_CTL_EN);
+
+ ret = read_poll_timeout(xudma_tchanrt_read, val,
+ val & (UDMA_CHAN_RT_CTL_PAIR_COMPLETE |
+ UDMA_CHAN_RT_CTL_PAIR_TIMEOUT),
+ 100, 500, false,
+ tx_chn->udma_tchanx, UDMA_CHAN_RT_CTL_REG);
+ if (ret || (val & UDMA_CHAN_RT_CTL_PAIR_TIMEOUT)) {
+ dev_err(tx_chn->common.dev, "TX channel autopair timeout\n");
+ xudma_tchanrt_write(tx_chn->udma_tchanx, UDMA_CHAN_RT_CTL_REG, 0);
+ return -ETIMEDOUT;
+ }
+ }
k3_udma_glue_dump_tx_rt_chn(tx_chn, "txchn en");
return 0;
@@ -573,8 +609,16 @@ void k3_udma_glue_tdown_tx_chn(struct k3_udma_glue_tx_channel *tx_chn,
k3_udma_glue_dump_tx_rt_chn(tx_chn, "txchn tdown1");
- xudma_tchanrt_write(tx_chn->udma_tchanx, UDMA_CHAN_RT_CTL_REG,
- UDMA_CHAN_RT_CTL_EN | UDMA_CHAN_RT_CTL_TDOWN);
+ if (tx_chn->common.udmax->match_data->version == K3_UDMA_V1) {
+ xudma_tchanrt_write(tx_chn->udma_tchanx, UDMA_CHAN_RT_CTL_REG,
+ UDMA_CHAN_RT_CTL_EN | UDMA_CHAN_RT_CTL_TDOWN);
+ } else {
+ xudma_tchanrt_write(tx_chn->udma_tchanx, UDMA_CHAN_RT_PEER_REG(8),
+ UDMA_CHAN_RT_PEER_REG8_FLUSH);
+ val = xudma_tchanrt_read(tx_chn->udma_tchanx, UDMA_CHAN_RT_CTL_REG);
+ xudma_tchanrt_write(tx_chn->udma_tchanx, UDMA_CHAN_RT_CTL_REG,
+ val | UDMA_CHAN_RT_CTL_TDOWN);
+ }
val = xudma_tchanrt_read(tx_chn->udma_tchanx, UDMA_CHAN_RT_CTL_REG);
@@ -589,10 +633,12 @@ void k3_udma_glue_tdown_tx_chn(struct k3_udma_glue_tx_channel *tx_chn,
i++;
}
- val = xudma_tchanrt_read(tx_chn->udma_tchanx,
- UDMA_CHAN_RT_PEER_RT_EN_REG);
- if (sync && (val & UDMA_PEER_RT_EN_ENABLE))
- dev_err(tx_chn->common.dev, "TX tdown peer not stopped\n");
+ if (tx_chn->common.udmax->match_data->version == K3_UDMA_V1) {
+ val = xudma_tchanrt_read(tx_chn->udma_tchanx,
+ UDMA_CHAN_RT_PEER_RT_EN_REG);
+ if (sync && (val & UDMA_PEER_RT_EN_ENABLE))
+ dev_err(tx_chn->common.dev, "TX tdown peer not stopped\n");
+ }
k3_udma_glue_dump_tx_rt_chn(tx_chn, "txchn tdown2");
}
EXPORT_SYMBOL_GPL(k3_udma_glue_tdown_tx_chn);
@@ -705,7 +751,6 @@ static int k3_udma_glue_cfg_rx_chn(struct k3_udma_glue_rx_channel *rx_chn)
TI_SCI_MSG_VALUE_RM_UDMAP_CH_CHAN_TYPE_VALID |
TI_SCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_VALID;
- req.nav_id = tisci_rm->tisci_dev_id;
req.index = rx_chn->udma_rchan_id;
req.rx_fetch_size = rx_chn->common.hdesc_size >> 2;
/*
@@ -725,11 +770,24 @@ static int k3_udma_glue_cfg_rx_chn(struct k3_udma_glue_rx_channel *rx_chn)
req.rx_chan_type = TI_SCI_RM_UDMAP_CHAN_TYPE_PKT_PBRR;
req.rx_atype = rx_chn->common.atype_asel;
+ if (!tisci_rm->tisci) {
+ u32 val = 0;
+
+ if (rx_chn->common.epib)
+ val |= UDMA_CHAN_CFG_FILT_EINFO;
+ if (rx_chn->common.psdata_size)
+ val |= UDMA_CHAN_CFG_FILT_PSWORDS;
+
+ xudma_rchanrt_write(rx_chn->udma_rchanx, UDMA_CHAN_RT_CFG_REG, val);
+
+ return 0;
+ }
+
+ req.nav_id = tisci_rm->tisci_dev_id;
ret = tisci_rm->tisci_udmap_ops->rx_ch_cfg(tisci_rm->tisci, &req);
if (ret)
dev_err(rx_chn->common.dev, "rchan%d cfg failed %d\n",
- rx_chn->udma_rchan_id, ret);
-
+ rx_chn->udma_rchan_id, ret);
return ret;
}
@@ -778,8 +836,11 @@ static int k3_udma_glue_cfg_rx_flow(struct k3_udma_glue_rx_channel *rx_chn,
}
if (xudma_is_pktdma(rx_chn->common.udmax)) {
- rx_ringfdq_id = flow->udma_rflow_id +
+ if (tisci_rm->tisci)
+ rx_ringfdq_id = flow->udma_rflow_id +
xudma_get_rflow_ring_offset(rx_chn->common.udmax);
+ else
+ rx_ringfdq_id = flow->udma_rflow_id;
rx_ring_id = 0;
} else {
rx_ring_id = flow_cfg->ring_rxq_id;
@@ -826,6 +887,21 @@ static int k3_udma_glue_cfg_rx_flow(struct k3_udma_glue_rx_channel *rx_chn,
rx_ringfdq_id = k3_ringacc_get_ring_id(flow->ringrxfdq);
}
+ if (!tisci_rm->tisci) {
+ u32 val = 0;
+
+ if (rx_chn->common.epib)
+ val |= UDMA_FLOWRT_RFA_RX_EINFO_PRESENT;
+ if (rx_chn->common.psdata_size)
+ val |= UDMA_FLOWRT_RFA_RX_PSINFO_PRESENT;
+ if (flow_cfg->rx_error_handling)
+ val |= UDMA_FLOWRT_RFA_RX_ERROR_HANDLING;
+
+ xudma_rflowrt_write(flow->udma_rflow, UDMA_RX_FLOWRT_RFA, val);
+ rx_chn->flows_ready++;
+ return 0;
+ }
+
memset(&req, 0, sizeof(req));
req.valid_params =
@@ -1331,6 +1407,9 @@ int k3_udma_glue_rx_flow_enable(struct k3_udma_glue_rx_channel *rx_chn,
if (!rx_chn->remote)
return -EINVAL;
+ if (!tisci_rm->tisci)
+ return 0;
+
rx_ring_id = k3_ringacc_get_ring_id(flow->ringrx);
rx_ringfdq_id = k3_ringacc_get_ring_id(flow->ringrxfdq);
@@ -1372,6 +1451,9 @@ int k3_udma_glue_rx_flow_disable(struct k3_udma_glue_rx_channel *rx_chn,
if (!rx_chn->remote)
return -EINVAL;
+ if (!tisci_rm->tisci)
+ return 0;
+
memset(&req, 0, sizeof(req));
req.valid_params =
TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_QNUM_VALID |
@@ -1407,21 +1489,39 @@ int k3_udma_glue_enable_rx_chn(struct k3_udma_glue_rx_channel *rx_chn)
if (rx_chn->flows_ready < rx_chn->flow_num)
return -EINVAL;
- ret = xudma_navss_psil_pair(rx_chn->common.udmax,
- rx_chn->common.src_thread,
- rx_chn->common.dst_thread);
- if (ret) {
- dev_err(rx_chn->common.dev, "PSI-L request err %d\n", ret);
- return ret;
- }
+ if (rx_chn->common.udmax->match_data->version == K3_UDMA_V1) {
+ ret = xudma_navss_psil_pair(rx_chn->common.udmax,
+ rx_chn->common.src_thread,
+ rx_chn->common.dst_thread);
+ if (ret) {
+ dev_err(rx_chn->common.dev, "PSI-L request err %d\n", ret);
+ return ret;
+ }
- rx_chn->psil_paired = true;
+ rx_chn->psil_paired = true;
- xudma_rchanrt_write(rx_chn->udma_rchanx, UDMA_CHAN_RT_CTL_REG,
- UDMA_CHAN_RT_CTL_EN);
+ xudma_rchanrt_write(rx_chn->udma_rchanx, UDMA_CHAN_RT_CTL_REG,
+ UDMA_CHAN_RT_CTL_EN);
- xudma_rchanrt_write(rx_chn->udma_rchanx, UDMA_CHAN_RT_PEER_RT_EN_REG,
- UDMA_PEER_RT_EN_ENABLE);
+ xudma_rchanrt_write(rx_chn->udma_rchanx, UDMA_CHAN_RT_PEER_RT_EN_REG,
+ UDMA_PEER_RT_EN_ENABLE);
+ } else {
+ u32 val;
+
+ xudma_rchanrt_write(rx_chn->udma_rchanx, UDMA_CHAN_RT_CTL_REG,
+ UDMA_CHAN_RT_CTL_AUTOPAIR | UDMA_CHAN_RT_CTL_EN);
+
+ ret = read_poll_timeout(xudma_rchanrt_read, val,
+ val & (UDMA_CHAN_RT_CTL_PAIR_COMPLETE |
+ UDMA_CHAN_RT_CTL_PAIR_TIMEOUT),
+ 100, 500, false,
+ rx_chn->udma_rchanx, UDMA_CHAN_RT_CTL_REG);
+ if (ret || (val & UDMA_CHAN_RT_CTL_PAIR_TIMEOUT)) {
+ dev_err(rx_chn->common.dev, "RX channel autopair timeout\n");
+ xudma_rchanrt_write(rx_chn->udma_rchanx, UDMA_CHAN_RT_CTL_REG, 0);
+ return -ETIMEDOUT;
+ }
+ }
k3_udma_glue_dump_rx_rt_chn(rx_chn, "rxrt en");
return 0;
@@ -1458,8 +1558,16 @@ void k3_udma_glue_tdown_rx_chn(struct k3_udma_glue_rx_channel *rx_chn,
k3_udma_glue_dump_rx_rt_chn(rx_chn, "rxrt tdown1");
- xudma_rchanrt_write(rx_chn->udma_rchanx, UDMA_CHAN_RT_PEER_RT_EN_REG,
- UDMA_PEER_RT_EN_ENABLE | UDMA_PEER_RT_EN_TEARDOWN);
+ if (rx_chn->common.udmax->match_data->version == K3_UDMA_V1) {
+ xudma_rchanrt_write(rx_chn->udma_rchanx, UDMA_CHAN_RT_PEER_RT_EN_REG,
+ UDMA_PEER_RT_EN_ENABLE | UDMA_PEER_RT_EN_TEARDOWN);
+ } else {
+ xudma_rchanrt_write(rx_chn->udma_rchanx, UDMA_CHAN_RT_PEER_REG(8),
+ UDMA_CHAN_RT_PEER_REG8_FLUSH);
+ val = xudma_rchanrt_read(rx_chn->udma_rchanx, UDMA_CHAN_RT_CTL_REG);
+ xudma_rchanrt_write(rx_chn->udma_rchanx, UDMA_CHAN_RT_CTL_REG,
+ val | UDMA_CHAN_RT_CTL_TDOWN);
+ }
val = xudma_rchanrt_read(rx_chn->udma_rchanx, UDMA_CHAN_RT_CTL_REG);
@@ -1474,10 +1582,12 @@ void k3_udma_glue_tdown_rx_chn(struct k3_udma_glue_rx_channel *rx_chn,
i++;
}
- val = xudma_rchanrt_read(rx_chn->udma_rchanx,
- UDMA_CHAN_RT_PEER_RT_EN_REG);
- if (sync && (val & UDMA_PEER_RT_EN_ENABLE))
- dev_err(rx_chn->common.dev, "TX tdown peer not stopped\n");
+ if (rx_chn->common.udmax->match_data->version == K3_UDMA_V1) {
+ val = xudma_rchanrt_read(rx_chn->udma_rchanx,
+ UDMA_CHAN_RT_PEER_RT_EN_REG);
+ if (sync && (val & UDMA_PEER_RT_EN_ENABLE))
+ dev_err(rx_chn->common.dev, "TX tdown peer not stopped\n");
+ }
k3_udma_glue_dump_rx_rt_chn(rx_chn, "rxrt tdown2");
}
EXPORT_SYMBOL_GPL(k3_udma_glue_tdown_rx_chn);
diff --git a/drivers/dma/ti/k3-udma-private.c b/drivers/dma/ti/k3-udma-private.c
index 525155d3bb513..d6d99f60519a1 100644
--- a/drivers/dma/ti/k3-udma-private.c
+++ b/drivers/dma/ti/k3-udma-private.c
@@ -3,6 +3,10 @@
* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
* Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
*/
+#include <linux/irq.h>
+#include <linux/irqchip.h>
+#include <linux/irqdomain.h>
+#include <linux/interrupt.h>
#include <linux/of.h>
#include <linux/of_platform.h>
@@ -165,6 +169,7 @@ void xudma_##res##rt_write(struct udma_##res *p, int reg, u32 val) \
EXPORT_SYMBOL(xudma_##res##rt_write)
XUDMA_RT_IO_FUNCTIONS(tchan);
XUDMA_RT_IO_FUNCTIONS(rchan);
+XUDMA_RT_IO_FUNCTIONS(rflow);
int xudma_is_pktdma(struct udma_dev *ud)
{
diff --git a/drivers/dma/ti/k3-udma.h b/drivers/dma/ti/k3-udma.h
index 2a9686f7a09bc..983cf2c32531c 100644
--- a/drivers/dma/ti/k3-udma.h
+++ b/drivers/dma/ti/k3-udma.h
@@ -85,6 +85,17 @@
#define UDMA_CHAN_RT_CTL_PAIR_COMPLETE BIT(16)
#define UDMA_CHAN_RT_CTL_ERROR BIT(0)
+/* UDMA_CHAN_CFG_REG */
+#define UDMA_CHAN_CFG_PAUSE_ON_ERR BIT(31)
+#define UDMA_CHAN_CFG_FILT_EINFO BIT(30)
+#define UDMA_CHAN_CFG_FILT_PSWORDS BIT(29)
+#define UDMA_CHAN_CFG_TX_SUPR_TDPKT BIT(8)
+
+/* UDMA_RX_FLOWRT_RFA */
+#define UDMA_FLOWRT_RFA_RX_EINFO_PRESENT BIT(30)
+#define UDMA_FLOWRT_RFA_RX_PSINFO_PRESENT BIT(29)
+#define UDMA_FLOWRT_RFA_RX_ERROR_HANDLING BIT(28)
+
/* UDMA_CHAN_RT_PDMA_STATE_REG */
#define UDMA_CHAN_RT_PDMA_STATE_IN_EVT BIT(31)
#define UDMA_CHAN_RT_PDMA_STATE_TDOWN BIT(30)
@@ -747,6 +758,8 @@ u32 xudma_rchanrt_read(struct udma_rchan *rchan, int reg);
void xudma_rchanrt_write(struct udma_rchan *rchan, int reg, u32 val);
bool xudma_rflow_is_gp(struct udma_dev *ud, int id);
int xudma_get_rflow_ring_offset(struct udma_dev *ud);
+u32 xudma_rflowrt_read(struct udma_rflow *rflow, int reg);
+void xudma_rflowrt_write(struct udma_rflow *rflow, int reg, u32 val);
int xudma_is_pktdma(struct udma_dev *ud);
--
2.54.0
next prev parent reply other threads:[~2026-09-28 3:00 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-28 2:56 [PATCH v10 00/19] dmaengine: ti: Add support for BCDMA v2 and PKTDMA v2 Sai Sree Kartheek Adivi
2026-09-28 2:56 ` [PATCH v10 01/19] dmaengine: ti: k3-udma: Fix sporadic crash on AM62x Sai Sree Kartheek Adivi
2026-09-28 8:39 ` Vignesh Raghavendra
2026-09-28 2:56 ` [PATCH v10 02/19] dmaengine: ti: k3-udma: move macros to header file Sai Sree Kartheek Adivi
2026-09-28 2:56 ` [PATCH v10 03/19] dmaengine: ti: k3-udma: move structs and enums " Sai Sree Kartheek Adivi
2026-09-28 2:56 ` [PATCH v10 04/19] dmaengine: ti: k3-udma: move static inline helper functions " Sai Sree Kartheek Adivi
2026-09-28 3:12 ` sashiko-bot
2026-09-28 2:56 ` [PATCH v10 05/19] dmaengine: ti: k3-udma: move descriptor management to k3-udma-common.c Sai Sree Kartheek Adivi
2026-09-28 8:39 ` Vignesh Raghavendra
2026-09-28 2:56 ` [PATCH v10 06/19] dmaengine: ti: k3-udma: move ring management functions " Sai Sree Kartheek Adivi
2026-09-28 2:56 ` [PATCH v10 07/19] dmaengine: ti: k3-udma: Add variant-specific function pointers to udma_dev Sai Sree Kartheek Adivi
2026-09-28 8:39 ` Vignesh Raghavendra
2026-09-28 2:56 ` [PATCH v10 08/19] dmaengine: ti: k3-udma: move udma utility functions to k3-udma-common.c Sai Sree Kartheek Adivi
2026-09-28 8:39 ` Vignesh Raghavendra
2026-09-28 2:56 ` [PATCH v10 09/19] dmaengine: ti: k3-udma: move resource management " Sai Sree Kartheek Adivi
2026-09-28 2:56 ` [PATCH v10 10/19] dmaengine: ti: k3-udma: refactor resource setup functions Sai Sree Kartheek Adivi
2026-09-28 8:39 ` Vignesh Raghavendra
2026-09-28 2:56 ` [PATCH v10 11/19] dmaengine: ti: k3-udma: move inclusion of k3-udma-private.c to k3-udma-common.c Sai Sree Kartheek Adivi
2026-09-28 3:13 ` sashiko-bot
2026-09-28 2:56 ` [PATCH v10 12/19] drivers: soc: ti: k3-ringacc: handle absence of tisci Sai Sree Kartheek Adivi
2026-09-28 3:15 ` sashiko-bot
2026-09-28 8:39 ` Vignesh Raghavendra
2026-09-28 2:56 ` [PATCH v10 13/19] dt-bindings: dma: ti: Add K3 BCDMA V2 Sai Sree Kartheek Adivi
2026-09-28 2:56 ` [PATCH v10 14/19] dt-bindings: dma: ti: Add K3 PKTDMA V2 Sai Sree Kartheek Adivi
2026-09-30 10:22 ` Krzysztof Kozlowski
2026-09-28 2:56 ` [PATCH v10 15/19] dmaengine: ti: k3-psil-am62l: Add AM62Lx PSIL and PDMA data Sai Sree Kartheek Adivi
2026-09-28 3:18 ` sashiko-bot
2026-09-28 8:39 ` Vignesh Raghavendra
2026-09-28 2:56 ` [PATCH v10 16/19] dmaengine: ti: k3-udma-v2: New driver for K3 BCDMA_V2 Sai Sree Kartheek Adivi
2026-09-28 3:26 ` sashiko-bot
2026-09-28 8:39 ` Vignesh Raghavendra
2026-09-28 2:56 ` [PATCH v10 17/19] dmaengine: ti: k3-udma-v2: Add support for PKTDMA V2 Sai Sree Kartheek Adivi
2026-09-28 3:21 ` sashiko-bot
2026-09-28 8:39 ` Vignesh Raghavendra
2026-10-01 7:17 ` Sai Sree Kartheek Adivi
2026-09-28 2:56 ` Sai Sree Kartheek Adivi [this message]
2026-09-28 3:17 ` [PATCH v10 18/19] dmaengine: ti: k3-udma-v2: Update glue layer to support " sashiko-bot
2026-09-28 2:56 ` [PATCH v10 19/19] dmaengine: ti: k3-udma: Validate resource ID and fix logging in reservation Sai Sree Kartheek Adivi
2026-09-28 8:39 ` Vignesh Raghavendra
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