[PATCH v2 0/3] i3c: dw: Support Synaptics sl2610 i3c

[PATCH v2 0/3] i3c: dw: Support Synaptics sl2610 i3c

[Jisheng Zhang]

This is subset of the "arm64: add Synaptics SL261X SoCs and RDK boards"
series.

Support the Synaptics SL2610 SoC I3C controller, which is compatible
with the Synopsys DesignWare I3C.

Since v1:
 - collect Reviewed-by tag
 - use sl2610 instead of sl261x
 - restrict altera i3c reset to 1
 - send as a separate series for i3c subsystem

Jisheng Zhang (3):
  dt-bindings: i3c: dw: support up to two reset lines
  i3c: dw: switch to array-based exclusive reset control
  dt-bindings: i3c: Add Synaptics sl2610 i3c

 .../bindings/i3c/snps,dw-i3c-master.yaml      | 16 +++++++++++--
 drivers/i3c/master/dw-i3c-master.c            | 24 ++++++++++++++-----
 drivers/i3c/master/dw-i3c-master.h            |  2 +-
 3 files changed, 33 insertions(+), 9 deletions(-)

-- 
2.53.0

[PATCH v2 1/3] dt-bindings: i3c: dw: support up to two reset lines

[Jisheng Zhang]

The Synopsys DesignWare I3C master controller can have multiple reset
lines, such as core reset, apb reset, and dma reset.

Update the DT binding documentation to increase maxItems for the resets
property to 2.

Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
---
 .../devicetree/bindings/i3c/snps,dw-i3c-master.yaml  | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml b/Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml
index dc7ee38001d6..6da7d90caa3e 100644
--- a/Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml
+++ b/Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml
@@ -12,6 +12,16 @@ maintainers:
 allOf:
   - $ref: i3c.yaml#
 
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: altr,agilex5-dw-i3c-master
+    then:
+      properties:
+        resets:
+          maxItems: 1
+
 properties:
   compatible:
     oneOf:
@@ -39,7 +49,7 @@ properties:
     maxItems: 1
 
   resets:
-    maxItems: 1
+    maxItems: 2
 
   power-domains:
     maxItems: 1
-- 
2.53.0

[PATCH v2 2/3] i3c: dw: switch to array-based exclusive reset control

[Jisheng Zhang]

The Synopsys DesignWare I3C master controller can have multiple reset
lines, such as a core reset and APB reset.

Refactor the driver to use devm_reset_control_array_get_exclusive()
instead of a single named reset handle. This automatically manages all
resets allocated to the device node sequentially.

Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
---
 drivers/i3c/master/dw-i3c-master.c | 24 ++++++++++++++++++------
 drivers/i3c/master/dw-i3c-master.h |  2 +-
 2 files changed, 19 insertions(+), 7 deletions(-)

diff --git a/drivers/i3c/master/dw-i3c-master.c b/drivers/i3c/master/dw-i3c-master.c
index 4563d8761ba0..1c6c870f5bb3 100644
--- a/drivers/i3c/master/dw-i3c-master.c
+++ b/drivers/i3c/master/dw-i3c-master.c
@@ -1657,6 +1657,11 @@ static const struct dw_i3c_platform_ops dw_i3c_platform_ops_default = {
 	.set_dat_ibi = dw_i3c_platform_set_dat_ibi_nop,
 };
 
+static void dw_i3c_resets_assert(void *data)
+{
+	reset_control_assert(data);
+}
+
 int dw_i3c_common_probe(struct dw_i3c_master *master,
 			struct platform_device *pdev)
 {
@@ -1696,10 +1701,17 @@ int dw_i3c_common_probe(struct dw_i3c_master *master,
 	if (IS_ERR(master->pclk))
 		return PTR_ERR(master->pclk);
 
-	master->core_rst = devm_reset_control_get_optional_exclusive_deasserted(&pdev->dev,
-										NULL);
-	if (IS_ERR(master->core_rst))
-		return PTR_ERR(master->core_rst);
+	master->resets = devm_reset_control_array_get_optional_exclusive(&pdev->dev);
+	if (IS_ERR(master->resets))
+		return PTR_ERR(master->resets);
+
+	ret = reset_control_deassert(master->resets);
+	if (ret)
+		return ret;
+
+	ret = devm_add_action_or_reset(&pdev->dev, dw_i3c_resets_assert, master->resets);
+	if (ret)
+		return ret;
 
 	spin_lock_init(&master->xferqueue.lock);
 	INIT_LIST_HEAD(&master->xferqueue.list);
@@ -1873,7 +1885,7 @@ static int __maybe_unused dw_i3c_master_runtime_suspend(struct device *dev)
 
 	dw_i3c_master_disable(master);
 
-	reset_control_assert(master->core_rst);
+	reset_control_assert(master->resets);
 	dw_i3c_master_disable_clks(master);
 	pinctrl_pm_select_sleep_state(dev);
 	return 0;
@@ -1885,7 +1897,7 @@ static int __maybe_unused dw_i3c_master_runtime_resume(struct device *dev)
 
 	pinctrl_pm_select_default_state(dev);
 	dw_i3c_master_enable_clks(master);
-	reset_control_deassert(master->core_rst);
+	reset_control_deassert(master->resets);
 
 	dw_i3c_master_set_intr_regs(master);
 	dw_i3c_master_restore_timing_regs(master);
diff --git a/drivers/i3c/master/dw-i3c-master.h b/drivers/i3c/master/dw-i3c-master.h
index 17ad817d1f8e..f5b4491b247a 100644
--- a/drivers/i3c/master/dw-i3c-master.h
+++ b/drivers/i3c/master/dw-i3c-master.h
@@ -36,7 +36,7 @@ struct dw_i3c_master {
 	} xferqueue;
 	struct dw_i3c_master_caps caps;
 	void __iomem *regs;
-	struct reset_control *core_rst;
+	struct reset_control *resets;
 	struct clk *core_clk;
 	struct clk *pclk;
 	char version[5];
-- 
2.53.0

[PATCH v2 3/3] dt-bindings: i3c: Add Synaptics sl2610 i3c

[Jisheng Zhang]

Add the compatible for the Synaptics SL2610 SoC I3C controller, which
is compatible with the Synopsys DesignWare I3C.

Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
---
 Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml b/Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml
index 6da7d90caa3e..6806a22114f9 100644
--- a/Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml
+++ b/Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml
@@ -27,7 +27,9 @@ properties:
     oneOf:
       - const: snps,dw-i3c-master-1.00a
       - items:
-          - const: altr,agilex5-dw-i3c-master
+          - enum:
+              - altr,agilex5-dw-i3c-master
+              - syna,sl2610-i3c
           - const: snps,dw-i3c-master-1.00a
 
   reg:
-- 
2.53.0

Re: [PATCH v2 1/3] dt-bindings: i3c: dw: support up to two reset lines

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Medium] dt-bindings: i3c: dw: maxItems mismatch with commit message
- [Low] dt-bindings: i3c: dw: missing items/reset-names for multiple resets
--

commit 6da78b08867272d83c36c1c30ce43bb39d9aaf6d
Author: Jisheng Zhang <jszhang@kernel.org>

dt-bindings: i3c: dw: support up to two reset lines

This commit updates the Synopsys DesignWare I3C master controller device tree
binding to support multiple reset lines. It increases the maxItems for the
resets property to 2 and adds a conditional block to maintain the previous
limit for the Agilex 5 variant.

> The Synopsys DesignWare I3C master controller can have multiple reset
> lines, such as core reset, apb reset, and dma reset.
> 
> Update the DT binding documentation to increase maxItems for the resets
> property to 2.

[Severity: Medium]
The commit message explicitly lists three distinct reset lines (core reset,
apb reset, and dma reset). Does limiting the property to 2 directly
contradict the hardware capabilities described?

A hardware configuration wired with all three resets would fail schema
validation, and the follow-up patches in the series do not appear to fix
this mismatch.

> diff --git a/Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml b/Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml
> --- a/Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml
> +++ b/Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml
[ ... ]
> @@ -39,7 +49,7 @@ properties:
>      maxItems: 1
>  
>    resets:
> -    maxItems: 1
> +    maxItems: 2

[Severity: Low]
When allowing multiple items in an array, does the schema need to document
the exact order (via an items list) or require reset-names?

Without a strict documented order or reset-names, the OS-independent ABI
remains ambiguous. Although a follow-up patch in this series (commit "i3c:
dw: switch to array-based exclusive reset control") updates the Linux driver
to use devm_reset_control_array_get_optional_exclusive to fetch all resets
regardless of order, the device tree binding itself remains incomplete.

Other OSes or future drivers that may need to toggle these distinct reset
lines sequentially currently have no ABI to rely on.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261005152425.25319-1-jszhang@kernel.org?part=1

Re: [PATCH v2 3/3] dt-bindings: i3c: Add Synaptics sl2610 i3c

[Conor Dooley]

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Acked-by: Conor Dooley <conor.dooley@microchip.com>
pw-bot: not-applicable

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Re: [PATCH v2 1/3] dt-bindings: i3c: dw: support up to two reset lines

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 75 bytes --]

Acked-by: Conor Dooley <conor.dooley@microchip.com>
pw-bot: not-applicable

[-- Attachment #2: signature.asc --]
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Re: [PATCH v2 0/3] i3c: dw: Support Synaptics sl2610 i3c

[Alexandre Belloni]

On Mon, 05 Oct 2026 23:24:22 +0800, Jisheng Zhang wrote:
> This is subset of the "arm64: add Synaptics SL261X SoCs and RDK boards"
> series.
> 
> Support the Synaptics SL2610 SoC I3C controller, which is compatible
> with the Synopsys DesignWare I3C.
> 
> Since v1:
>  - collect Reviewed-by tag
>  - use sl2610 instead of sl261x
>  - restrict altera i3c reset to 1
>  - send as a separate series for i3c subsystem
> 
> [...]

Applied, thanks!

[1/3] dt-bindings: i3c: dw: support up to two reset lines
      https://git.kernel.org/i3c/c/6931331f48dc
[2/3] i3c: dw: switch to array-based exclusive reset control
      https://git.kernel.org/i3c/c/224e3606711d
[3/3] dt-bindings: i3c: Add Synaptics sl2610 i3c
      https://git.kernel.org/i3c/c/fc5eb1b0631a

Best regards,

-- 
Alexandre Belloni, co-owner and COO, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com