* [PATCH v2 0/2] arm64: dts: socfpga: agilex: add SoCDK multi-QSPI board @ 2026-10-06 2:54 genevieve.chan 2026-10-06 2:54 ` [PATCH v2 1/2] dt-bindings: arm: altera: add Agilex " genevieve.chan 2026-10-06 2:54 ` [PATCH v2 2/2] arm64: dts: socfpga: agilex: " genevieve.chan 0 siblings, 2 replies; 6+ messages in thread From: genevieve.chan @ 2026-10-06 2:54 UTC (permalink / raw) To: Dinh Nguyen, Rob Herring, Krzysztof Kozlowski, Conor Dooley Cc: devicetree, linux-kernel From: Genevieve Chan <genevieve.chan@altera.com> The Agilex SoCDK is populated with a single QSPI flash by default. A multi-QSPI daughter board can be fitted in its place. That board connects four Micron MT25QU02G devices (256 MiB each, 1 GiB total) to the HPS QSPI controller on chip selects 0-3. Each device is one "Boot and fpga data" partition covering the whole flash, and is described in quad mode at 25 MHz. This is a board-level population difference, in the same way the existing SoCDK eMMC and NAND variants differ from the default SoCDK. The HPS is the Agilex SoC, later marketed as Agilex 7 F-Series. The programming model is unchanged, so the board falls back to "intel,socfpga-agilex" and does not add an F-Series SoC compatible. Agilex 7 M-Series is a different device and already has its own fallback. Patch 1 documents that compatible next to the other Agilex SoCDK boards. Patch 2 adds socfpga_agilex_socdk_multiqspi.dts. UART, Ethernet, USB, SDMMC, LEDs and the watchdog match the SoCDK; the QSPI node is the difference. Changes in v2: - Rename the compatible, DTS filename and model, dropping "agilex7f". - State in the binding patch why the fallback is "intel,socfpga-agilex". - Describe the daughter card instead of restating the diff. Genevieve Chan (2): dt-bindings: arm: altera: add Agilex SoCDK multi-QSPI board arm64: dts: socfpga: agilex: add Agilex SoCDK multi-QSPI board Documentation/devicetree/bindings/arm/altera.yaml | 1 + arch/arm64/boot/dts/intel/Makefile | 1 + .../dts/intel/socfpga_agilex_socdk_multiqspi.dts | 213 +++++++++++++++++++++ 3 files changed, 215 insertions(+) base-commit: 04a1d21330501b113ba04efb81724f1c95ad2db8 -- 2.43.7 ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v2 1/2] dt-bindings: arm: altera: add Agilex SoCDK multi-QSPI board 2026-10-06 2:54 [PATCH v2 0/2] arm64: dts: socfpga: agilex: add SoCDK multi-QSPI board genevieve.chan @ 2026-10-06 2:54 ` genevieve.chan 2026-10-07 10:31 ` Conor Dooley 2026-10-06 2:54 ` [PATCH v2 2/2] arm64: dts: socfpga: agilex: " genevieve.chan 1 sibling, 1 reply; 6+ messages in thread From: genevieve.chan @ 2026-10-06 2:54 UTC (permalink / raw) To: Dinh Nguyen, Rob Herring, Krzysztof Kozlowski, Conor Dooley Cc: devicetree, linux-kernel From: Genevieve Chan <genevieve.chan@altera.com> The Agilex SoCDK can be fitted with a multi-QSPI daughter card in place of the default single-flash QSPI card. The multi-QSPI card carries four Micron MT25QU02G flashes connected to the HPS QSPI controller on chip selects 0-3. The different flash population requires a separate board DTS, hence, add a board compatible for it, following the existing SoCDK variants. The board uses the Agilex SoC (marketed as Agilex 7 F-Series), so it falls back to "intel,socfpga-agilex". Signed-off-by: Genevieve Chan <genevieve.chan@altera.com> --- Changes in v2: - Rename compatible from intel,socfpga-agilex7f-socdk-multiqspi to intel,socfpga-agilex-socdk-multiqspi. - Describe the hardware difference in the commit message. Documentation/devicetree/bindings/arm/altera.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/altera.yaml b/Documentation/devicetree/bindings/arm/altera.yaml index 5fce1161210e..01f6323b9a6b 100644 --- a/Documentation/devicetree/bindings/arm/altera.yaml +++ b/Documentation/devicetree/bindings/arm/altera.yaml @@ -97,6 +97,7 @@ properties: - intel,socfpga-agilex-n6000 - intel,socfpga-agilex-socdk - intel,socfpga-agilex-socdk-emmc + - intel,socfpga-agilex-socdk-multiqspi - const: intel,socfpga-agilex - description: Agilex3 boards -- 2.43.7 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v2 1/2] dt-bindings: arm: altera: add Agilex SoCDK multi-QSPI board 2026-10-06 2:54 ` [PATCH v2 1/2] dt-bindings: arm: altera: add Agilex " genevieve.chan @ 2026-10-07 10:31 ` Conor Dooley 0 siblings, 0 replies; 6+ messages in thread From: Conor Dooley @ 2026-10-07 10:31 UTC (permalink / raw) To: genevieve.chan Cc: Dinh Nguyen, Rob Herring, Krzysztof Kozlowski, Conor Dooley, devicetree, linux-kernel [-- Attachment #1: Type: text/plain, Size: 75 bytes --] Acked-by: Conor Dooley <conor.dooley@microchip.com> pw-bot: not-applicable [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v2 2/2] arm64: dts: socfpga: agilex: add Agilex SoCDK multi-QSPI board 2026-10-06 2:54 [PATCH v2 0/2] arm64: dts: socfpga: agilex: add SoCDK multi-QSPI board genevieve.chan 2026-10-06 2:54 ` [PATCH v2 1/2] dt-bindings: arm: altera: add Agilex " genevieve.chan @ 2026-10-06 2:54 ` genevieve.chan 2026-10-06 3:02 ` sashiko-bot 2026-10-07 13:43 ` Dinh Nguyen 1 sibling, 2 replies; 6+ messages in thread From: genevieve.chan @ 2026-10-06 2:54 UTC (permalink / raw) To: Dinh Nguyen, Rob Herring, Krzysztof Kozlowski, Conor Dooley Cc: devicetree, linux-kernel From: Genevieve Chan <genevieve.chan@altera.com> Add a device tree for the Agilex SoCDK fitted with the multi-QSPI daughter board. The daughter board replaces the single QSPI flash of the default SoCDK with four Micron MT25QU02G flashes on chip selects 0-3, which allows the system to use up to 1 GiB of QSPI storage. The board is otherwise identical to the SoCDK and builds on socfpga_agilex.dtsi. Signed-off-by: Genevieve Chan <genevieve.chan@altera.com> --- Changes in v2: - Rename file, compatible and model to drop the "agilex7f" prefix. - Reword commit message to describe the hardware. arch/arm64/boot/dts/intel/Makefile | 1 + .../intel/socfpga_agilex_socdk_multiqspi.dts | 213 ++++++++++++++++++ 2 files changed, 214 insertions(+) create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex_socdk_multiqspi.dts diff --git a/arch/arm64/boot/dts/intel/Makefile b/arch/arm64/boot/dts/intel/Makefile index b52cd2330cef..071bad408688 100644 --- a/arch/arm64/boot/dts/intel/Makefile +++ b/arch/arm64/boot/dts/intel/Makefile @@ -2,6 +2,7 @@ dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_agilex_n6000.dtb \ socfpga_agilex_socdk.dtb \ socfpga_agilex_socdk_emmc.dtb \ + socfpga_agilex_socdk_multiqspi.dtb \ socfpga_agilex_socdk_nand.dtb \ socfpga_agilex3_socdk.dtb \ socfpga_agilex5_socdk.dtb \ diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_multiqspi.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_multiqspi.dts new file mode 100644 index 000000000000..0bf087fa7553 --- /dev/null +++ b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_multiqspi.dts @@ -0,0 +1,213 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2026, Intel Corporation + */ +#include "socfpga_agilex.dtsi" + +/ { + model = "SoCFPGA Agilex SoCDK multi-QSPI daughter board"; + compatible = "intel,socfpga-agilex-socdk-multiqspi", "intel,socfpga-agilex"; + + aliases { + serial0 = &uart0; + ethernet0 = &gmac0; + ethernet1 = &gmac1; + ethernet2 = &gmac2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + led0 { + label = "hps_led0"; + gpios = <&portb 20 GPIO_ACTIVE_HIGH>; + }; + + led1 { + label = "hps_led1"; + gpios = <&portb 19 GPIO_ACTIVE_HIGH>; + }; + + led2 { + label = "hps_led2"; + gpios = <&portb 21 GPIO_ACTIVE_HIGH>; + }; + }; + + memory@80000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the reg */ + reg = <0 0x80000000 0 0>; + }; +}; + +&gpio1 { + status = "okay"; +}; + +&gmac0 { + status = "okay"; + /* PHY delays are configured via skew properties */ + phy-mode = "rgmii"; + phy-handle = <&phy0>; + + max-frame-size = <9000>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy0: ethernet-phy@4 { + reg = <4>; + + txd0-skew-ps = <0>; /* -420ps */ + txd1-skew-ps = <0>; /* -420ps */ + txd2-skew-ps = <0>; /* -420ps */ + txd3-skew-ps = <0>; /* -420ps */ + rxd0-skew-ps = <420>; /* 0ps */ + rxd1-skew-ps = <420>; /* 0ps */ + rxd2-skew-ps = <420>; /* 0ps */ + rxd3-skew-ps = <420>; /* 0ps */ + txen-skew-ps = <0>; /* -420ps */ + txc-skew-ps = <900>; /* 0ps */ + rxdv-skew-ps = <420>; /* 0ps */ + rxc-skew-ps = <1680>; /* 780ps */ + }; + }; +}; + +&mmc { + status = "okay"; + cap-sd-highspeed; + broken-cd; + bus-width = <4>; + clk-phase-sd-hs = <0>, <135>; +}; + +&osc1 { + clock-frequency = <25000000>; +}; + +&uart0 { + status = "okay"; +}; + +&usb0 { + status = "okay"; + disable-over-current; +}; + +&watchdog0 { + status = "okay"; +}; + +&qspi { + status = "okay"; + + flash@0 { + compatible = "micron,mt25qu02g", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <25000000>; + + m25p,fast-read; + cdns,read-delay = <2>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + qspi_boot0: partition@0 { + label = "Boot and fpga data"; + reg = <0x0 0x10000000>; + }; + }; + }; + + flash@1 { + compatible = "micron,mt25qu02g", "jedec,spi-nor"; + reg = <1>; + spi-max-frequency = <25000000>; + + m25p,fast-read; + cdns,read-delay = <2>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + qspi_boot1: partition@0 { + label = "Boot and fpga data"; + reg = <0x0 0x10000000>; + }; + }; + }; + + flash@2 { + compatible = "micron,mt25qu02g", "jedec,spi-nor"; + reg = <2>; + spi-max-frequency = <25000000>; + + m25p,fast-read; + cdns,read-delay = <2>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + qspi_boot2: partition@0 { + label = "Boot and fpga data"; + reg = <0x0 0x10000000>; + }; + }; + }; + + flash@3 { + compatible = "micron,mt25qu02g", "jedec,spi-nor"; + reg = <3>; + spi-max-frequency = <25000000>; + + m25p,fast-read; + cdns,read-delay = <2>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + qspi_boot3: partition@0 { + label = "Boot and fpga data"; + reg = <0x0 0x10000000>; + }; + }; + }; +}; -- 2.43.7 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v2 2/2] arm64: dts: socfpga: agilex: add Agilex SoCDK multi-QSPI board 2026-10-06 2:54 ` [PATCH v2 2/2] arm64: dts: socfpga: agilex: " genevieve.chan @ 2026-10-06 3:02 ` sashiko-bot 2026-10-07 13:43 ` Dinh Nguyen 1 sibling, 0 replies; 6+ messages in thread From: sashiko-bot @ 2026-10-06 3:02 UTC (permalink / raw) To: genevieve.chan; +Cc: conor+dt, devicetree, robh Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider: - [Medium] mtd: duplicate partition labels across multi-QSPI flashes - [Low] dts: excessive duplication of SoCDK baseboard configuration -- commit e53835bafbaf52462a16d7064f169ecf5af12f67 Author: Genevieve Chan <genevieve.chan@altera.com> arm64: dts: socfpga: agilex: add Agilex SoCDK multi-QSPI board This commit adds a new device tree for the Agilex SoCDK multi-QSPI daughter board, which replaces the single QSPI flash with four micron flashes. The board is otherwise identical to the standard SoCDK. > diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_multiqspi.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_multiqspi.dts > new file mode 100644 > --- /dev/null > +++ b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_multiqspi.dts > @@ -0,0 +1,213 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (C) 2026, Intel Corporation > + */ > +#include "socfpga_agilex.dtsi" > + > +/ { > + model = "SoCFPGA Agilex SoCDK multi-QSPI daughter board"; > + compatible = "intel,socfpga-agilex-socdk-multiqspi", "intel,socfpga-agilex"; > + > + aliases { > + serial0 = &uart0; > + ethernet0 = &gmac0; > + ethernet1 = &gmac1; > + ethernet2 = &gmac2; > + }; [Severity: Low] This isn't a bug, but there appears to be a lot of duplicated baseboard configuration here. The commit message notes the board is otherwise identical to the SoCDK, but over 100 lines of baseboard definitions like these aliases, memory, LEDs, Ethernet MAC, MMC, and UART are copied directly from the socfpga_agilex_socdk device tree. Would it be better to extract this shared configuration into a common socfpga_agilex_socdk.dtsi to prevent the board definitions from drifting out of sync over time? [ ... ] > + flash@0 { > + compatible = "micron,mt25qu02g", "jedec,spi-nor"; > + reg = <0>; [ ... ] > + partitions { > + compatible = "fixed-partitions"; > + #address-cells = <1>; > + #size-cells = <1>; > + > + qspi_boot0: partition@0 { > + label = "Boot and fpga data"; > + reg = <0x0 0x10000000>; > + }; > + }; > + }; > + > + flash@1 { > + compatible = "micron,mt25qu02g", "jedec,spi-nor"; > + reg = <1>; [ ... ] > + partitions { > + compatible = "fixed-partitions"; > + #address-cells = <1>; > + #size-cells = <1>; > + > + qspi_boot1: partition@0 { > + label = "Boot and fpga data"; > + reg = <0x0 0x10000000>; > + }; > + }; > + }; [Severity: Medium] Is it intentional to use the exact same partition label for flash@0, flash@1, flash@2, and flash@3? When the device tree is parsed at boot, the Linux MTD subsystem uses this label to identify the partition to userspace. Having four partitions with identical names breaks name-based access like /dev/mtd/by-name/ or root=mtd: because userspace tools will only be able to uniquely address the first matched partition. Additionally, since flashes on CS1 through CS3 are typically not boot flashes, the shared label could be misleading. Could these labels be made unique for each individual flash? -- Sashiko AI review · https://sashiko.dev/#/patchset/20261006025418.31931-1-genevieve.chan@altera.com?part=2 ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v2 2/2] arm64: dts: socfpga: agilex: add Agilex SoCDK multi-QSPI board 2026-10-06 2:54 ` [PATCH v2 2/2] arm64: dts: socfpga: agilex: " genevieve.chan 2026-10-06 3:02 ` sashiko-bot @ 2026-10-07 13:43 ` Dinh Nguyen 1 sibling, 0 replies; 6+ messages in thread From: Dinh Nguyen @ 2026-10-07 13:43 UTC (permalink / raw) To: genevieve.chan, Rob Herring, Krzysztof Kozlowski, Conor Dooley Cc: devicetree, linux-kernel NIT: your commit header "arm64: dts: socfpga: agilex: add Agilex SoCDK multi-QSPI board" Avoid using the same name multiple times. Please reword this to arm64: dts: socfpga: agilex: add SoCDK multi-QSPI board or arm64: dts: socfpga: add Agilex SoCDK multi-QSPI board On 10/5/26 21:54, genevieve.chan@altera.com wrote: > From: Genevieve Chan <genevieve.chan@altera.com> > > Add a device tree for the Agilex SoCDK fitted with the multi-QSPI > daughter board. The daughter board replaces the single QSPI flash of > the default SoCDK with four Micron MT25QU02G flashes on chip selects > 0-3, which allows the system to use up to 1 GiB of QSPI storage. > > The board is otherwise identical to the SoCDK and builds on > socfpga_agilex.dtsi. > > Signed-off-by: Genevieve Chan <genevieve.chan@altera.com> > --- > Changes in v2: > - Rename file, compatible and model to drop the "agilex7f" prefix. > - Reword commit message to describe the hardware. > > arch/arm64/boot/dts/intel/Makefile | 1 + > .../intel/socfpga_agilex_socdk_multiqspi.dts | 213 ++++++++++++++++++ > 2 files changed, 214 insertions(+) > create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex_socdk_multiqspi.dts > > diff --git a/arch/arm64/boot/dts/intel/Makefile b/arch/arm64/boot/dts/intel/Makefile > index b52cd2330cef..071bad408688 100644 > --- a/arch/arm64/boot/dts/intel/Makefile > +++ b/arch/arm64/boot/dts/intel/Makefile > @@ -2,6 +2,7 @@ > dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_agilex_n6000.dtb \ > socfpga_agilex_socdk.dtb \ > socfpga_agilex_socdk_emmc.dtb \ > + socfpga_agilex_socdk_multiqspi.dtb \ > socfpga_agilex_socdk_nand.dtb \ > socfpga_agilex3_socdk.dtb \ > socfpga_agilex5_socdk.dtb \ > diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_multiqspi.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_multiqspi.dts > new file mode 100644 > index 000000000000..0bf087fa7553 > --- /dev/null > +++ b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_multiqspi.dts > @@ -0,0 +1,213 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (C) 2026, Intel Corporation > + */ > +#include "socfpga_agilex.dtsi" > + > +/ { > + model = "SoCFPGA Agilex SoCDK multi-QSPI daughter board"; > + compatible = "intel,socfpga-agilex-socdk-multiqspi", "intel,socfpga-agilex"; > + > + aliases { > + serial0 = &uart0; > + ethernet0 = &gmac0; > + ethernet1 = &gmac1; > + ethernet2 = &gmac2; > + }; > + > + chosen { > + stdout-path = "serial0:115200n8"; > + }; > + > + leds { > + compatible = "gpio-leds"; > + led0 { > + label = "hps_led0"; > + gpios = <&portb 20 GPIO_ACTIVE_HIGH>; > + }; > + > + led1 { > + label = "hps_led1"; > + gpios = <&portb 19 GPIO_ACTIVE_HIGH>; > + }; > + > + led2 { > + label = "hps_led2"; > + gpios = <&portb 21 GPIO_ACTIVE_HIGH>; > + }; > + }; > + > + memory@80000000 { > + device_type = "memory"; > + /* We expect the bootloader to fill in the reg */ > + reg = <0 0x80000000 0 0>; > + }; > +}; > + > +&gpio1 { > + status = "okay"; > +}; > + > +&gmac0 { > + status = "okay"; > + /* PHY delays are configured via skew properties */ > + phy-mode = "rgmii"; > + phy-handle = <&phy0>; > + > + max-frame-size = <9000>; > + > + mdio0 { > + #address-cells = <1>; > + #size-cells = <0>; > + compatible = "snps,dwmac-mdio"; > + phy0: ethernet-phy@4 { > + reg = <4>; > + > + txd0-skew-ps = <0>; /* -420ps */ > + txd1-skew-ps = <0>; /* -420ps */ > + txd2-skew-ps = <0>; /* -420ps */ > + txd3-skew-ps = <0>; /* -420ps */ > + rxd0-skew-ps = <420>; /* 0ps */ > + rxd1-skew-ps = <420>; /* 0ps */ > + rxd2-skew-ps = <420>; /* 0ps */ > + rxd3-skew-ps = <420>; /* 0ps */ > + txen-skew-ps = <0>; /* -420ps */ > + txc-skew-ps = <900>; /* 0ps */ > + rxdv-skew-ps = <420>; /* 0ps */ > + rxc-skew-ps = <1680>; /* 780ps */ > + }; > + }; > +}; > + > +&mmc { > + status = "okay"; > + cap-sd-highspeed; > + broken-cd; > + bus-width = <4>; > + clk-phase-sd-hs = <0>, <135>; > +}; > + > +&osc1 { > + clock-frequency = <25000000>; > +}; > + > +&uart0 { > + status = "okay"; > +}; > + > +&usb0 { > + status = "okay"; > + disable-over-current; > +}; > + > +&watchdog0 { > + status = "okay"; > +}; > + > +&qspi { > + status = "okay"; > + > + flash@0 { > + compatible = "micron,mt25qu02g", "jedec,spi-nor"; > + reg = <0>; > + spi-max-frequency = <25000000>; The devkit has 100 MHz, why is this card only 25M MHz? > + > + m25p,fast-read; > + cdns,read-delay = <2>; > + cdns,tshsl-ns = <50>; > + cdns,tsd2d-ns = <50>; > + cdns,tchsh-ns = <4>; > + cdns,tslch-ns = <4>; > + spi-tx-bus-width = <4>; > + spi-rx-bus-width = <4>; > + > + partitions { > + compatible = "fixed-partitions"; > + #address-cells = <1>; > + #size-cells = <1>; > + > + qspi_boot0: partition@0 { > + label = "Boot and fpga data"; > + reg = <0x0 0x10000000>; > + }; > + }; > + }; > + > + flash@1 { > + compatible = "micron,mt25qu02g", "jedec,spi-nor"; > + reg = <1>; > + spi-max-frequency = <25000000>; > + > + m25p,fast-read; > + cdns,read-delay = <2>; > + cdns,tshsl-ns = <50>; > + cdns,tsd2d-ns = <50>; > + cdns,tchsh-ns = <4>; > + cdns,tslch-ns = <4>; > + spi-tx-bus-width = <4>; > + spi-rx-bus-width = <4>; > + > + partitions { > + compatible = "fixed-partitions"; > + #address-cells = <1>; > + #size-cells = <1>; > + > + qspi_boot1: partition@0 { > + label = "Boot and fpga data"; > + reg = <0x0 0x10000000>; > + }; > + }; > + }; > + > + flash@2 { > + compatible = "micron,mt25qu02g", "jedec,spi-nor"; > + reg = <2>; > + spi-max-frequency = <25000000>; > + > + m25p,fast-read; > + cdns,read-delay = <2>; > + cdns,tshsl-ns = <50>; > + cdns,tsd2d-ns = <50>; > + cdns,tchsh-ns = <4>; > + cdns,tslch-ns = <4>; > + spi-tx-bus-width = <4>; > + spi-rx-bus-width = <4>; > + > + partitions { > + compatible = "fixed-partitions"; > + #address-cells = <1>; > + #size-cells = <1>; > + > + qspi_boot2: partition@0 { > + label = "Boot and fpga data"; > + reg = <0x0 0x10000000>; > + }; > + }; > + }; > + > + flash@3 { > + compatible = "micron,mt25qu02g", "jedec,spi-nor"; > + reg = <3>; > + spi-max-frequency = <25000000>; > + > + m25p,fast-read; > + cdns,read-delay = <2>; > + cdns,tshsl-ns = <50>; > + cdns,tsd2d-ns = <50>; > + cdns,tchsh-ns = <4>; > + cdns,tslch-ns = <4>; > + spi-tx-bus-width = <4>; > + spi-rx-bus-width = <4>; > + > + partitions { > + compatible = "fixed-partitions"; > + #address-cells = <1>; > + #size-cells = <1>; > + > + qspi_boot3: partition@0 { > + label = "Boot and fpga data"; Sashiko's comment on this is valid. You give these label a unique name, "Boot and fpga data 3" Dinh ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2026-10-07 13:43 UTC | newest] Thread overview: 6+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2026-10-06 2:54 [PATCH v2 0/2] arm64: dts: socfpga: agilex: add SoCDK multi-QSPI board genevieve.chan 2026-10-06 2:54 ` [PATCH v2 1/2] dt-bindings: arm: altera: add Agilex " genevieve.chan 2026-10-07 10:31 ` Conor Dooley 2026-10-06 2:54 ` [PATCH v2 2/2] arm64: dts: socfpga: agilex: " genevieve.chan 2026-10-06 3:02 ` sashiko-bot 2026-10-07 13:43 ` Dinh Nguyen
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