From: Ali Rouhi <arouhi@sitime.com>
To: "sashiko-reviews@lists.linux.dev" <sashiko-reviews@lists.linux.dev>
Cc: Jiri Pirko <jiri@resnulli.us>,
Vadim Fedorenko <vadim.fedorenko@linux.dev>,
Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>,
Ivan Vecera <ivecera@redhat.com>,
Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>,
Carolina Jubran <cjubran@nvidia.com>,
Oleg Zadorozhnyi <Oleg.Zadorozhnyi@devoxsoftware.com>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"netdev@vger.kernel.org" <netdev@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH net-next v13 02/12] dt-bindings: dpll: add SiTime SiT95316 clock generator
Date: Fri, 16 Oct 2026 00:55:42 +0000 [thread overview]
Message-ID: <20261016005541.11374-1-arouhi@sitime.com> (raw)
In-Reply-To: <sashiko-outbox-171992@kernel.org>
On Wed, 14 Oct 2026, sashiko-bot@kernel.org wrote:
Reply inline.
> [Severity: Low] The description states this must be a single entry,
> but should there be a maxItems: 1 constraint to structurally enforce
> this? Without it, a device tree node providing an array of multiple
> 64-bit frequencies for an input pin will silently pass schema
> validation.
Agreed, and v14 adds it.
The example was the problem, not the schema. The rates were written
/bits/ 64, and supported-frequencies-hz is a 32-bit type, so each rate
decoded as two cells and maxItems: 1 failed on the example itself:
input-pins:pin@0:supported-frequencies-hz: [[0], [10000000]] is too long
Rob Herring asked for the 32-bit width on this patch independently.
With the examples corrected the constraint holds, and it is in v14 on
the input pin list. The output pins keep an unbounded list, since an
output can be set to any of several rates.
next prev parent reply other threads:[~2026-10-16 0:55 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-13 22:41 [PATCH net-next v13 00/12] dpll: add SiTime SiT9531x DPLL clock driver Ali Rouhi
2026-10-13 22:41 ` [PATCH net-next v13 01/12] dt-bindings: vendor-prefixes: add SiTime Corporation Ali Rouhi
2026-10-13 22:41 ` [PATCH net-next v13 02/12] dt-bindings: dpll: add SiTime SiT95316 clock generator Ali Rouhi
2026-10-14 22:41 ` sashiko-bot
2026-10-16 0:55 ` Ali Rouhi [this message]
2026-10-15 3:31 ` Rob Herring
2026-10-16 0:55 ` Ali Rouhi
2026-10-13 22:41 ` [PATCH net-next v13 03/12] dpll: add basic SiTime SiT9531x support Ali Rouhi
2026-10-13 22:41 ` [PATCH net-next v13 04/12] dpll: sit9531x: read DPLL types and pin properties from system firmware Ali Rouhi
2026-10-14 22:41 ` sashiko-bot
2026-10-16 0:55 ` Ali Rouhi
2026-10-13 22:41 ` [PATCH net-next v13 06/12] dpll: sit9531x: implement input pin state on a DPLL Ali Rouhi
2026-10-13 22:41 ` [PATCH net-next v13 05/12] dpll: sit9531x: register DPLL devices and pins Ali Rouhi
2026-10-14 22:41 ` sashiko-bot
2026-10-16 0:55 ` Ali Rouhi
2026-10-13 22:41 ` [PATCH net-next v13 08/12] dpll: sit9531x: add support to get and set frequency on pins Ali Rouhi
2026-10-14 22:41 ` sashiko-bot
2026-10-16 0:55 ` Ali Rouhi
2026-10-13 22:41 ` [PATCH net-next v13 07/12] dpll: sit9531x: add support to get and set priority on input pins Ali Rouhi
2026-10-13 22:41 ` [PATCH net-next v13 10/12] dpll: sit9531x: add support to adjust output phase Ali Rouhi
2026-10-14 22:41 ` sashiko-bot
2026-10-16 0:55 ` Ali Rouhi
2026-10-13 22:41 ` [PATCH net-next v13 09/12] dpll: sit9531x: implement output pin state on a DPLL Ali Rouhi
2026-10-13 22:41 ` [PATCH net-next v13 12/12] dpll: sit9531x: model the inter-PLL sync net as a pair of pins Ali Rouhi
2026-10-14 22:41 ` sashiko-bot
2026-10-16 0:55 ` Ali Rouhi
2026-10-13 22:41 ` [PATCH net-next v13 11/12] dpll: sit9531x: add support to get phase offset on the connected input pin Ali Rouhi
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