[PATCH 0/8] drm/panel: novatek-nt36672e: Add SM8450 HDK display card

[PATCH 0/8] drm/panel: novatek-nt36672e: Add SM8450 HDK display card

[Vladimir Zapolskiy]

The series extends the NT36672E binding and driver to support the panel
module, and adds a device tree overlay for the SM8450 HDK display card.

The display card for the Qualcomm SM8450 HDK board carries an LCD panel
module based on the Novatek NT36672E display driver IC. Unlike the panel
module, which is supported by the NT36672E panel driver on the QCM6490
IDP board, the display card panel is connected over 3 MIPI C-PHY trios,
has a resolution of 1080x2400, and it runs at 144Hz with Display Stream
Compression, therefore a new panel configuration sequence is needed.

Since MIPI PHY type of the DSI link is fixed by the panel module design,
the driver selects the panel description by the PHY type of the DSI link.

The initialization sequence, the display timings and the DSC parameters
of the display card panel are taken from the Qualcomm display device
tree source for the panel:

  https://git.codelinaro.org/clo/la/platform/vendor/opensource/display-devicetree
  tag DISPLAY.LA.6.0.r12-02500-WAIPIO.QSSI17.0
  display/dsi-panel-nt36672e-fhd-plus-144hz-video-cphy.dtsi

The integrated touchscreen controller of the display card is not
described, since there is no binding or driver support for it yet.

Vladimir Zapolskiy (8):
  dt-bindings: display: panel: novatek,nt36672e: Document the reset GPIO polarity
  dt-bindings: display: panel: novatek,nt36672e: Add bias enable GPIO
  drm/panel: novatek-nt36672e: Make the AVDD and AVEE supplies optional
  drm/panel: novatek-nt36672e: Support the bias enable GPIO
  drm/panel: novatek-nt36672e: Verify the number of D-PHY data lanes
  drm/panel: novatek-nt36672e: Add support of the C-PHY panel module
  arm64: dts: qcom: sm8450-hdk: Add display card overlay
  arm64: dts: qcom: qcm6490-idp: Describe the panel bias enable GPIO

 .../display/panel/novatek,nt36672e.yaml       |  41 +-
 arch/arm64/boot/dts/qcom/Makefile             |   4 +
 arch/arm64/boot/dts/qcom/qcm6490-idp.dts      |  17 +-
 .../dts/qcom/sm8450-hdk-display-card.dtso     | 144 +++++
 drivers/gpu/drm/panel/Kconfig                 |   8 +-
 .../gpu/drm/panel/panel-novatek-nt36672e.c    | 596 +++++++++++++++++-
 6 files changed, 762 insertions(+), 48 deletions(-)
 create mode 100644 arch/arm64/boot/dts/qcom/sm8450-hdk-display-card.dtso


base-commit: 6b4b543fa18757297ac756a6fe6e64f506b7844a
-- 
2.51.0

[PATCH 1/8] dt-bindings: display: panel: novatek,nt36672e: Document the reset GPIO polarity

[Vladimir Zapolskiy]

The reset GPIO of NT36672E panels has been described as active high since
the binding was added, also see the example and the QCM6490 IDP board
device tree, however actually it serves as the active low signal, also
panel-common.yaml expects active low reset GPIOs to be described as such.

Document the active high description of the reset GPIO explicitly as
the exceptional deviation from the actual signal polarity, any new devices
will use it in the same way as the existing ones.

Signed-off-by: Vladimir Zapolskiy <vz@kernel.org>
---
 .../bindings/display/panel/novatek,nt36672e.yaml         | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/display/panel/novatek,nt36672e.yaml b/Documentation/devicetree/bindings/display/panel/novatek,nt36672e.yaml
index dc4672f3d01d..45743376995b 100644
--- a/Documentation/devicetree/bindings/display/panel/novatek,nt36672e.yaml
+++ b/Documentation/devicetree/bindings/display/panel/novatek,nt36672e.yaml
@@ -24,7 +24,14 @@ properties:
   avdd-supply: true
   avee-supply: true
   port: true
-  reset-gpios: true
+  reset-gpios:
+    maxItems: 1
+    description:
+      GPIO connected to the reset pin of the panel. The GPIO must be described
+      as active high (GPIO_ACTIVE_HIGH), the asserted state releases the panel
+      from reset. Note that the RESET_N pin is in fact an active low signal,
+      the inverted description is kept for compatibility with existing device
+      trees, while it deviates from the convention of panel-common.yaml.
   backlight: true
 
 required:
-- 
2.51.0

Re: [PATCH 1/8] dt-bindings: display: panel: novatek,nt36672e: Document the reset GPIO polarity

[Krzysztof Kozlowski]

On Wed, Oct 28, 2026 at 11:51:44AM +0200, Vladimir Zapolskiy wrote:
> The reset GPIO of NT36672E panels has been described as active high since
> the binding was added, also see the example and the QCM6490 IDP board
> device tree, however actually it serves as the active low signal, also
> panel-common.yaml expects active low reset GPIOs to be described as such.
> 
> Document the active high description of the reset GPIO explicitly as
> the exceptional deviation from the actual signal polarity, any new devices
> will use it in the same way as the existing ones.
> 
> Signed-off-by: Vladimir Zapolskiy <vz@kernel.org>
> ---
>  .../bindings/display/panel/novatek,nt36672e.yaml         | 9 ++++++++-
>  1 file changed, 8 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/display/panel/novatek,nt36672e.yaml b/Documentation/devicetree/bindings/display/panel/novatek,nt36672e.yaml
> index dc4672f3d01d..45743376995b 100644
> --- a/Documentation/devicetree/bindings/display/panel/novatek,nt36672e.yaml
> +++ b/Documentation/devicetree/bindings/display/panel/novatek,nt36672e.yaml
> @@ -24,7 +24,14 @@ properties:
>    avdd-supply: true
>    avee-supply: true
>    port: true
> -  reset-gpios: true
> +  reset-gpios:
> +    maxItems: 1
> +    description:
> +      GPIO connected to the reset pin of the panel. The GPIO must be described
> +      as active high (GPIO_ACTIVE_HIGH), the asserted state releases the panel

I disagree that it has to be active high, because, since we do not
represent pin inverters in DT, it depends on board layout. Wording would
need to be correct if this stays.

> +      from reset. Note that the RESET_N pin is in fact an active low signal,
> +      the inverted description is kept for compatibility with existing device
> +      trees, while it deviates from the convention of panel-common.yaml.

We might fix it at some point, so not sure if it is worth documenting in
the binding. And what about usage of this binding in other projects
which implement it correctly?

Best regards,
Krzysztof

Re: [PATCH 1/8] dt-bindings: display: panel: novatek,nt36672e: Document the reset GPIO polarity

[Vladimir Zapolskiy]

On 10/28/26 15:56, Krzysztof Kozlowski wrote:
> On Wed, Oct 28, 2026 at 11:51:44AM +0200, Vladimir Zapolskiy wrote:
>> The reset GPIO of NT36672E panels has been described as active high since
>> the binding was added, also see the example and the QCM6490 IDP board
>> device tree, however actually it serves as the active low signal, also
>> panel-common.yaml expects active low reset GPIOs to be described as such.
>>
>> Document the active high description of the reset GPIO explicitly as
>> the exceptional deviation from the actual signal polarity, any new devices
>> will use it in the same way as the existing ones.
>>
>> Signed-off-by: Vladimir Zapolskiy <vz@kernel.org>
>> ---
>>   .../bindings/display/panel/novatek,nt36672e.yaml         | 9 ++++++++-
>>   1 file changed, 8 insertions(+), 1 deletion(-)
>>
>> diff --git a/Documentation/devicetree/bindings/display/panel/novatek,nt36672e.yaml b/Documentation/devicetree/bindings/display/panel/novatek,nt36672e.yaml
>> index dc4672f3d01d..45743376995b 100644
>> --- a/Documentation/devicetree/bindings/display/panel/novatek,nt36672e.yaml
>> +++ b/Documentation/devicetree/bindings/display/panel/novatek,nt36672e.yaml
>> @@ -24,7 +24,14 @@ properties:
>>     avdd-supply: true
>>     avee-supply: true
>>     port: true
>> -  reset-gpios: true
>> +  reset-gpios:
>> +    maxItems: 1
>> +    description:
>> +      GPIO connected to the reset pin of the panel. The GPIO must be described
>> +      as active high (GPIO_ACTIVE_HIGH), the asserted state releases the panel
> 
> I disagree that it has to be active high, because, since we do not
> represent pin inverters in DT, it depends on board layout. Wording would
> need to be correct if this stays.
> 

I'm all for a better wording.

The described display panel device operates (here resets) according to
the active low signal RESET_N, the device driver is written to interpret
the signal as active high. A signal inverter may be present on a board, but
then the description of this board feature would belong to the board dts,
e.g. in a form of a simple comment around the property.

>> +      from reset. Note that the RESET_N pin is in fact an active low signal,
>> +      the inverted description is kept for compatibility with existing device
>> +      trees, while it deviates from the convention of panel-common.yaml.
> 
> We might fix it at some point, so not sure if it is worth documenting in
> the binding. And what about usage of this binding in other projects
> which implement it correctly?
> 

In the upstream there is only one user qcm6490-idp.dts, and changing
the polarity will be an ABI breaking change, unfortunately.

Here it's a similar story to another one about OV9282 reset-gpios polarity,
it ended up in keeping the polarity of the signal to avoid ABI breakage:

   https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/qcom/qrb2210-rb1-vision-mezzanine.dtso#n45

Probably the best way to operate here is to give a clear 'reset-gpios'
property description in the OV9282 sensor or this NT36672E panel dt docs.

-- 
Best wishes,
Vladimir

Re: [PATCH 1/8] dt-bindings: display: panel: novatek,nt36672e: Document the reset GPIO polarity

[Krzysztof Kozlowski]

On 28/10/2026 15:56, Vladimir Zapolskiy wrote:
>> We might fix it at some point, so not sure if it is worth documenting in
>> the binding. And what about usage of this binding in other projects
>> which implement it correctly?
>>
> 
> In the upstream there is only one user qcm6490-idp.dts, and changing
> the polarity will be an ABI breaking change, unfortunately.

And all other projects?

Best regards,
Krzysztof

Re: [PATCH 1/8] dt-bindings: display: panel: novatek,nt36672e: Document the reset GPIO polarity

[Vladimir Zapolskiy]

On 10/28/26 16:59, Krzysztof Kozlowski wrote:
> On 28/10/2026 15:56, Vladimir Zapolskiy wrote:
>>> We might fix it at some point, so not sure if it is worth documenting in
>>> the binding. And what about usage of this binding in other projects
>>> which implement it correctly?
>>>
>>
>> In the upstream there is only one user qcm6490-idp.dts, and changing
>> the polarity will be an ABI breaking change, unfortunately.
> 
> And all other projects?
> 

It might be a challenging task to check usage of "novatek,nt36672e"
compatible display panels in all other projects. I've asked about it:

* https://chatgpt.com/uc/6ae25571-2ef0-83ea-81e5-2522e70c4a93

The check gives this info:

1. Linux kernel - invalid GPIO polarity in the driver and qcm6490-idp.dts,
2. Android - invalid GPIO polarity in the copied driver and qcm6490-idp.dts,
3. FreeBSD - invalid GPIO polarity in the copied qcm6490-idp.dts, no driver.

Please let me know, if there are other projects to check. To my
understanding the RESET_N polarity cannot be corrected anymore,
and the best option is to clearly document a difference between
the device and its dt-binding documentation.

-- 
Best wishes,
Vladimir

[PATCH 2/8] dt-bindings: display: panel: novatek,nt36672e: Add bias enable GPIO

[Vladimir Zapolskiy]

The pair of positive and negative bias supplies of an NT36672E panel,
AVDD and AVEE, also known as VSP and VSN, are either provided by the host,
or generated on the panel module itself. In the latter case the module
exposes only a bias enable signal with no need to describe the supplies.

Make the AVDD and AVEE supplies optional, but require them to be
described together as the indivisible pair, and add an optional enable
GPIO for the bias enable signal of the panel module, which excludes
the bias supplies, if present in the actual device tree node.

Signed-off-by: Vladimir Zapolskiy <vz@kernel.org>
---
 .../display/panel/novatek,nt36672e.yaml       | 32 +++++++++++++++----
 1 file changed, 26 insertions(+), 6 deletions(-)

diff --git a/Documentation/devicetree/bindings/display/panel/novatek,nt36672e.yaml b/Documentation/devicetree/bindings/display/panel/novatek,nt36672e.yaml
index 45743376995b..daf2f96b8ed4 100644
--- a/Documentation/devicetree/bindings/display/panel/novatek,nt36672e.yaml
+++ b/Documentation/devicetree/bindings/display/panel/novatek,nt36672e.yaml
@@ -11,6 +11,13 @@ maintainers:
 
 allOf:
   - $ref: panel-common.yaml#
+  - if:
+      required:
+        - enable-gpios
+    then:
+      properties:
+        avdd-supply: false
+        avee-supply: false
 
 properties:
   compatible:
@@ -21,8 +28,20 @@ properties:
     description: DSI virtual channel
 
   vddi-supply: true
-  avdd-supply: true
-  avee-supply: true
+
+  avdd-supply:
+    description: Positive bias supply of the panel
+
+  avee-supply:
+    description: Negative bias supply of the panel
+
+  enable-gpios:
+    maxItems: 1
+    description:
+      GPIO connected to the bias enable signal of the panel module, which
+      switches on the positive and negative bias supplies generated on the
+      module. The signal is active high.
+
   port: true
   reset-gpios:
     maxItems: 1
@@ -38,11 +57,13 @@ required:
   - compatible
   - reg
   - vddi-supply
-  - avdd-supply
-  - avee-supply
   - reset-gpios
   - port
 
+dependentRequired:
+  avdd-supply: [avee-supply]
+  avee-supply: [avdd-supply]
+
 additionalProperties: false
 
 examples:
@@ -55,11 +76,10 @@ examples:
             compatible = "novatek,nt36672e";
             reg = <0>;
 
+            enable-gpios = <&pmic_gpios 8 GPIO_ACTIVE_HIGH>;
             reset-gpios = <&tlmm 44 GPIO_ACTIVE_HIGH>;
 
             vddi-supply = <&vreg_l8c_1p8>;
-            avdd-supply = <&disp_avdd>;
-            avee-supply = <&disp_avee>;
 
             backlight = <&pwm_backlight>;
 
-- 
2.51.0

Re: [PATCH 2/8] dt-bindings: display: panel: novatek,nt36672e: Add bias enable GPIO

[Krzysztof Kozlowski]

On Wed, Oct 28, 2026 at 11:51:45AM +0200, Vladimir Zapolskiy wrote:
> The pair of positive and negative bias supplies of an NT36672E panel,
> AVDD and AVEE, also known as VSP and VSN, are either provided by the host,
> or generated on the panel module itself. In the latter case the module
> exposes only a bias enable signal with no need to describe the supplies.
> 
> Make the AVDD and AVEE supplies optional, but require them to be
> described together as the indivisible pair, and add an optional enable
> GPIO for the bias enable signal of the panel module, which excludes
> the bias supplies, if present in the actual device tree node.
> 
> Signed-off-by: Vladimir Zapolskiy <vz@kernel.org>
> ---
>  .../display/panel/novatek,nt36672e.yaml       | 32 +++++++++++++++----
>  1 file changed, 26 insertions(+), 6 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/display/panel/novatek,nt36672e.yaml b/Documentation/devicetree/bindings/display/panel/novatek,nt36672e.yaml
> index 45743376995b..daf2f96b8ed4 100644
> --- a/Documentation/devicetree/bindings/display/panel/novatek,nt36672e.yaml
> +++ b/Documentation/devicetree/bindings/display/panel/novatek,nt36672e.yaml
> @@ -11,6 +11,13 @@ maintainers:
>  
>  allOf:
>    - $ref: panel-common.yaml#
> +  - if:
> +      required:
> +        - enable-gpios
> +    then:
> +      properties:
> +        avdd-supply: false
> +        avee-supply: false

Move entire allOf to the end, before unevaluated/additionalProperties
part.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>

Best regards,
Krzysztof

[PATCH 3/8] drm/panel: novatek-nt36672e: Make the AVDD and AVEE supplies optional

[Vladimir Zapolskiy]

The positive and negative bias supplies of an NT36672E panel, AVDD and
AVEE, are not exposed by the panel modules, which generate the bias on
the module itself.

Split the supplies into the required VDDI supply and the pair of AVDD
and AVEE bias supplies, which are either both described or both absent,
and get the bias supplies only if they are described.

Signed-off-by: Vladimir Zapolskiy <vz@kernel.org>
---
 .../gpu/drm/panel/panel-novatek-nt36672e.c    | 69 +++++++++++++------
 1 file changed, 49 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/panel/panel-novatek-nt36672e.c b/drivers/gpu/drm/panel/panel-novatek-nt36672e.c
index c5e00eb55722..80934c6bf250 100644
--- a/drivers/gpu/drm/panel/panel-novatek-nt36672e.c
+++ b/drivers/gpu/drm/panel/panel-novatek-nt36672e.c
@@ -13,16 +13,13 @@
 
 #include <video/mipi_display.h>
 
-static const char * const regulator_names[] = {
-	"vddi",
-	"avdd",
-	"avee",
+static const struct regulator_bulk_data nt36672e_supplies[] = {
+	{ .supply = "vddi", .init_load_uA = 62000 },
 };
 
-static const unsigned long regulator_enable_loads[] = {
-	62000,
-	100000,
-	100000,
+static const struct regulator_bulk_data nt36672e_bias_supplies[] = {
+	{ .supply = "avdd", .init_load_uA = 100000 },
+	{ .supply = "avee", .init_load_uA = 100000 },
 };
 
 struct panel_desc {
@@ -40,7 +37,8 @@ struct nt36672e_panel {
 	struct drm_panel panel;
 	struct mipi_dsi_device *dsi;
 	struct gpio_desc *reset_gpio;
-	struct regulator_bulk_data supplies[3];
+	struct regulator_bulk_data *supplies;
+	struct regulator_bulk_data *bias_supplies;
 	const struct panel_desc *desc;
 };
 
@@ -362,12 +360,23 @@ static int nt36672e_power_on(struct nt36672e_panel *ctx)
 	struct mipi_dsi_device *dsi = ctx->dsi;
 	int ret;
 
-	ret = regulator_bulk_enable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
+	ret = regulator_bulk_enable(ARRAY_SIZE(nt36672e_supplies), ctx->supplies);
 	if (ret < 0) {
 		dev_err(&dsi->dev, "regulator bulk enable failed: %d\n", ret);
 		return ret;
 	}
 
+	if (ctx->bias_supplies) {
+		ret = regulator_bulk_enable(ARRAY_SIZE(nt36672e_bias_supplies),
+					    ctx->bias_supplies);
+		if (ret < 0) {
+			dev_err(&dsi->dev, "bias regulator enable failed: %d\n", ret);
+			regulator_bulk_disable(ARRAY_SIZE(nt36672e_supplies),
+					       ctx->supplies);
+			return ret;
+		}
+	}
+
 	/*
 	 * Reset sequence of nt36672e panel requires the panel to be out of reset
 	 * for 10ms, followed by being held in reset for 10ms and then out again.
@@ -389,7 +398,14 @@ static int nt36672e_power_off(struct nt36672e_panel *ctx)
 
 	gpiod_set_value(ctx->reset_gpio, 0);
 
-	ret = regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
+	if (ctx->bias_supplies) {
+		ret = regulator_bulk_disable(ARRAY_SIZE(nt36672e_bias_supplies),
+					     ctx->bias_supplies);
+		if (ret)
+			dev_err(&dsi->dev, "bias regulator disable failed: %d\n", ret);
+	}
+
+	ret = regulator_bulk_disable(ARRAY_SIZE(nt36672e_supplies), ctx->supplies);
 	if (ret)
 		dev_err(&dsi->dev, "regulator bulk disable failed: %d\n", ret);
 
@@ -520,7 +536,8 @@ static int nt36672e_panel_probe(struct mipi_dsi_device *dsi)
 {
 	struct device *dev = &dsi->dev;
 	struct nt36672e_panel *ctx;
-	int i, ret = 0;
+	bool avdd, avee;
+	int ret = 0;
 
 	ctx = devm_drm_panel_alloc(dev, struct nt36672e_panel, panel,
 				   &nt36672e_drm_funcs,
@@ -534,15 +551,27 @@ static int nt36672e_panel_probe(struct mipi_dsi_device *dsi)
 		return -ENODEV;
 	}
 
-	for (i = 0; i < ARRAY_SIZE(ctx->supplies); i++) {
-		ctx->supplies[i].supply = regulator_names[i];
-		ctx->supplies[i].init_load_uA = regulator_enable_loads[i];
-	}
-
-	ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(ctx->supplies),
-			ctx->supplies);
+	ret = devm_regulator_bulk_get_const(dev, ARRAY_SIZE(nt36672e_supplies),
+					    nt36672e_supplies, &ctx->supplies);
 	if (ret < 0)
-		return ret;
+		return dev_err_probe(dev, ret, "Failed to get regulators\n");
+
+	/* The bias supplies are either both described or generated on the module */
+	avdd = of_property_present(dev->of_node, "avdd-supply");
+	avee = of_property_present(dev->of_node, "avee-supply");
+	if (avdd != avee)
+		return dev_err_probe(dev, -EINVAL,
+				     "avdd and avee supplies must be described together\n");
+
+	if (avdd) {
+		ret = devm_regulator_bulk_get_const(dev,
+						    ARRAY_SIZE(nt36672e_bias_supplies),
+						    nt36672e_bias_supplies,
+						    &ctx->bias_supplies);
+		if (ret < 0)
+			return dev_err_probe(dev, ret,
+					     "Failed to get bias regulators\n");
+	}
 
 	ctx->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
 	if (IS_ERR(ctx->reset_gpio))
-- 
2.51.0

[PATCH 4/8] drm/panel: novatek-nt36672e: Support the bias enable GPIO

[Vladimir Zapolskiy]

Some NT36672E panel modules generate their positive and negative bias
supplies on the module, and expose only a bias enable signal instead of
the AVDD and AVEE supply inputs, add support of such bias enable GPIO.

Signed-off-by: Vladimir Zapolskiy <vz@kernel.org>
---
 drivers/gpu/drm/panel/panel-novatek-nt36672e.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/panel/panel-novatek-nt36672e.c b/drivers/gpu/drm/panel/panel-novatek-nt36672e.c
index 80934c6bf250..0a2d54ee8069 100644
--- a/drivers/gpu/drm/panel/panel-novatek-nt36672e.c
+++ b/drivers/gpu/drm/panel/panel-novatek-nt36672e.c
@@ -37,6 +37,7 @@ struct nt36672e_panel {
 	struct drm_panel panel;
 	struct mipi_dsi_device *dsi;
 	struct gpio_desc *reset_gpio;
+	struct gpio_desc *enable_gpio;
 	struct regulator_bulk_data *supplies;
 	struct regulator_bulk_data *bias_supplies;
 	const struct panel_desc *desc;
@@ -377,6 +378,8 @@ static int nt36672e_power_on(struct nt36672e_panel *ctx)
 		}
 	}
 
+	gpiod_set_value_cansleep(ctx->enable_gpio, 1);
+
 	/*
 	 * Reset sequence of nt36672e panel requires the panel to be out of reset
 	 * for 10ms, followed by being held in reset for 10ms and then out again.
@@ -397,6 +400,7 @@ static int nt36672e_power_off(struct nt36672e_panel *ctx)
 	int ret = 0;
 
 	gpiod_set_value(ctx->reset_gpio, 0);
+	gpiod_set_value_cansleep(ctx->enable_gpio, 0);
 
 	if (ctx->bias_supplies) {
 		ret = regulator_bulk_disable(ARRAY_SIZE(nt36672e_bias_supplies),
@@ -577,6 +581,16 @@ static int nt36672e_panel_probe(struct mipi_dsi_device *dsi)
 	if (IS_ERR(ctx->reset_gpio))
 		return dev_err_probe(dev, PTR_ERR(ctx->reset_gpio), "Failed to get reset-gpios\n");
 
+	ctx->enable_gpio = devm_gpiod_get_optional(dev, "enable", GPIOD_OUT_LOW);
+	if (IS_ERR(ctx->enable_gpio))
+		return dev_err_probe(dev, PTR_ERR(ctx->enable_gpio),
+				     "Failed to get enable-gpios\n");
+
+	/* The bias is either supplied to or generated on the panel module */
+	if (ctx->enable_gpio && ctx->bias_supplies)
+		return dev_err_probe(dev, -EINVAL,
+				     "enable-gpios and bias supplies are mutually exclusive\n");
+
 	ctx->dsi = dsi;
 	mipi_dsi_set_drvdata(dsi, ctx);
 
-- 
2.51.0

[PATCH 5/8] drm/panel: novatek-nt36672e: Verify the number of D-PHY data lanes

[Vladimir Zapolskiy]

The NT36672E panel in the MIPI D-PHY mode is connected over 4 data lanes,
a mismatching device tree description results in a panel, which won't work.

Get the PHY type of the DSI link from the PHY of the DSI host, and get
the number of data lanes from the DSI host endpoint to check the match.

Signed-off-by: Vladimir Zapolskiy <vz@kernel.org>
---
 .../gpu/drm/panel/panel-novatek-nt36672e.c    | 37 +++++++++++++++++++
 1 file changed, 37 insertions(+)

diff --git a/drivers/gpu/drm/panel/panel-novatek-nt36672e.c b/drivers/gpu/drm/panel/panel-novatek-nt36672e.c
index 0a2d54ee8069..33676e334b9f 100644
--- a/drivers/gpu/drm/panel/panel-novatek-nt36672e.c
+++ b/drivers/gpu/drm/panel/panel-novatek-nt36672e.c
@@ -5,14 +5,18 @@
 #include <linux/gpio/consumer.h>
 #include <linux/module.h>
 #include <linux/of.h>
+#include <linux/of_graph.h>
 #include <linux/regulator/consumer.h>
 
 #include <drm/drm_mipi_dsi.h>
 #include <drm/drm_modes.h>
+#include <drm/drm_of.h>
 #include <drm/drm_panel.h>
 
 #include <video/mipi_display.h>
 
+#include <dt-bindings/phy/phy.h>
+
 static const struct regulator_bulk_data nt36672e_supplies[] = {
 	{ .supply = "vddi", .init_load_uA = 62000 },
 };
@@ -536,6 +540,30 @@ static const struct drm_panel_funcs nt36672e_drm_funcs = {
 	.get_modes = nt36672e_panel_get_modes,
 };
 
+/*
+ * Get the PHY type of the DSI link from the PHY of the DSI host, MIPI D-PHY
+ * is the default, if the PHY type is not specified.
+ */
+static u32 nt36672e_get_dsi_phy_type(struct device *dev)
+{
+	struct device_node *host, *phy;
+	u32 phy_type = PHY_TYPE_DPHY;
+
+	host = of_graph_get_remote_node(dev->of_node, 0, 0);
+	if (!host)
+		return phy_type;
+
+	phy = of_parse_phandle(host, "phys", 0);
+	of_node_put(host);
+	if (!phy)
+		return phy_type;
+
+	of_property_read_u32(phy, "phy-type", &phy_type);
+	of_node_put(phy);
+
+	return phy_type;
+}
+
 static int nt36672e_panel_probe(struct mipi_dsi_device *dsi)
 {
 	struct device *dev = &dsi->dev;
@@ -598,6 +626,15 @@ static int nt36672e_panel_probe(struct mipi_dsi_device *dsi)
 	dsi->format = ctx->desc->format;
 	dsi->mode_flags = ctx->desc->mode_flags;
 
+	/* A MIPI D-PHY link to the panel shall have exactly 4 data lanes */
+	if (nt36672e_get_dsi_phy_type(dev) == PHY_TYPE_DPHY) {
+		ret = drm_of_get_data_lanes_count_remote(dev->of_node, 0, -1, 1, 4);
+		if (ret > 0 && ret != 4)
+			return dev_err_probe(dev, -EINVAL,
+					     "%d D-PHY data lanes described, 4 required\n",
+					     ret);
+	}
+
 	ret = drm_panel_of_backlight(&ctx->panel);
 	if (ret)
 		return dev_err_probe(dev, ret, "Failed to get backlight\n");
-- 
2.51.0

[PATCH 6/8] drm/panel: novatek-nt36672e: Add support of the C-PHY panel module

[Vladimir Zapolskiy]

The display card for the Qualcomm SM8450 HDK board has an NT36672E panel
module with a resolution of 1080x2400, which is connected over 3 MIPI
C-PHY trios, and runs at 144Hz with Display Stream Compression.

The MIPI PHY type of the DSI link is fixed by the panel module design,
thus select the panel type by the PHY type of the DSI link, MIPI D-PHY
selects the existing panel description, MIPI C-PHY selects the new one.

The initialization sequence, the display timings and the DSC parameters
of the new supported MIPI C-PHY panel module are taken from the Qualcomm
display device tree source of the panel:

  https://git.codelinaro.org/clo/la/platform/vendor/opensource/display-devicetree
  tag DISPLAY.LA.6.0.r12-02500-WAIPIO.QSSI17.0
  display/dsi-panel-nt36672e-fhd-plus-144hz-video-cphy.dtsi

The DSC picture parameter set is sent after the display is switched on,
the display decompression is enabled by the initialization sequence.

Signed-off-by: Vladimir Zapolskiy <vz@kernel.org>
---
 drivers/gpu/drm/panel/Kconfig                 |   8 +-
 .../gpu/drm/panel/panel-novatek-nt36672e.c    | 496 +++++++++++++++++-
 2 files changed, 486 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
index 7a520b4d60fe..634d44d26a74 100644
--- a/drivers/gpu/drm/panel/Kconfig
+++ b/drivers/gpu/drm/panel/Kconfig
@@ -720,10 +720,14 @@ config DRM_PANEL_NOVATEK_NT36672E
 	depends on OF
 	depends on DRM_MIPI_DSI
 	depends on BACKLIGHT_CLASS_DEVICE
+	select DRM_DISPLAY_DSC_HELPER
+	select DRM_DISPLAY_HELPER
 	help
 	  Say Y here if you want to enable support for Novatek NT36672E DSI Video Mode
-	  LCD panel module. The panel has a resolution of 1080x2408 and uses 24 bit
-	  RGB per pixel.
+	  LCD panel modules. The supported panel modules use 24 bit RGB per pixel,
+	  and have a resolution of 1080x2408 with a 4-lane MIPI D-PHY link, or
+	  a resolution of 1080x2400 with a 3-trio MIPI C-PHY link and Display
+	  Stream Compression.
 
 config DRM_PANEL_NOVATEK_NT37700F
 	tristate "Novatek NT37700F DSI panel"
diff --git a/drivers/gpu/drm/panel/panel-novatek-nt36672e.c b/drivers/gpu/drm/panel/panel-novatek-nt36672e.c
index 33676e334b9f..42d1448ea971 100644
--- a/drivers/gpu/drm/panel/panel-novatek-nt36672e.c
+++ b/drivers/gpu/drm/panel/panel-novatek-nt36672e.c
@@ -8,6 +8,8 @@
 #include <linux/of_graph.h>
 #include <linux/regulator/consumer.h>
 
+#include <drm/display/drm_dsc.h>
+#include <drm/display/drm_dsc_helper.h>
 #include <drm/drm_mipi_dsi.h>
 #include <drm/drm_modes.h>
 #include <drm/drm_of.h>
@@ -33,6 +35,8 @@ struct panel_desc {
 	unsigned long mode_flags;
 	enum mipi_dsi_pixel_format format;
 	unsigned int lanes;
+	u32 phy_type;
+	const struct drm_dsc_config *dsc;
 	const char *panel_name;
 	void (*init_sequence)(struct mipi_dsi_multi_context *ctx);
 };
@@ -45,6 +49,7 @@ struct nt36672e_panel {
 	struct regulator_bulk_data *supplies;
 	struct regulator_bulk_data *bias_supplies;
 	const struct panel_desc *desc;
+	struct drm_dsc_config dsc;
 };
 
 #define NT36672E_DCS_SWITCH_PAGE	0xff
@@ -360,6 +365,401 @@ static void nt36672e_1080x2408_60hz_init(struct mipi_dsi_multi_context *ctx)
 	mipi_dsi_dcs_write_seq_multi(ctx, 0x55, 0x01);
 }
 
+static void nt36672e_1080x2400_144hz_cphy_init(struct mipi_dsi_multi_context *ctx)
+{
+	nt36672e_switch_page(ctx, 0x10);
+	nt36672e_enable_reload_cmds(ctx);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0xb0, 0x00);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0xc0, 0x03);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0xc1, 0x89, 0x28, 0x00, 0x08, 0x00, 0xaa, 0x02,
+				     0x0e, 0x00, 0x2b, 0x00, 0x07, 0x0d, 0xb7, 0x0c, 0xb7);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0xc2, 0x1b, 0xa0);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0xe9, 0x01);
+
+	nt36672e_switch_page(ctx, 0x20);
+	nt36672e_enable_reload_cmds(ctx);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x01, 0x66);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x06, 0x40);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x07, 0x38);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x18, 0x77);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x69, 0x91);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x95, 0xd1);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x96, 0xd1);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0xf2, 0x65);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0xf3, 0x74);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0xf4, 0x65);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0xf5, 0x74);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0xf6, 0x65);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0xf7, 0x74);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0xf8, 0x65);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0xf9, 0x74);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x89, 0x15);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x8a, 0x15);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x8d, 0x15);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x8e, 0x15);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x8f, 0x15);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x91, 0x15);
+
+	nt36672e_switch_page(ctx, 0x24);
+	nt36672e_enable_reload_cmds(ctx);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x01, 0x0f);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x03, 0x0c);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x05, 0x1d);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x08, 0x2f);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x09, 0x2e);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x0a, 0x2d);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x0b, 0x2c);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x11, 0x17);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x12, 0x13);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x13, 0x15);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x15, 0x14);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x16, 0x16);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x17, 0x18);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x1b, 0x01);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x1d, 0x1d);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x20, 0x2f);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x21, 0x2e);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x22, 0x2d);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x23, 0x2c);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x29, 0x17);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x2a, 0x13);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x2b, 0x15);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x2f, 0x14);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x30, 0x16);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x31, 0x18);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x32, 0x04);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x34, 0x10);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x35, 0x1f);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x36, 0x1f);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x4d, 0x1b);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x4e, 0x4b);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x4f, 0x4b);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x53, 0x4b);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x71, 0x30);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x79, 0x11);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x7a, 0x82);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x7b, 0x96);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x7d, 0x04);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x80, 0x04);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x81, 0x04);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x82, 0x13);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x84, 0x31);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x85, 0x00);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x86, 0x00);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x87, 0x00);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x90, 0x13);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x92, 0x31);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x93, 0x00);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x94, 0x00);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x95, 0x00);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x9c, 0xf4);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x9d, 0x01);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0xa0, 0x16);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0xa2, 0x16);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0xa3, 0x02);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0xa4, 0x04);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0xa5, 0x04);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0xc6, 0xc0);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0xc9, 0x00);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0xd9, 0x80);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0xe9, 0x02);
+
+	nt36672e_switch_page(ctx, 0x25);
+	nt36672e_enable_reload_cmds(ctx);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x18, 0x22);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x19, 0xe4);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x21, 0x40);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x66, 0xd8);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x68, 0x50);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x69, 0x10);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x6b, 0x00);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x6d, 0x0d);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x6e, 0x48);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x72, 0x41);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x73, 0x4a);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x74, 0xd0);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x77, 0x62);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x79, 0x81);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x7d, 0x40);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x7e, 0x1d);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x7f, 0x00);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x80, 0x04);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x84, 0x0d);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0xcf, 0x80);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0xd6, 0x80);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0xd7, 0x80);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0xef, 0x20);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0xf0, 0x84);
+
+	nt36672e_switch_page(ctx, 0x26);
+	nt36672e_enable_reload_cmds(ctx);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x15, 0x04);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x81, 0x16);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x83, 0x03);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x84, 0x03);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x85, 0x01);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x86, 0x03);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x87, 0x01);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x8a, 0x1a);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x8b, 0x11);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x8c, 0x24);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x8e, 0x42);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x8f, 0x11);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x90, 0x11);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x91, 0x11);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x9a, 0x81);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x9b, 0x03);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x9c, 0x00);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x9d, 0x00);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x9e, 0x00);
+
+	nt36672e_switch_page(ctx, 0x27);
+	nt36672e_enable_reload_cmds(ctx);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x01, 0x60);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x20, 0x81);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x21, 0xea);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x25, 0x82);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x26, 0x3f);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x6e, 0x00);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x6f, 0x00);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x70, 0x00);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x71, 0x00);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x72, 0x00);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x75, 0x00);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x76, 0x00);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x77, 0x00);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x7d, 0x09);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x7e, 0x5f);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x80, 0x23);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x82, 0x09);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x83, 0x5f);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x88, 0x01);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x89, 0x10);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0xa5, 0x10);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0xa6, 0x23);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0xa7, 0x01);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0xb6, 0x40);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0xe3, 0x02);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0xe4, 0xe0);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0xe5, 0x01);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0xe6, 0x33);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0xe9, 0x03);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0xea, 0x5e);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0xeb, 0x01);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0xec, 0x67);
+
+	nt36672e_switch_page(ctx, 0x2a);
+	nt36672e_enable_reload_cmds(ctx);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x00, 0x91);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x03, 0x20);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x04, 0x73);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x07, 0x64);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x0a, 0x60);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x0c, 0x06);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x0d, 0x40);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x0e, 0x02);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x0f, 0x01);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x11, 0x58);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x15, 0x0e);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x16, 0x79);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x19, 0x0d);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x1a, 0xf2);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x1b, 0x14);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x1d, 0x36);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x1e, 0x55);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x1f, 0x55);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x20, 0x55);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x28, 0x0a);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x29, 0x0b);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x2a, 0x4b);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x2b, 0x05);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x2d, 0x08);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x2f, 0x01);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x30, 0x47);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x31, 0x23);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x33, 0x25);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x34, 0xff);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x35, 0x2c);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x36, 0x75);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x37, 0xfb);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x38, 0x2e);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x39, 0x73);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x3a, 0x47);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x46, 0x40);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x47, 0x02);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x4a, 0xf0);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x4e, 0x0e);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x4f, 0x8b);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x52, 0x0e);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x53, 0x04);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x54, 0x14);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x56, 0x36);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x57, 0x80);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x58, 0x80);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x59, 0x80);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x60, 0x80);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x61, 0x0a);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x62, 0x03);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x63, 0xed);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x65, 0x05);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x66, 0x01);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x67, 0x04);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x68, 0x4d);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x6a, 0x0a);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x6b, 0xc9);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x6c, 0x1f);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x6d, 0xe3);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x6e, 0xc6);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x6f, 0x20);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x70, 0xe2);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x71, 0x04);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x7a, 0x04);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x7b, 0x40);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x7c, 0x01);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x7d, 0x01);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x7f, 0xe0);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x83, 0x0f);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x84, 0xc5);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x87, 0x0f);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x88, 0x42);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x89, 0x14);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x8b, 0x36);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x8c, 0x33);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x8d, 0x33);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x8e, 0x33);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x95, 0x80);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x96, 0xfd);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x97, 0x19);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x98, 0x4a);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x99, 0x07);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x9a, 0x0b);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x9b, 0x03);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x9c, 0x8b);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x9d, 0xff);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x9f, 0x8b);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0xa0, 0xff);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0xa2, 0x4e);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0xa3, 0x01);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0xa4, 0xf8);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0xa5, 0x52);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0xa6, 0xfd);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0xa7, 0x4b);
+
+	nt36672e_switch_page(ctx, 0x2c);
+	nt36672e_enable_reload_cmds(ctx);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x00, 0x02);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x01, 0x02);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x02, 0x02);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x03, 0x16);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x04, 0x16);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x05, 0x16);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x0d, 0x1f);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x0e, 0x1f);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x16, 0x1b);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x17, 0x4b);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x18, 0x4b);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x19, 0x4b);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x2a, 0x03);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x4d, 0x16);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x4e, 0x03);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x53, 0x02);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x54, 0x02);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x55, 0x02);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x56, 0x0b);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x58, 0x0b);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x59, 0x0b);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x61, 0x19);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x62, 0x19);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x6a, 0x10);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x6b, 0x2a);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x6c, 0x2a);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x6d, 0x2a);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x7e, 0x03);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x9d, 0x0b);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x9e, 0x04);
+
+	nt36672e_switch_page(ctx, 0x20);
+	nt36672e_enable_reload_cmds(ctx);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0xb0, 0x00, 0xe2, 0x00, 0xe9, 0x00, 0xf6, 0x01,
+				     0x01, 0x01, 0x0c, 0x01, 0x15, 0x01, 0x20, 0x01, 0x28);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0xb1, 0x01, 0x33, 0x01, 0x51, 0x01, 0x6e, 0x01,
+				     0x9a, 0x01, 0xc0, 0x01, 0xfd, 0x02, 0x34, 0x02, 0x35);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0xb2, 0x02, 0x6b, 0x02, 0xa9, 0x02, 0xd1, 0x03,
+				     0x04, 0x03, 0x25, 0x03, 0x51, 0x03, 0x5f, 0x03, 0x6d);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0xb3, 0x03, 0x7d, 0x03, 0x90, 0x03, 0xa7, 0x03,
+				     0xbb, 0x03, 0xd4, 0x03, 0xd8, 0x00, 0x00);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0xb4, 0x00, 0xaa, 0x00, 0xb3, 0x00, 0xc4, 0x00,
+				     0xd4, 0x00, 0xe2, 0x00, 0xf0, 0x00, 0xfc, 0x01, 0x08);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0xb5, 0x01, 0x12, 0x01, 0x39, 0x01, 0x58, 0x01,
+				     0x8c, 0x01, 0xb5, 0x01, 0xf7, 0x02, 0x30, 0x02, 0x31);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0xb6, 0x02, 0x68, 0x02, 0xa6, 0x02, 0xce, 0x03,
+				     0x01, 0x03, 0x23, 0x03, 0x4e, 0x03, 0x5c, 0x03, 0x6a);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0xb7, 0x03, 0x7b, 0x03, 0x8e, 0x03, 0xa5, 0x03,
+				     0xbb, 0x03, 0xd4, 0x03, 0xd8, 0x00, 0x00);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0xb8, 0x00, 0x00, 0x00, 0x20, 0x00, 0x47, 0x00,
+				     0x65, 0x00, 0x85, 0x00, 0x99, 0x00, 0xad, 0x00, 0xc0);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0xb9, 0x00, 0xd2, 0x01, 0x06, 0x01, 0x30, 0x01,
+				     0x70, 0x01, 0x9f, 0x01, 0xe8, 0x02, 0x25, 0x02, 0x26);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0xba, 0x02, 0x5f, 0x02, 0x9f, 0x02, 0xc7, 0x02,
+				     0xfd, 0x03, 0x20, 0x03, 0x52, 0x03, 0x63, 0x03, 0x67);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0xbb, 0x03, 0x78, 0x03, 0x8b, 0x03, 0xa3, 0x03,
+				     0xb9, 0x03, 0xd4, 0x03, 0xd8, 0x00, 0x00);
+
+	nt36672e_switch_page(ctx, 0x21);
+	nt36672e_enable_reload_cmds(ctx);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0xb0, 0x00, 0xe2, 0x00, 0xe9, 0x00, 0xf6, 0x01,
+				     0x01, 0x01, 0x0c, 0x01, 0x15, 0x01, 0x20, 0x01, 0x28);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0xb1, 0x01, 0x33, 0x01, 0x51, 0x01, 0x6e, 0x01,
+				     0x9a, 0x01, 0xc0, 0x01, 0xfd, 0x02, 0x34, 0x02, 0x35);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0xb2, 0x02, 0x6b, 0x02, 0xa9, 0x02, 0xd1, 0x03,
+				     0x04, 0x03, 0x25, 0x03, 0x51, 0x03, 0x5f, 0x03, 0x6d);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0xb3, 0x03, 0x7d, 0x03, 0x90, 0x03, 0xa7, 0x03,
+				     0xbb, 0x03, 0xd4, 0x03, 0xd8, 0x00, 0x00);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0xb4, 0x00, 0xaa, 0x00, 0xb3, 0x00, 0xc4, 0x00,
+				     0xd4, 0x00, 0xe2, 0x00, 0xf0, 0x00, 0xfc, 0x01, 0x08);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0xb5, 0x01, 0x12, 0x01, 0x39, 0x01, 0x58, 0x01,
+				     0x8c, 0x01, 0xb5, 0x01, 0xf7, 0x02, 0x30, 0x02, 0x31);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0xb6, 0x02, 0x68, 0x02, 0xa6, 0x02, 0xce, 0x03,
+				     0x01, 0x03, 0x23, 0x03, 0x4e, 0x03, 0x5c, 0x03, 0x6a);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0xb7, 0x03, 0x7b, 0x03, 0x8e, 0x03, 0xa5, 0x03,
+				     0xbb, 0x03, 0xd4, 0x03, 0xd8, 0x00, 0x00);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0xb8, 0x00, 0x00, 0x00, 0x20, 0x00, 0x47, 0x00,
+				     0x65, 0x00, 0x85, 0x00, 0x99, 0x00, 0xad, 0x00, 0xc0);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0xb9, 0x00, 0xd2, 0x01, 0x06, 0x01, 0x30, 0x01,
+				     0x70, 0x01, 0x9f, 0x01, 0xe8, 0x02, 0x25, 0x02, 0x26);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0xba, 0x02, 0x5f, 0x02, 0x9f, 0x02, 0xc7, 0x02,
+				     0xfd, 0x03, 0x20, 0x03, 0x52, 0x03, 0x63, 0x03, 0x67);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0xbb, 0x03, 0x78, 0x03, 0x8b, 0x03, 0xa3, 0x03,
+				     0xb9, 0x03, 0xd4, 0x03, 0xd8, 0x00, 0x00);
+
+	nt36672e_switch_page(ctx, 0xe0);
+	nt36672e_enable_reload_cmds(ctx);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x35, 0x82);
+
+	nt36672e_switch_page(ctx, 0xf0);
+	nt36672e_enable_reload_cmds(ctx);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x5a, 0x00);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0xd2, 0x52);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x9f, 0x12);
+
+	nt36672e_switch_page(ctx, 0xd0);
+	nt36672e_enable_reload_cmds(ctx);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x53, 0x22);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x54, 0x02);
+
+	nt36672e_switch_page(ctx, 0xc0);
+	nt36672e_enable_reload_cmds(ctx);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x9c, 0x11);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x9d, 0x11);
+
+	nt36672e_switch_page(ctx, 0x10);
+	nt36672e_enable_reload_cmds(ctx);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x35, 0x01);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x51, 0xff);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x53, 0x0c);
+	mipi_dsi_dcs_write_seq_multi(ctx, 0x55, 0x00);
+}
+
 static int nt36672e_power_on(struct nt36672e_panel *ctx)
 {
 	struct mipi_dsi_device *dsi = ctx->dsi;
@@ -437,6 +837,14 @@ static int nt36672e_on(struct nt36672e_panel *nt36672e)
 
 	mipi_dsi_msleep(&ctx, 100);
 
+	/* Display decompression is enabled by the initialization sequence */
+	if (desc->dsc) {
+		struct drm_dsc_picture_parameter_set pps;
+
+		drm_dsc_pps_payload_pack(&pps, &nt36672e->dsc);
+		mipi_dsi_picture_parameter_set_multi(&ctx, &pps);
+	}
+
 	return ctx.accum_err;
 }
 
@@ -511,10 +919,59 @@ static const struct panel_desc nt36672e_panel_desc = {
 	.mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS,
 	.format = MIPI_DSI_FMT_RGB888,
 	.lanes = 4,
+	.phy_type = PHY_TYPE_DPHY,
 	.panel_name = "nt36672e fhd plus panel",
 	.init_sequence = nt36672e_1080x2408_60hz_init,
 };
 
+static const struct drm_display_mode nt36672e_1080x2400_144hz = {
+	.name = "1080x2400",
+	.clock = (1080 + 76 + 20 + 80) * (2400 + 54 + 10 + 10) * 144 / 1000,
+	.hdisplay = 1080,
+	.hsync_start = 1080 + 76,
+	.hsync_end = 1080 + 76 + 20,
+	.htotal = 1080 + 76 + 20 + 80,
+	.vdisplay = 2400,
+	.vsync_start = 2400 + 54,
+	.vsync_end = 2400 + 54 + 10,
+	.vtotal = 2400 + 54 + 10 + 10,
+	.flags = 0,
+};
+
+static const struct drm_dsc_config nt36672e_1080x2400_dsc = {
+	.dsc_version_major = 1,
+	.dsc_version_minor = 1,
+	.slice_height = 8,
+	.slice_width = 540,
+	.slice_count = 1080 / 540,
+	.bits_per_component = 8,
+	.bits_per_pixel = 8 << 4,	/* 4 fractional bits */
+	.block_pred_enable = true,
+};
+
+static const struct panel_desc nt36672e_cphy_panel_desc = {
+	.display_mode = &nt36672e_1080x2400_144hz,
+	.width_mm = 70,
+	.height_mm = 154,
+	.mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
+		      MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS,
+	.format = MIPI_DSI_FMT_RGB888,
+	.lanes = 3,
+	.phy_type = PHY_TYPE_CPHY,
+	.dsc = &nt36672e_1080x2400_dsc,
+	.panel_name = "nt36672e fhd plus c-phy panel",
+	.init_sequence = nt36672e_1080x2400_144hz_cphy_init,
+};
+
+/*
+ * The panel modules share the compatible, the module is selected by the PHY
+ * type of the DSI link, which is fixed by the panel module.
+ */
+static const struct panel_desc * const nt36672e_panel_descs[] = {
+	&nt36672e_panel_desc,
+	&nt36672e_cphy_panel_desc,
+};
+
 static int nt36672e_panel_get_modes(struct drm_panel *panel, struct drm_connector *connector)
 {
 	struct nt36672e_panel *ctx = to_nt36672e_panel(panel);
@@ -569,7 +1026,8 @@ static int nt36672e_panel_probe(struct mipi_dsi_device *dsi)
 	struct device *dev = &dsi->dev;
 	struct nt36672e_panel *ctx;
 	bool avdd, avee;
-	int ret = 0;
+	u32 phy_type;
+	int i, ret = 0;
 
 	ctx = devm_drm_panel_alloc(dev, struct nt36672e_panel, panel,
 				   &nt36672e_drm_funcs,
@@ -577,12 +1035,18 @@ static int nt36672e_panel_probe(struct mipi_dsi_device *dsi)
 	if (IS_ERR(ctx))
 		return PTR_ERR(ctx);
 
-	ctx->desc = of_device_get_match_data(dev);
-	if (!ctx->desc) {
-		dev_err(dev, "missing device configuration\n");
-		return -ENODEV;
+	phy_type = nt36672e_get_dsi_phy_type(dev);
+	for (i = 0; i < ARRAY_SIZE(nt36672e_panel_descs); i++) {
+		if (nt36672e_panel_descs[i]->phy_type == phy_type) {
+			ctx->desc = nt36672e_panel_descs[i];
+			break;
+		}
 	}
 
+	if (!ctx->desc)
+		return dev_err_probe(dev, -EINVAL,
+				     "Unsupported DSI PHY type %u\n", phy_type);
+
 	ret = devm_regulator_bulk_get_const(dev, ARRAY_SIZE(nt36672e_supplies),
 					    nt36672e_supplies, &ctx->supplies);
 	if (ret < 0)
@@ -626,13 +1090,16 @@ static int nt36672e_panel_probe(struct mipi_dsi_device *dsi)
 	dsi->format = ctx->desc->format;
 	dsi->mode_flags = ctx->desc->mode_flags;
 
-	/* A MIPI D-PHY link to the panel shall have exactly 4 data lanes */
-	if (nt36672e_get_dsi_phy_type(dev) == PHY_TYPE_DPHY) {
-		ret = drm_of_get_data_lanes_count_remote(dev->of_node, 0, -1, 1, 4);
-		if (ret > 0 && ret != 4)
-			return dev_err_probe(dev, -EINVAL,
-					     "%d D-PHY data lanes described, 4 required\n",
-					     ret);
+	/* The DSI link shall have the number of data lanes of the panel */
+	ret = drm_of_get_data_lanes_count_remote(dev->of_node, 0, -1, 1, 4);
+	if (ret > 0 && ret != dsi->lanes)
+		return dev_err_probe(dev, -EINVAL,
+				     "%d DSI data lanes described, %u required\n",
+				     ret, dsi->lanes);
+
+	if (ctx->desc->dsc) {
+		ctx->dsc = *ctx->desc->dsc;
+		dsi->dsc = &ctx->dsc;
 	}
 
 	ret = drm_panel_of_backlight(&ctx->panel);
@@ -665,10 +1132,7 @@ static void nt36672e_panel_remove(struct mipi_dsi_device *dsi)
 }
 
 static const struct of_device_id nt36672e_of_match[] = {
-	{
-		.compatible = "novatek,nt36672e",
-		.data = &nt36672e_panel_desc,
-	},
+	{ .compatible = "novatek,nt36672e" },
 	{ }
 };
 MODULE_DEVICE_TABLE(of, nt36672e_of_match);
-- 
2.51.0

[PATCH 7/8] arm64: dts: qcom: sm8450-hdk: Add display card overlay

[Vladimir Zapolskiy]

The SM8450 HDK board can be connected to an external display card, which
carries a 1080x2400 LCD panel module powered by the Novatek NT36672E
display driver IC with an integrated touchscreen controller.

The panel is connected to DSI0 over a 3-trio MIPI C-PHY link, power is
supplied by VREG_L12C_1P8, the bias supplies are on the panel module,
and they are enabled by signal PM8350 GPIO8 (LCD_BIAS_EN).

The backlight is controlled by the PM8350 GPIO9 (LCD_WLED_EN) signal and
the PM8350C LPG PWM on PM8350C GPIO8 (LCD_PWM).

As documented in the panel binding, the reset GPIO is described as
active high, although the panel reset signal is active low.

The DSI0 output is shared with the on-board Lontium LT9611UXC HDMI
bridge, thus disable the bridge and its power supplies in the overlay.

The touchscreen controller is not described, since there is no binding
or driver support for it yet.

Signed-off-by: Vladimir Zapolskiy <vz@kernel.org>
---
 arch/arm64/boot/dts/qcom/Makefile             |   4 +
 .../dts/qcom/sm8450-hdk-display-card.dtso     | 144 ++++++++++++++++++
 2 files changed, 148 insertions(+)
 create mode 100644 arch/arm64/boot/dts/qcom/sm8450-hdk-display-card.dtso

diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index 88230c4e00ea..93abf21132c1 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -422,6 +422,10 @@ dtb-$(CONFIG_ARCH_QCOM)	+= sm8350-microsoft-surface-duo2.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= sm8350-mtp.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= sm8350-sony-xperia-sagami-pdx214.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= sm8350-sony-xperia-sagami-pdx215.dtb
+
+sm8450-hdk-display-card-dtbs	:= sm8450-hdk.dtb sm8450-hdk-display-card.dtbo
+
+dtb-$(CONFIG_ARCH_QCOM)	+= sm8450-hdk-display-card.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= sm8450-hdk.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= sm8450-qrd.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= sm8450-samsung-r0q.dtb
diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk-display-card.dtso b/arch/arm64/boot/dts/qcom/sm8450-hdk-display-card.dtso
new file mode 100644
index 000000000000..0e7b48b8357a
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sm8450-hdk-display-card.dtso
@@ -0,0 +1,144 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) Linaro Limited
+ * Copyright (c) Vladimir Zapolskiy <vz@kernel.org>
+ */
+
+/*
+ * Display Card kit overlay
+ *
+ * S5702 switch 7 should be turned OFF to route DSI0 to the display panel
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
+
+/dts-v1/;
+/plugin/;
+
+&{/} {
+	lcd_backlight: backlight {
+		compatible = "pwm-backlight";
+		pwms = <&pm8350c_pwm 3 65535>;
+		enable-gpios = <&pm8350_gpios 9 GPIO_ACTIVE_HIGH>;
+
+		pinctrl-0 = <&lcd_wled_en>;
+		pinctrl-names = "default";
+	};
+};
+
+/* Disable HDMI bridge related nodes (mutually exclusive with the display card) */
+
+&i2c9 {
+	status = "disabled";
+};
+
+&lt9611_1v2 {
+	status = "disabled";
+};
+
+&lt9611_3v3 {
+	status = "disabled";
+};
+
+&lt9611_codec {
+	status = "disabled";
+};
+
+&mdss_dsi0 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	panel@0 {
+		compatible = "novatek,nt36672e";
+		reg = <0>;
+
+		enable-gpios = <&pm8350_gpios 8 GPIO_ACTIVE_HIGH>;
+		reset-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
+
+		vddi-supply = <&vreg_l12c_1p8>;
+
+		backlight = <&lcd_backlight>;
+
+		pinctrl-0 = <&disp0_reset_n_active>, <&mdp_vsync>, <&lcd_bias_en>;
+		pinctrl-1 = <&disp0_reset_n_suspend>, <&mdp_vsync>, <&lcd_bias_en>;
+		pinctrl-names = "default", "sleep";
+
+		port {
+			panel0_in: endpoint {
+				remote-endpoint = <&mdss_dsi0_out>;
+			};
+		};
+	};
+};
+
+&mdss_dsi0_out {
+	remote-endpoint = <&panel0_in>;
+	data-lanes = <0 1 2>;
+};
+
+&mdss_dsi0_phy {
+	phy-type = <PHY_TYPE_CPHY>;
+};
+
+&pm8350_gpios {
+	lcd_bias_en: lcd-bias-en-state {
+		pins = "gpio8";
+		function = "normal";
+		output-low;
+		bias-disable;
+		qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>;
+		power-source = <0>;
+	};
+
+	lcd_wled_en: lcd-wled-en-state {
+		pins = "gpio9";
+		function = "normal";
+		output-low;
+		bias-disable;
+		qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>;
+		power-source = <0>;
+	};
+};
+
+&pm8350c_gpios {
+	lcd_pwm: lcd-pwm-state {
+		pins = "gpio8";
+		function = "func1";
+		output-low;
+		bias-disable;
+		qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>;
+		power-source = <0>;
+	};
+};
+
+&pm8350c_pwm {
+	pinctrl-0 = <&lcd_pwm>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&tlmm {
+	disp0_reset_n_active: disp0-reset-n-active-state {
+		pins = "gpio0";
+		function = "gpio";
+		drive-strength = <8>;
+		bias-disable;
+	};
+
+	disp0_reset_n_suspend: disp0-reset-n-suspend-state {
+		pins = "gpio0";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-pull-down;
+	};
+
+	mdp_vsync: mdp-vsync-state {
+		pins = "gpio86";
+		function = "mdp_vsync";
+		drive-strength = <2>;
+		bias-pull-down;
+	};
+};
-- 
2.51.0

Re: [PATCH 7/8] arm64: dts: qcom: sm8450-hdk: Add display card overlay

[Konrad Dybcio]

On 10/28/26 10:51 AM, Vladimir Zapolskiy wrote:
> The SM8450 HDK board can be connected to an external display card, which
> carries a 1080x2400 LCD panel module powered by the Novatek NT36672E
> display driver IC with an integrated touchscreen controller.
> 
> The panel is connected to DSI0 over a 3-trio MIPI C-PHY link, power is

Either "a trio" or "3 lanes", 3 trios would be *a lot* of bandwidth

Otherwise I think this looks good

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad

[PATCH 8/8] arm64: dts: qcom: qcm6490-idp: Describe the panel bias enable GPIO

[Vladimir Zapolskiy]

The positive and negative bias supplies of the NT36672E panel on the
QCM6490 IDP board are switched on by the PM7250B GPIO2 bias enable
signal, which is described as a single fixed regulator supplying both
AVDD and AVEE bias supplies of the panel. The fixed regulator does not
describe the hardware, it can not supply a positive and a negative
voltage at the same time, and apparently bias supplies are generated
right on the display panel module.

Since the panel binding supports the bias enable GPIO, describe the
signal as such, and remove the oddly described and used fixed regulator.

Signed-off-by: Vladimir Zapolskiy <vz@kernel.org>
---
 arch/arm64/boot/dts/qcom/qcm6490-idp.dts | 17 ++++-------------
 1 file changed, 4 insertions(+), 13 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts
index af7821e02fdb..98bbe662bd3b 100644
--- a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts
+++ b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts
@@ -51,17 +51,6 @@ chosen {
 		stdout-path = "serial0:115200n8";
 	};
 
-	lcd_disp_bias: regulator-lcd-disp-bias {
-		compatible = "regulator-fixed";
-		regulator-name = "lcd_disp_bias";
-		regulator-min-microvolt = <5500000>;
-		regulator-max-microvolt = <5500000>;
-		gpio = <&pm7250b_gpios 2 GPIO_ACTIVE_HIGH>;
-		enable-active-high;
-		pinctrl-0 = <&lcd_disp_bias_en>;
-		pinctrl-names = "default";
-	};
-
 	gpio-keys {
 		compatible = "gpio-keys";
 
@@ -653,14 +642,16 @@ panel@0 {
 		compatible = "novatek,nt36672e";
 		reg = <0>;
 
+		enable-gpios = <&pm7250b_gpios 2 GPIO_ACTIVE_HIGH>;
 		reset-gpios = <&tlmm 44 GPIO_ACTIVE_HIGH>;
 
 		vddi-supply = <&vreg_l8c_1p62>;
-		avdd-supply = <&lcd_disp_bias>;
-		avee-supply = <&lcd_disp_bias>;
 
 		backlight = <&pm8350c_pwm_backlight>;
 
+		pinctrl-0 = <&lcd_disp_bias_en>;
+		pinctrl-names = "default";
+
 		port {
 			panel0_in: endpoint {
 				remote-endpoint = <&mdss_dsi0_out>;
-- 
2.51.0

Re: [PATCH 8/8] arm64: dts: qcom: qcm6490-idp: Describe the panel bias enable GPIO

[Konrad Dybcio]

On 10/28/26 10:51 AM, Vladimir Zapolskiy wrote:
> The positive and negative bias supplies of the NT36672E panel on the
> QCM6490 IDP board are switched on by the PM7250B GPIO2 bias enable
> signal, which is described as a single fixed regulator supplying both
> AVDD and AVEE bias supplies of the panel. The fixed regulator does not
> describe the hardware, it can not supply a positive and a negative
> voltage at the same time, and apparently bias supplies are generated
> right on the display panel module.
> 
> Since the panel binding supports the bias enable GPIO, describe the
> signal as such, and remove the oddly described and used fixed regulator.
> 
> Signed-off-by: Vladimir Zapolskiy <vz@kernel.org>
> ---

Acked-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad