[PATCH 0/3] spmi: Add SmartDV SPMI controller driver and bindings

[PATCH 0/3] spmi: Add SmartDV SPMI controller driver and bindings

[vamshi gajjela]

From: Vamshi Gajjela <vamshigajjela@google.com>

This series adds Device Tree bindings and a controller driver for the
SmartDV IP Solutions MIPI System Power Management Interface (SPMI) master
controller ("smartdv,spmi").

This IP is integrated in Google Tensor SoCs starting with the G5
generation (codename: laguna, canonically written as "lga",
"google,lga-spmi") to communicate with on-board Power Management ICs
(PMICs).

The controller supports MIPI SPMI v1.0 and v2.0 non-data bus commands
(RESET, SLEEP, SHUTDOWN, WAKEUP), register read/write, extended register
read/write, and extended register read/write long transfers up to 16 bytes.

Patch 1/3 adds the "smartdv" vendor prefix to vendor-prefixes.yaml.
Patch 2/3 documents the Device Tree bindings for the SmartDV SPMI
controller ("smartdv,spmi" and "google,lga-spmi").
Patch 3/3 adds the spmi-smartdv controller driver.

Vamshi Gajjela (3):
  dt-bindings: vendor-prefixes: Add smartdv
  dt-bindings: spmi: Add SmartDV SPMI controller
  spmi: Add SmartDV SPMI controller driver

 .../bindings/spmi/smartdv,spmi.yaml           | 126 +++++
 .../devicetree/bindings/vendor-prefixes.yaml  |   2 +
 MAINTAINERS                                   |   7 +
 drivers/spmi/Kconfig                          |  10 +
 drivers/spmi/Makefile                         |   1 +
 drivers/spmi/spmi-smartdv.c                   | 525 ++++++++++++++++++
 6 files changed, 671 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/spmi/smartdv,spmi.yaml
 create mode 100644 drivers/spmi/spmi-smartdv.c

-- 
2.56.0.317.g454f8302e1-goog

[PATCH 1/3] dt-bindings: vendor-prefixes: Add smartdv

[vamshi gajjela]

From: Vamshi Gajjela <vamshigajjela@google.com>

Add the "smartdv" vendor prefix for SmartDV IP Solutions Private
Limited.

Signed-off-by: Vamshi Gajjela <vamshigajjela@google.com>
---
 Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index ba2002969373..f15d81da1e3d 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -1569,6 +1569,8 @@ patternProperties:
     description: SKOV A/S
   "^skyworks,.*":
     description: Skyworks Solutions, Inc.
+  "^smartdv,.*":
+    description: SmartDV IP Solutions Private Limited
   "^smartfiber,.*":
     description: ShenZhen Smartfiber Technology Co, Ltd.
   "^smartlabs,.*":
-- 
2.56.0.317.g454f8302e1-goog

[PATCH 2/3] dt-bindings: spmi: Add SmartDV SPMI controller

[vamshi gajjela]

From: Vamshi Gajjela <vamshigajjela@google.com>

Document the device tree bindings for the SmartDV IP Solutions MIPI SPMI
master controller ("smartdv,spmi").

This controller IP is integrated in Google Tensor SoCs starting with the
G5 generation (codename: laguna, canonically written as "lga"), so add
"google,lga-spmi" with a fallback to "smartdv,spmi".

Signed-off-by: Vamshi Gajjela <vamshigajjela@google.com>
---
 .../bindings/spmi/smartdv,spmi.yaml           | 126 ++++++++++++++++++
 MAINTAINERS                                   |   6 +
 2 files changed, 132 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/spmi/smartdv,spmi.yaml

diff --git a/Documentation/devicetree/bindings/spmi/smartdv,spmi.yaml b/Documentation/devicetree/bindings/spmi/smartdv,spmi.yaml
new file mode 100644
index 000000000000..e0512e60d932
--- /dev/null
+++ b/Documentation/devicetree/bindings/spmi/smartdv,spmi.yaml
@@ -0,0 +1,126 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/spmi/smartdv,spmi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: SmartDV IP Solutions SPMI Controller
+
+maintainers:
+  - Vamshi Gajjela <vamshigajjela@google.com>
+
+description:
+  SmartDV IP Solutions MIPI System Power Management Interface (SPMI) master
+  controller supporting MIPI SPMI Specification versions 1.0 and 2.0.
+
+allOf:
+  - $ref: spmi.yaml#
+
+properties:
+  compatible:
+    oneOf:
+      - items:
+          - const: google,lga-spmi
+          - const: smartdv,spmi
+      - const: smartdv,spmi
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    description:
+      Core clock to the controller from which SPMI SCL is derived. Optional if
+      the controller uses a free-running clock and clock-frequency is specified.
+    maxItems: 1
+
+  resets:
+    maxItems: 1
+
+  clock-frequency:
+    description:
+      Input core clock frequency in Hz when the controller uses a free-running
+      clock not described in clocks.
+
+  smartdv,master-arb-enable:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    enum: [0, 1]
+    default: 0
+    description:
+      Enable master bus arbitration phase (0 = disable, 1 = enable).
+
+  smartdv,master-id:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    minimum: 0
+    maximum: 3
+    default: 0
+    description:
+      Master ID for the controller on the SPMI bus.
+
+  smartdv,spmi-version:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    enum: [0, 1]
+    default: 0
+    description:
+      MIPI SPMI specification version used for transfers (0 for MIPI SPMI v1.0,
+      1 for MIPI SPMI v2.0).
+
+  smartdv,arb-retry-limit:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    minimum: 0
+    maximum: 255
+    default: 32
+    description:
+      Maximum number of times the master retries a command when losing bus
+      arbitration.
+
+  smartdv,prescaler:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    minimum: 0
+    maximum: 255
+    default: 0
+    description:
+      Clock divider value to generate SPMI SCL from the input core clock. Writing
+      1 divides the system clock by 2; more generally, a non-zero value n
+      divides the system clock by 2 * n.
+
+  smartdv,read-latency:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    minimum: 0
+    maximum: 255
+    default: 32
+    description:
+      Number of SPMI SCL clock cycles to pause during bus turnaround on read
+      commands to allow the target device to fetch data.
+
+  smartdv,arb-scl-delay:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    minimum: 0
+    maximum: 3
+    default: 0
+    description:
+      Delay between arbitration and Sequence Start Condition (SSC) when the
+      controller is the Bus Owner Master (BOM).
+
+required:
+  - compatible
+  - reg
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/spmi/spmi.h>
+
+    spmi@14853000 {
+        compatible = "google,lga-spmi", "smartdv,spmi";
+        reg = <0x14853000 0x100>;
+        #address-cells = <2>;
+        #size-cells = <0>;
+        clock-frequency = <19200000>;
+        smartdv,master-arb-enable = <1>;
+        smartdv,spmi-version = <1>;
+
+        pmic@f {
+            reg = <0xf SPMI_USID>;
+        };
+    };
diff --git a/MAINTAINERS b/MAINTAINERS
index eaeb60c1e1c2..f44c597c2075 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -25243,6 +25243,12 @@ T:	git https://github.com/cschaufler/smack-next.git
 F:	Documentation/admin-guide/LSM/Smack.rst
 F:	security/smack/
 
+SMARTDV SPMI CONTROLLER DRIVER
+M:	Vamshi Gajjela <vamshigajjela@google.com>
+L:	linux-kernel@vger.kernel.org
+S:	Maintained
+F:	Documentation/devicetree/bindings/spmi/smartdv,spmi.yaml
+
 SMBDIRECT (RDMA Stream Transport with Read/Write-Offload, MS-SMBD)
 M:	Steve French <smfrench@gmail.com>
 M:	Steve French <sfrench@samba.org>
-- 
2.56.0.317.g454f8302e1-goog

[PATCH 3/3] spmi: Add SmartDV SPMI controller driver

[vamshi gajjela]

From: Vamshi Gajjela <vamshigajjela@google.com>

Add support for the SmartDV IP Solutions MIPI SPMI master controller
("smartdv,spmi"). The controller supports standard MIPI SPMI v1.0 and
v2.0 bus commands (RESET, SLEEP, SHUTDOWN, WAKEUP), register read/write,
extended register read/write, and extended register read/write long
transfers.

Signed-off-by: Vamshi Gajjela <vamshigajjela@google.com>
---
 MAINTAINERS                 |   1 +
 drivers/spmi/Kconfig        |  10 +
 drivers/spmi/Makefile       |   1 +
 drivers/spmi/spmi-smartdv.c | 525 ++++++++++++++++++++++++++++++++++++
 4 files changed, 537 insertions(+)
 create mode 100644 drivers/spmi/spmi-smartdv.c

diff --git a/MAINTAINERS b/MAINTAINERS
index f44c597c2075..fc0d364ad22b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -25248,6 +25248,7 @@ M:	Vamshi Gajjela <vamshigajjela@google.com>
 L:	linux-kernel@vger.kernel.org
 S:	Maintained
 F:	Documentation/devicetree/bindings/spmi/smartdv,spmi.yaml
+F:	drivers/spmi/spmi-smartdv.c
 
 SMBDIRECT (RDMA Stream Transport with Read/Write-Offload, MS-SMBD)
 M:	Steve French <smfrench@gmail.com>
diff --git a/drivers/spmi/Kconfig b/drivers/spmi/Kconfig
index a80cf4047b86..13bd85b0e23e 100644
--- a/drivers/spmi/Kconfig
+++ b/drivers/spmi/Kconfig
@@ -54,4 +54,14 @@ config SPMI_MTK_PMIF
 	  This is required for communicating with Mediatek PMICs and
 	  other devices that have the SPMI interface.
 
+config SPMI_SMARTDV
+	tristate "SmartDV IP Solutions SPMI Controller"
+	depends on HAS_IOMEM
+	help
+	  If you say yes to this option, support will be included for the
+	  SmartDV IP Solutions MIPI SPMI master controller.
+
+	  To compile this driver as a module, choose M here: the module
+	  will be called spmi-smartdv.
+
 endif
diff --git a/drivers/spmi/Makefile b/drivers/spmi/Makefile
index 38ac635645ba..34f6d6487604 100644
--- a/drivers/spmi/Makefile
+++ b/drivers/spmi/Makefile
@@ -8,3 +8,4 @@ obj-$(CONFIG_SPMI_APPLE)	+= spmi-apple-controller.o
 obj-$(CONFIG_SPMI_HISI3670)	+= hisi-spmi-controller.o
 obj-$(CONFIG_SPMI_MSM_PMIC_ARB)	+= spmi-pmic-arb.o
 obj-$(CONFIG_SPMI_MTK_PMIF)	+= spmi-mtk-pmif.o
+obj-$(CONFIG_SPMI_SMARTDV)	+= spmi-smartdv.o
diff --git a/drivers/spmi/spmi-smartdv.c b/drivers/spmi/spmi-smartdv.c
new file mode 100644
index 000000000000..6f6563df087d
--- /dev/null
+++ b/drivers/spmi/spmi-smartdv.c
@@ -0,0 +1,525 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * SmartDV IP Solutions SPMI controller driver
+ *
+ * Copyright 2026 Google LLC
+ * Author: Vamshi Gajjela <vamshigajjela@google.com>
+ */
+
+#include <linux/bitfield.h>
+#include <linux/bits.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/kernel.h>
+#include <linux/minmax.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/property.h>
+#include <linux/reset.h>
+#include <linux/spinlock.h>
+#include <linux/spmi.h>
+#include <linux/units.h>
+
+/* SPMI controller register address offsets */
+#define CONTROL			0x0
+#define IRQ_STATUS		0x8
+#define REQ_COMMAND		0x10
+#define REQ_DATA0		0x14
+#define REQ_DATA1		0x18
+#define REQ_DATA2		0x1c
+#define REQ_DATA3		0x20
+#define REQ_RD_STATUS		0x24
+#define RD_ERR_INDEX		0x28
+
+/* SPMI controller CONTROL register bit masks */
+#define SPMI_CONTROL_MASTER_EN			BIT(0)
+#define SPMI_CONTROL_ARB_ENABLE_MASK		BIT(1)
+#define SPMI_CONTROL_MID_MASK			GENMASK(3, 2)
+#define SPMI_CONTROL_VERSION_MASK		GENMASK(5, 4)
+#define SPMI_CONTROL_ARB_RETRY_LIMIT_MASK	GENMASK(13, 6)
+#define SPMI_CONTROL_PRESCALER_MASK		GENMASK(21, 14)
+#define SPMI_CONTROL_RD_LATENCY_MASK		GENMASK(29, 22)
+#define SPMI_CONTROL_ARB_SSC_DELAY_MASK		GENMASK(31, 30)
+
+/* SPMI irq status bit position */
+#define SPMI_IRQ_REQ_CMD_DONE		BIT(0)
+#define SPMI_IRQ_RSP_NEW_CMD		BIT(1)
+#define SPMI_IRQ_ABORT_MST_CMD		BIT(2)
+#define SPMI_IRQ_READ_DATA_PAR_ERR	BIT(3)
+#define SPMI_IRQ_READ_NO_RESP_ERR	BIT(4)
+#define SPMI_IRQ_CMD_NACK_ERR		BIT(5)
+#define SPMI_IRQ_BUS_TIMEOUT		BIT(6)
+#define SPMI_IRQ_NO_BOM_CMD_PAR_ERR	BIT(7)
+#define SPMI_IRQ_NO_BOM_ADDR_LO_PAR_ERR	BIT(8)
+#define SPMI_IRQ_NO_BOM_WR_DATA_PAR_ERR	BIT(9)
+#define SPMI_IRQ_ARB_REQ_TIMER_TIMEOUT	BIT(10)
+#define SPMI_IRQ_IS_BOM			BIT(11)
+#define SPMI_IRQ_CONNECTED		BIT(12)
+
+#define SPMI_ANY_ERROR_IRQ_FLAG			\
+	(					\
+	SPMI_IRQ_ABORT_MST_CMD |		\
+	SPMI_IRQ_READ_DATA_PAR_ERR |		\
+	SPMI_IRQ_READ_NO_RESP_ERR |		\
+	SPMI_IRQ_CMD_NACK_ERR |			\
+	SPMI_IRQ_BUS_TIMEOUT |			\
+	SPMI_IRQ_NO_BOM_CMD_PAR_ERR |		\
+	SPMI_IRQ_NO_BOM_ADDR_LO_PAR_ERR |	\
+	SPMI_IRQ_NO_BOM_WR_DATA_PAR_ERR		\
+	)
+
+/* REQ_COMMAND register fields mask */
+#define SPMI_REQ_COMMAND_NEW_CMD_MASK		BIT(0)
+#define SPMI_REQ_COMMAND_PRIMARY_ARB_MASK	BIT(1)
+#define SPMI_REQ_COMMAND_OPCODE_MASK		GENMASK(6, 2)
+#define SPMI_REQ_COMMAND_ADDR_MASK		GENMASK(10, 7)
+#define SPMI_REQ_COMMAND_BYTE_CNT_MASK		GENMASK(14, 11)
+#define SPMI_REQ_COMMAND_REQ_ADDR_MASK		GENMASK(30, 15)
+
+#define DEFAULT_ARB_RETRY_LIMIT	32
+#define DEFAULT_PRESCALER	0
+#define DEFAULT_READ_LATENCY	32
+#define DEFAULT_ARB_SCL_DELAY	0
+#define REQ_COMMAND_TIMEOUT_MS	100
+#define REQ_COMMAND_TIMEOUT_US	(REQ_COMMAND_TIMEOUT_MS * USEC_PER_MSEC)
+#define REQ_COMMAND_POLL_US	1
+
+enum smartdv_spmi_xfer_type {
+	SMARTDV_SPMI_XFER_CMD = 0,
+	SMARTDV_SPMI_XFER_WRITE = 1,
+	SMARTDV_SPMI_XFER_READ = 2,
+};
+
+/* SmartDV REQ_COMMAND register opcode values (bits [6:2]) */
+enum smartdv_spmi_hc_cmd_op_code {
+	SMARTDV_SPMI_CMD_REG_WRITE = 0,
+	SMARTDV_SPMI_CMD_REG_READ = 1,
+	SMARTDV_SPMI_CMD_EXT_REG_WRITE = 2,
+	SMARTDV_SPMI_CMD_EXT_REG_READ = 3,
+	SMARTDV_SPMI_CMD_EXT_REG_WRITE_L = 4,
+	SMARTDV_SPMI_CMD_EXT_REG_READ_L = 5,
+	SMARTDV_SPMI_CMD_REG_WRITE_0 = 6,
+	SMARTDV_SPMI_CMD_RESET = 10,
+	SMARTDV_SPMI_CMD_SLEEP = 11,
+	SMARTDV_SPMI_CMD_SHUTDOWN = 12,
+	SMARTDV_SPMI_CMD_WAKEUP = 13,
+};
+
+/**
+ * struct smartdv_spmi - SmartDV SPMI driver instance
+ * @ctrl: Pointer to spmi_controller structure
+ * @dev: Pointer to device structure
+ * @base: Virtual address of the SPMI controller registers
+ * @lock: Spinlock to serialize bus access
+ * @i_clk: Hardware clock feeding the controller
+ * @rst: Hardware reset to controller
+ * @clk_freq: Core clock frequency in Hz (i_clk)
+ * @ctrl_reg: Cached control register value from last write
+ */
+struct smartdv_spmi {
+	struct spmi_controller	*ctrl;
+	struct device		*dev;
+	void __iomem		*base;
+	spinlock_t		lock; /* Serialize bus access */
+	struct clk		*i_clk;
+	struct reset_control	*rst;
+	unsigned int		clk_freq;
+	u32			ctrl_reg;
+};
+
+static inline u32 smartdv_spmi_readl(struct smartdv_spmi *sdrv, u32 offset)
+{
+	return readl(sdrv->base + offset);
+}
+
+static inline void smartdv_spmi_writel(struct smartdv_spmi *sdrv, u32 offset, u32 val)
+{
+	writel(val, sdrv->base + offset);
+}
+
+static void smartdv_spmi_read_err_status_dump(struct smartdv_spmi *sdrv)
+{
+	dev_dbg(sdrv->dev, "No response frame & parity error: %#x\n",
+		smartdv_spmi_readl(sdrv, REQ_RD_STATUS));
+	dev_dbg(sdrv->dev, "Read data frame error: %#x\n",
+		smartdv_spmi_readl(sdrv, RD_ERR_INDEX));
+}
+
+static void smartdv_spmi_clear_req_data_reg(struct smartdv_spmi *sdrv)
+{
+	smartdv_spmi_writel(sdrv, REQ_DATA0, 0x0);
+	smartdv_spmi_writel(sdrv, REQ_DATA1, 0x0);
+	smartdv_spmi_writel(sdrv, REQ_DATA2, 0x0);
+	smartdv_spmi_writel(sdrv, REQ_DATA3, 0x0);
+}
+
+static int smartdv_spmi_wait_for_done(struct smartdv_spmi *sdrv, u32 *irq_status)
+{
+	int ret;
+
+	/* wait for cmd done status */
+	ret = readl_poll_timeout_atomic(sdrv->base + IRQ_STATUS, *irq_status,
+					(*irq_status & SPMI_IRQ_REQ_CMD_DONE) != 0,
+					REQ_COMMAND_POLL_US, REQ_COMMAND_TIMEOUT_US);
+	/* clear all interrupts */
+	smartdv_spmi_writel(sdrv, IRQ_STATUS, *irq_status);
+
+	return ret;
+}
+
+static int smartdv_spmi_xfer(struct smartdv_spmi *sdrv,
+			     enum smartdv_spmi_xfer_type xfer_type,
+			     u8 opc, u8 sid, u16 saddr, size_t bc)
+{
+	u32 irq_status;
+	u32 cmd = 0;
+	int ret;
+
+	/* program control register, master enable */
+	smartdv_spmi_writel(sdrv, CONTROL, sdrv->ctrl_reg | SPMI_CONTROL_MASTER_EN);
+
+	/* prepare req_command register */
+	cmd |= SPMI_REQ_COMMAND_NEW_CMD_MASK;
+	cmd |= SPMI_REQ_COMMAND_PRIMARY_ARB_MASK;
+	cmd |= FIELD_PREP(SPMI_REQ_COMMAND_OPCODE_MASK, opc);
+	cmd |= FIELD_PREP(SPMI_REQ_COMMAND_ADDR_MASK, sid);
+
+	if (xfer_type != SMARTDV_SPMI_XFER_CMD) {
+		cmd |= FIELD_PREP(SPMI_REQ_COMMAND_BYTE_CNT_MASK, bc - 1);
+		cmd |= FIELD_PREP(SPMI_REQ_COMMAND_REQ_ADDR_MASK, saddr);
+	}
+
+	/* request new command */
+	smartdv_spmi_writel(sdrv, REQ_COMMAND, cmd);
+
+	ret = smartdv_spmi_wait_for_done(sdrv, &irq_status);
+	if (ret) {
+		dev_err(sdrv->dev, "request timeout.\n");
+		goto out;
+	}
+
+	/* check interrupt status for any error(s) */
+	if (irq_status & SPMI_ANY_ERROR_IRQ_FLAG) {
+		ret = -EIO;
+		dev_err(sdrv->dev,
+			"sid %#x opc %#x addr %#x len %#zx irq_status: %#x\n",
+			sid, opc, saddr, bc, irq_status);
+
+		if (xfer_type == SMARTDV_SPMI_XFER_READ)
+			smartdv_spmi_read_err_status_dump(sdrv);
+	}
+
+out:
+	/* program control register, with master disable */
+	smartdv_spmi_writel(sdrv, CONTROL, sdrv->ctrl_reg);
+
+	return ret;
+}
+
+static void smartdv_spmi_read_req_data(struct smartdv_spmi *sdrv, u8 *buf, size_t bc)
+{
+	u32 addr = REQ_DATA0;
+	size_t len;
+	u32 reg;
+
+	while (bc) {
+		len = min(bc, sizeof(reg));
+		reg = smartdv_spmi_readl(sdrv, addr);
+		memcpy(buf, &reg, len);
+		buf += len;
+		bc -= len;
+		addr += sizeof(reg);
+	}
+}
+
+static int smartdv_spmi_read_cmd(struct spmi_controller *ctrl,
+				 u8 opcode, u8 sid, u16 saddr, u8 *__buf, size_t bc)
+{
+	struct smartdv_spmi *sdrv = spmi_controller_get_drvdata(ctrl);
+	unsigned long flags;
+	int ret;
+	u8 opc;
+
+	switch (opcode) {
+	case SPMI_CMD_READ:
+		opc = SMARTDV_SPMI_CMD_REG_READ;
+		break;
+	case SPMI_CMD_EXT_READ:
+		opc = SMARTDV_SPMI_CMD_EXT_REG_READ;
+		break;
+	case SPMI_CMD_EXT_READL:
+		opc = SMARTDV_SPMI_CMD_EXT_REG_READ_L;
+		break;
+	default:
+		dev_err(&ctrl->dev, "invalid cmd %#x\n", opcode);
+		return -EINVAL;
+	}
+
+	spin_lock_irqsave(&sdrv->lock, flags);
+
+	/* clear req_data registers by writing zeros */
+	smartdv_spmi_clear_req_data_reg(sdrv);
+
+	/* clear read status register */
+	smartdv_spmi_writel(sdrv, REQ_RD_STATUS, 0x0);
+
+	/* initiate transfer on the bus */
+	ret = smartdv_spmi_xfer(sdrv, SMARTDV_SPMI_XFER_READ, opc, sid, saddr, bc);
+	if (!ret)
+		/* read received data */
+		smartdv_spmi_read_req_data(sdrv, __buf, bc);
+
+	spin_unlock_irqrestore(&sdrv->lock, flags);
+
+	return ret;
+}
+
+static void smartdv_spmi_write_req_data(struct smartdv_spmi *sdrv, const u8 *buf, size_t bc)
+{
+	u32 addr = REQ_DATA0;
+	size_t len;
+	u32 data;
+
+	while (bc) {
+		data = 0;
+		len = min(bc, sizeof(data));
+		memcpy(&data, buf, len);
+		smartdv_spmi_writel(sdrv, addr, data);
+		buf += len;
+		bc -= len;
+		addr += sizeof(data);
+	}
+}
+
+static int smartdv_spmi_write_cmd(struct spmi_controller *ctrl,
+				  u8 opcode, u8 sid, u16 saddr, const u8 *__buf, size_t bc)
+{
+	struct smartdv_spmi *sdrv = spmi_controller_get_drvdata(ctrl);
+	unsigned long flags;
+	u8 opc;
+	int ret;
+
+	switch (opcode) {
+	case SPMI_CMD_ZERO_WRITE:
+		opc = SMARTDV_SPMI_CMD_REG_WRITE_0;
+		break;
+	case SPMI_CMD_WRITE:
+		opc = SMARTDV_SPMI_CMD_REG_WRITE;
+		break;
+	case SPMI_CMD_EXT_WRITE:
+		opc = SMARTDV_SPMI_CMD_EXT_REG_WRITE;
+		break;
+	case SPMI_CMD_EXT_WRITEL:
+		opc = SMARTDV_SPMI_CMD_EXT_REG_WRITE_L;
+		break;
+	default:
+		dev_err(&ctrl->dev, "invalid write cmd %#x\n", opcode);
+		return -EINVAL;
+	}
+
+	spin_lock_irqsave(&sdrv->lock, flags);
+
+	/* fill data */
+	smartdv_spmi_write_req_data(sdrv, __buf, bc);
+
+	/* initiate transfer on the bus */
+	ret = smartdv_spmi_xfer(sdrv, SMARTDV_SPMI_XFER_WRITE, opc, sid, saddr, bc);
+
+	spin_unlock_irqrestore(&sdrv->lock, flags);
+
+	return ret;
+}
+
+static int smartdv_spmi_cmd(struct spmi_controller *ctrl, u8 opcode, u8 sid)
+{
+	struct smartdv_spmi *sdrv = spmi_controller_get_drvdata(ctrl);
+	unsigned long flags;
+	int ret;
+	u8 opc;
+
+	switch (opcode) {
+	case SPMI_CMD_RESET:
+		opc = SMARTDV_SPMI_CMD_RESET;
+		break;
+	case SPMI_CMD_SLEEP:
+		opc = SMARTDV_SPMI_CMD_SLEEP;
+		break;
+	case SPMI_CMD_SHUTDOWN:
+		opc = SMARTDV_SPMI_CMD_SHUTDOWN;
+		break;
+	case SPMI_CMD_WAKEUP:
+		opc = SMARTDV_SPMI_CMD_WAKEUP;
+		break;
+	default:
+		dev_err(&ctrl->dev, "invalid cmd %#x\n", opcode);
+		return -EINVAL;
+	}
+
+	spin_lock_irqsave(&sdrv->lock, flags);
+
+	/* initiate transfer on the bus */
+	ret = smartdv_spmi_xfer(sdrv, SMARTDV_SPMI_XFER_CMD, opc, sid, 0, 0);
+
+	spin_unlock_irqrestore(&sdrv->lock, flags);
+
+	return ret;
+}
+
+/* devm action callbacks */
+static void smartdv_spmi_reset_control_assert(void *data)
+{
+	reset_control_assert(data);
+}
+
+static int smartdv_spmi_init_clk_reset(struct smartdv_spmi *sdrv)
+{
+	struct device *dev = sdrv->dev;
+	int ret;
+
+	/* read i_clk rate from the device tree node */
+	device_property_read_u32(dev, "clock-frequency", &sdrv->clk_freq);
+
+	sdrv->i_clk = devm_clk_get_optional_enabled(dev, NULL);
+	if (IS_ERR(sdrv->i_clk))
+		return dev_err_probe(dev, PTR_ERR(sdrv->i_clk), "could not get i_clk\n");
+
+	if (sdrv->i_clk)
+		sdrv->clk_freq = clk_get_rate(sdrv->i_clk);
+
+	/* no clock rate is defined, fail. */
+	if (!sdrv->clk_freq)
+		return dev_err_probe(dev, -EINVAL, "i_clk rate not defined\n");
+
+	/* check for optional reset */
+	sdrv->rst = devm_reset_control_get_optional_exclusive(dev, NULL);
+	if (IS_ERR(sdrv->rst))
+		return dev_err_probe(dev, PTR_ERR(sdrv->rst), "error in get reset ctrl\n");
+
+	if (sdrv->rst) {
+		ret = reset_control_deassert(sdrv->rst);
+		if (ret)
+			return dev_err_probe(dev, ret, "error in deassert reset %d\n", ret);
+
+		ret = devm_add_action_or_reset(dev, smartdv_spmi_reset_control_assert, sdrv->rst);
+		if (ret)
+			return dev_err_probe(dev, ret, "error register rst assert devm action\n");
+	}
+
+	return 0;
+}
+
+static void smartdv_spmi_process_ctrl_reg_dt_param(struct smartdv_spmi *sdrv)
+{
+	struct device *dev = sdrv->dev;
+	u32 ctrlreg = 0;
+	u32 reg;
+
+	/* read control register parameters from the device tree node */
+	reg = 0;
+	device_property_read_u32(dev, "smartdv,master-arb-enable", &reg);
+	ctrlreg |= FIELD_PREP(SPMI_CONTROL_ARB_ENABLE_MASK, reg);
+
+	reg = 0;
+	device_property_read_u32(dev, "smartdv,master-id", &reg);
+	ctrlreg |= FIELD_PREP(SPMI_CONTROL_MID_MASK, reg);
+
+	reg = 0;
+	device_property_read_u32(dev, "smartdv,spmi-version", &reg);
+	ctrlreg |= FIELD_PREP(SPMI_CONTROL_VERSION_MASK, reg);
+
+	reg = DEFAULT_ARB_RETRY_LIMIT;
+	device_property_read_u32(dev, "smartdv,arb-retry-limit", &reg);
+	ctrlreg |= FIELD_PREP(SPMI_CONTROL_ARB_RETRY_LIMIT_MASK, reg);
+
+	reg = DEFAULT_PRESCALER;
+	device_property_read_u32(dev, "smartdv,prescaler", &reg);
+	ctrlreg |= FIELD_PREP(SPMI_CONTROL_PRESCALER_MASK, reg);
+
+	reg = DEFAULT_READ_LATENCY;
+	device_property_read_u32(dev, "smartdv,read-latency", &reg);
+	ctrlreg |= FIELD_PREP(SPMI_CONTROL_RD_LATENCY_MASK, reg);
+
+	reg = DEFAULT_ARB_SCL_DELAY;
+	device_property_read_u32(dev, "smartdv,arb-scl-delay", &reg);
+	ctrlreg |= FIELD_PREP(SPMI_CONTROL_ARB_SSC_DELAY_MASK, reg);
+
+	sdrv->ctrl_reg = ctrlreg;
+}
+
+static void smartdv_spmi_pr_info(struct smartdv_spmi *sdrv)
+{
+	u32 prescaler = FIELD_GET(SPMI_CONTROL_PRESCALER_MASK, sdrv->ctrl_reg);
+
+	dev_dbg(sdrv->dev, "clk %lu kHz, scl %lu kHz (ctrl_reg: %#x)\n",
+		sdrv->clk_freq / HZ_PER_KHZ,
+		sdrv->clk_freq / ((prescaler ? prescaler * 2 : 1) * HZ_PER_KHZ),
+		sdrv->ctrl_reg);
+}
+
+static int smartdv_spmi_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct smartdv_spmi *sdrv;
+	struct spmi_controller *ctrl;
+	int ret;
+
+	ctrl = devm_spmi_controller_alloc(dev, sizeof(*sdrv));
+	if (IS_ERR(ctrl))
+		return PTR_ERR(ctrl);
+
+	sdrv = spmi_controller_get_drvdata(ctrl);
+	sdrv->ctrl = ctrl;
+	sdrv->dev = dev;
+
+	sdrv->base = devm_platform_ioremap_resource(pdev, 0);
+	if (IS_ERR(sdrv->base))
+		return PTR_ERR(sdrv->base);
+
+	platform_set_drvdata(pdev, sdrv);
+
+	/* parse control register parameters from device tree properties */
+	smartdv_spmi_process_ctrl_reg_dt_param(sdrv);
+
+	/* initialize clock and reset if available */
+	ret = smartdv_spmi_init_clk_reset(sdrv);
+	if (ret)
+		return ret;
+
+	spin_lock_init(&sdrv->lock);
+
+	/* Callbacks */
+	ctrl->cmd = smartdv_spmi_cmd;
+	ctrl->read_cmd = smartdv_spmi_read_cmd;
+	ctrl->write_cmd = smartdv_spmi_write_cmd;
+
+	ret = devm_spmi_controller_add(dev, ctrl);
+	if (ret)
+		return dev_err_probe(dev, ret, "spmi_controller_add failed\n");
+
+	smartdv_spmi_pr_info(sdrv);
+
+	return 0;
+}
+
+static const struct of_device_id smartdv_spmi_of_match[] = {
+	{ .compatible = "smartdv,spmi" },
+	{}
+};
+MODULE_DEVICE_TABLE(of, smartdv_spmi_of_match);
+
+static struct platform_driver smartdv_spmi_platform_driver = {
+	.probe = smartdv_spmi_probe,
+	.driver = {
+		.name = "smartdv-spmi",
+		.of_match_table = smartdv_spmi_of_match,
+	},
+};
+
+module_platform_driver(smartdv_spmi_platform_driver);
+
+MODULE_AUTHOR("Vamshi Gajjela <vamshigajjela@google.com>");
+MODULE_DESCRIPTION("SmartDV IP Solutions SPMI controller driver");
+MODULE_LICENSE("GPL");
-- 
2.56.0.317.g454f8302e1-goog

Re: [PATCH 2/3] dt-bindings: spmi: Add SmartDV SPMI controller

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 6751 bytes --]

On Tue, Nov 03, 2026 at 09:56:06AM +0530, vamshi gajjela wrote:
> From: Vamshi Gajjela <vamshigajjela@google.com>
> 
> Document the device tree bindings for the SmartDV IP Solutions MIPI SPMI
> master controller ("smartdv,spmi").
> 
> This controller IP is integrated in Google Tensor SoCs starting with the
> G5 generation (codename: laguna, canonically written as "lga"), so add
> "google,lga-spmi" with a fallback to "smartdv,spmi".
> 
> Signed-off-by: Vamshi Gajjela <vamshigajjela@google.com>
> ---
>  .../bindings/spmi/smartdv,spmi.yaml           | 126 ++++++++++++++++++
>  MAINTAINERS                                   |   6 +
>  2 files changed, 132 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/spmi/smartdv,spmi.yaml
> 
> diff --git a/Documentation/devicetree/bindings/spmi/smartdv,spmi.yaml b/Documentation/devicetree/bindings/spmi/smartdv,spmi.yaml
> new file mode 100644
> index 000000000000..e0512e60d932
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/spmi/smartdv,spmi.yaml
> @@ -0,0 +1,126 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/spmi/smartdv,spmi.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: SmartDV IP Solutions SPMI Controller
> +
> +maintainers:
> +  - Vamshi Gajjela <vamshigajjela@google.com>
> +
> +description:
> +  SmartDV IP Solutions MIPI System Power Management Interface (SPMI) master
> +  controller supporting MIPI SPMI Specification versions 1.0 and 2.0.
> +
> +allOf:
> +  - $ref: spmi.yaml#
> +
> +properties:
> +  compatible:
> +    oneOf:
> +      - items:
> +          - const: google,lga-spmi

> +          - const: smartdv,spmi
> +      - const: smartdv,spmi

I hate compatibles for purchasable IP like this, particularly when
unversioned as they maybe become effectively useless when a new revision
releases. The standalone smartdv,spmi compatible has to go at least,
soc-specific compatibles are mandatory.

> +
> +  reg:
> +    maxItems: 1
> +
> +  clocks:
> +    description:
> +      Core clock to the controller from which SPMI SCL is derived. Optional if
> +      the controller uses a free-running clock and clock-frequency is specified.
> +    maxItems: 1
> +
> +  resets:
> +    maxItems: 1
> +
> +  clock-frequency:
> +    description:
> +      Input core clock frequency in Hz when the controller uses a free-running
> +      clock not described in clocks.
> +
> +  smartdv,master-arb-enable:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    enum: [0, 1]
> +    default: 0
> +    description:
> +      Enable master bus arbitration phase (0 = disable, 1 = enable).

What aspect of board design governs the decision here?
Why can it not be determined from the soc specific compatible?

> +
> +  smartdv,master-id:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    minimum: 0
> +    maximum: 3
> +    default: 0
> +    description:
> +      Master ID for the controller on the SPMI bus.

What aspect of board design governs the decision here?
Why can it not be determined from the soc specific compatible?


> +
> +  smartdv,spmi-version:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    enum: [0, 1]
> +    default: 0
> +    description:
> +      MIPI SPMI specification version used for transfers (0 for MIPI SPMI v1.0,
> +      1 for MIPI SPMI v2.0).

What aspect of board design governs the decision here?
Why can it not be determined from the soc specific compatible?


> +
> +  smartdv,arb-retry-limit:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    minimum: 0
> +    maximum: 255
> +    default: 32
> +    description:
> +      Maximum number of times the master retries a command when losing bus
> +      arbitration.

What aspect of board design governs the decision here?
Why can it not be determined from the soc specific compatible?


> +
> +  smartdv,prescaler:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    minimum: 0
> +    maximum: 255
> +    default: 0
> +    description:
> +      Clock divider value to generate SPMI SCL from the input core clock. Writing
> +      1 divides the system clock by 2; more generally, a non-zero value n
> +      divides the system clock by 2 * n.

What aspect of board design governs the decision here?
Why can it not be determined from the soc specific compatible?


> +
> +  smartdv,read-latency:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    minimum: 0
> +    maximum: 255
> +    default: 32
> +    description:
> +      Number of SPMI SCL clock cycles to pause during bus turnaround on read
> +      commands to allow the target device to fetch data.

What aspect of board design governs the decision here?
Why can it not be determined from the soc specific compatible?


> +
> +  smartdv,arb-scl-delay:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    minimum: 0
> +    maximum: 3
> +    default: 0
> +    description:
> +      Delay between arbitration and Sequence Start Condition (SSC) when the
> +      controller is the Bus Owner Master (BOM).

What aspect of board design governs the decision here?
Why can it not be determined from the soc specific compatible?


> +
> +required:
> +  - compatible
> +  - reg

I find it hard to believe that this is the set of required properties.

pw-bot: changes-requested

Thanks,
Conor.

> +
> +unevaluatedProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/spmi/spmi.h>
> +
> +    spmi@14853000 {
> +        compatible = "google,lga-spmi", "smartdv,spmi";
> +        reg = <0x14853000 0x100>;
> +        #address-cells = <2>;
> +        #size-cells = <0>;
> +        clock-frequency = <19200000>;
> +        smartdv,master-arb-enable = <1>;
> +        smartdv,spmi-version = <1>;
> +
> +        pmic@f {
> +            reg = <0xf SPMI_USID>;
> +        };
> +    };
> diff --git a/MAINTAINERS b/MAINTAINERS
> index eaeb60c1e1c2..f44c597c2075 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -25243,6 +25243,12 @@ T:	git https://github.com/cschaufler/smack-next.git
>  F:	Documentation/admin-guide/LSM/Smack.rst
>  F:	security/smack/
>  
> +SMARTDV SPMI CONTROLLER DRIVER
> +M:	Vamshi Gajjela <vamshigajjela@google.com>
> +L:	linux-kernel@vger.kernel.org
> +S:	Maintained
> +F:	Documentation/devicetree/bindings/spmi/smartdv,spmi.yaml
> +
>  SMBDIRECT (RDMA Stream Transport with Read/Write-Offload, MS-SMBD)
>  M:	Steve French <smfrench@gmail.com>
>  M:	Steve French <sfrench@samba.org>
> -- 
> 2.56.0.317.g454f8302e1-goog
> 

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Re: [PATCH 1/3] dt-bindings: vendor-prefixes: Add smartdv

[Krzysztof Kozlowski]

On Tue, Nov 03, 2026 at 09:56:05AM +0530, vamshi gajjela wrote:
> From: Vamshi Gajjela <vamshigajjela@google.com>
> 
> Add the "smartdv" vendor prefix for SmartDV IP Solutions Private
> Limited.

There are multiple smartdv companies with different domains, so I guess
you want smartdv-ips? Or maybe all companies are the same?

Best regards,
Krzysztof

Re: [PATCH 2/3] dt-bindings: spmi: Add SmartDV SPMI controller

[Krzysztof Kozlowski]

On Tue, Nov 03, 2026 at 09:56:06AM +0530, vamshi gajjela wrote:
> From: Vamshi Gajjela <vamshigajjela@google.com>
> 
> Document the device tree bindings for the SmartDV IP Solutions MIPI SPMI
> master controller ("smartdv,spmi").
> 
> This controller IP is integrated in Google Tensor SoCs starting with the
> G5 generation (codename: laguna, canonically written as "lga"), so add
> "google,lga-spmi" with a fallback to "smartdv,spmi".
> 
> Signed-off-by: Vamshi Gajjela <vamshigajjela@google.com>
> ---
>  .../bindings/spmi/smartdv,spmi.yaml           | 126 ++++++++++++++++++
>  MAINTAINERS                                   |   6 +
>  2 files changed, 132 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/spmi/smartdv,spmi.yaml
> 
> diff --git a/Documentation/devicetree/bindings/spmi/smartdv,spmi.yaml b/Documentation/devicetree/bindings/spmi/smartdv,spmi.yaml
> new file mode 100644
> index 000000000000..e0512e60d932
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/spmi/smartdv,spmi.yaml
> @@ -0,0 +1,126 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/spmi/smartdv,spmi.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: SmartDV IP Solutions SPMI Controller
> +
> +maintainers:
> +  - Vamshi Gajjela <vamshigajjela@google.com>
> +
> +description:
> +  SmartDV IP Solutions MIPI System Power Management Interface (SPMI) master
> +  controller supporting MIPI SPMI Specification versions 1.0 and 2.0.
> +
> +allOf:
> +  - $ref: spmi.yaml#
> +
> +properties:
> +  compatible:
> +    oneOf:
> +      - items:
> +          - const: google,lga-spmi
> +          - const: smartdv,spmi
> +      - const: smartdv,spmi
> +
> +  reg:
> +    maxItems: 1
> +
> +  clocks:
> +    description:
> +      Core clock to the controller from which SPMI SCL is derived. Optional if
> +      the controller uses a free-running clock and clock-frequency is specified.

Don't repeat constraints in free form text. Just create proper
constraints.

> +    maxItems: 1
> +
> +  resets:
> +    maxItems: 1
> +
> +  clock-frequency:
> +    description:
> +      Input core clock frequency in Hz when the controller uses a free-running
> +      clock not described in clocks.

Why clock would not be described in clocks? From where does it come?

> +
> +  smartdv,master-arb-enable:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    enum: [0, 1]
> +    default: 0
> +    description:
> +      Enable master bus arbitration phase (0 = disable, 1 = enable).
> +
> +  smartdv,master-id:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    minimum: 0
> +    maximum: 3
> +    default: 0
> +    description:
> +      Master ID for the controller on the SPMI bus.

smartdv,bus-id, I guess

> +
> +  smartdv,spmi-version:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    enum: [0, 1]
> +    default: 0
> +    description:
> +      MIPI SPMI specification version used for transfers (0 for MIPI SPMI v1.0,
> +      1 for MIPI SPMI v2.0).

And why would that be board level configuration?

> +
> +  smartdv,arb-retry-limit:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    minimum: 0
> +    maximum: 255
> +    default: 32
> +    description:
> +      Maximum number of times the master retries a command when losing bus
> +      arbitration.
> +
> +  smartdv,prescaler:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    minimum: 0
> +    maximum: 255
> +    default: 0
> +    description:
> +      Clock divider value to generate SPMI SCL from the input core clock. Writing
> +      1 divides the system clock by 2; more generally, a non-zero value n
> +      divides the system clock by 2 * n.
> +
> +  smartdv,read-latency:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    minimum: 0
> +    maximum: 255
> +    default: 32
> +    description:
> +      Number of SPMI SCL clock cycles to pause during bus turnaround on read
> +      commands to allow the target device to fetch data.
> +
> +  smartdv,arb-scl-delay:

Except Conor's comments, some of the properties here should use proper
units.

> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    minimum: 0
> +    maximum: 3
> +    default: 0
> +    description:
> +      Delay between arbitration and Sequence Start Condition (SSC) when the
> +      controller is the Bus Owner Master (BOM).
> +
> +required:
> +  - compatible
> +  - reg

Best regards,
Krzysztof