[PATCH 0/3] arm64: dts: qcom: sm8350: Add CCI and camera MCLK pins

[PATCH 0/3] arm64: dts: qcom: sm8350: Add CCI and camera MCLK pins

[Vladimir Zapolskiy]

Add Qualcomm SM8350 Camera Control Interface (CCI) controllers and the
pin configurations of camera sensor master clock outputs.

The series depends on the SM8350 camera clock controller support:

  https://lore.kernel.org/all/20261104001704.2744766-1-vz@kernel.org/

Vladimir Zapolskiy (3):
  dt-bindings: i2c: qcom-cci: Document SM8350 compatible
  arm64: dts: qcom: sm8350: Add CCI device tree nodes
  arm64: dts: qcom: sm8350: Add camera MCLK pinctrl states

 .../devicetree/bindings/i2c/qcom,i2c-cci.yaml |   2 +
 arch/arm64/boot/dts/qcom/sm8350.dtsi          | 231 ++++++++++++++++++
 2 files changed, 233 insertions(+)

-- 
2.51.0

[PATCH 1/3] dt-bindings: i2c: qcom-cci: Document SM8350 compatible

[Vladimir Zapolskiy]

Add Qualcomm SM8350 SoC compatible to the CCI device tree bindings,
SM8350 CCI is compatible with CCI v2 found on MSM8996.

Signed-off-by: Vladimir Zapolskiy <vz@kernel.org>
---
 Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml
index 1e8def25ec0e..63083e0bdd9c 100644
--- a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml
+++ b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml
@@ -40,6 +40,7 @@ properties:
               - qcom,sm6150-cci
               - qcom,sm6350-cci
               - qcom,sm8250-cci
+              - qcom,sm8350-cci
               - qcom,sm8450-cci
               - qcom,sm8550-cci
               - qcom,sm8650-cci
@@ -219,6 +220,7 @@ allOf:
             enum:
               - qcom,sc7280-cci
               - qcom,sm8250-cci
+              - qcom,sm8350-cci
               - qcom,sm8450-cci
     then:
       properties:
-- 
2.51.0

[PATCH 2/3] arm64: dts: qcom: sm8350: Add CCI device tree nodes

[Vladimir Zapolskiy]

Add Camera Control Interface (CCI) controller device tree nodes and pin
configurations of the I2C busses to SM8350 SoC dtsi.

Signed-off-by: Vladimir Zapolskiy <vz@kernel.org>
---
 arch/arm64/boot/dts/qcom/sm8350.dtsi | 147 +++++++++++++++++++++++++++
 1 file changed, 147 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index a51942c99f8a..41dff3736061 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -10,6 +10,7 @@
 #include <dt-bindings/clock/qcom,gcc-sm8350.h>
 #include <dt-bindings/clock/qcom,gpucc-sm8350.h>
 #include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/clock/qcom,sm8350-camcc.h>
 #include <dt-bindings/clock/qcom,sm8350-videocc.h>
 #include <dt-bindings/dma/qcom-gpi.h>
 #include <dt-bindings/firmware/qcom,scm.h>
@@ -2830,6 +2831,88 @@ videocc: clock-controller@abf0000 {
 			#power-domain-cells = <1>;
 		};
 
+		cci0: cci@ac4f000 {
+			compatible = "qcom,sm8350-cci", "qcom,msm8996-cci";
+			reg = <0 0x0ac4f000 0 0x1000>;
+			interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
+			power-domains = <&camcc TITAN_TOP_GDSC>;
+
+			clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
+				 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
+				 <&camcc CAM_CC_CPAS_AHB_CLK>,
+				 <&camcc CAM_CC_CCI_0_CLK>,
+				 <&camcc CAM_CC_CCI_0_CLK_SRC>;
+			clock-names = "camnoc_axi",
+				      "slow_ahb_src",
+				      "cpas_ahb",
+				      "cci",
+				      "cci_src";
+
+			pinctrl-0 = <&cci0_0_default &cci0_1_default>;
+			pinctrl-1 = <&cci0_0_sleep &cci0_1_sleep>;
+			pinctrl-names = "default", "sleep";
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			status = "disabled";
+
+			cci0_i2c0: i2c-bus@0 {
+				reg = <0>;
+				clock-frequency = <1000000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+			};
+
+			cci0_i2c1: i2c-bus@1 {
+				reg = <1>;
+				clock-frequency = <1000000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+			};
+		};
+
+		cci1: cci@ac50000 {
+			compatible = "qcom,sm8350-cci", "qcom,msm8996-cci";
+			reg = <0 0x0ac50000 0 0x1000>;
+			interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>;
+			power-domains = <&camcc TITAN_TOP_GDSC>;
+
+			clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
+				 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
+				 <&camcc CAM_CC_CPAS_AHB_CLK>,
+				 <&camcc CAM_CC_CCI_1_CLK>,
+				 <&camcc CAM_CC_CCI_1_CLK_SRC>;
+			clock-names = "camnoc_axi",
+				      "slow_ahb_src",
+				      "cpas_ahb",
+				      "cci",
+				      "cci_src";
+
+			pinctrl-0 = <&cci1_0_default &cci1_1_default>;
+			pinctrl-1 = <&cci1_0_sleep &cci1_1_sleep>;
+			pinctrl-names = "default", "sleep";
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			status = "disabled";
+
+			cci1_i2c0: i2c-bus@0 {
+				reg = <0>;
+				clock-frequency = <1000000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+			};
+
+			cci1_i2c1: i2c-bus@1 {
+				reg = <1>;
+				clock-frequency = <1000000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+			};
+		};
+
 		camcc: clock-controller@ad00000 {
 			compatible = "qcom,sm8350-camcc";
 			reg = <0 0x0ad00000 0 0x10000>;
@@ -3348,6 +3431,70 @@ tlmm: pinctrl@f100000 {
 			gpio-ranges = <&tlmm 0 0 204>;
 			wakeup-parent = <&pdc>;
 
+			cci0_0_default: cci0-0-default-state {
+				/* SDA, SCL */
+				pins = "gpio107", "gpio108";
+				function = "cci_i2c";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			cci0_0_sleep: cci0-0-sleep-state {
+				/* SDA, SCL */
+				pins = "gpio107", "gpio108";
+				function = "cci_i2c";
+				drive-strength = <2>;
+				bias-pull-down;
+			};
+
+			cci0_1_default: cci0-1-default-state {
+				/* SDA, SCL */
+				pins = "gpio109", "gpio110";
+				function = "cci_i2c";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			cci0_1_sleep: cci0-1-sleep-state {
+				/* SDA, SCL */
+				pins = "gpio109", "gpio110";
+				function = "cci_i2c";
+				drive-strength = <2>;
+				bias-pull-down;
+			};
+
+			cci1_0_default: cci1-0-default-state {
+				/* SDA, SCL */
+				pins = "gpio111", "gpio112";
+				function = "cci_i2c";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			cci1_0_sleep: cci1-0-sleep-state {
+				/* SDA, SCL */
+				pins = "gpio111", "gpio112";
+				function = "cci_i2c";
+				drive-strength = <2>;
+				bias-pull-down;
+			};
+
+			cci1_1_default: cci1-1-default-state {
+				/* SDA, SCL */
+				pins = "gpio113", "gpio114";
+				function = "cci_i2c";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			cci1_1_sleep: cci1-1-sleep-state {
+				/* SDA, SCL */
+				pins = "gpio113", "gpio114";
+				function = "cci_i2c";
+				drive-strength = <2>;
+				bias-pull-down;
+			};
+
 			sdc2_default_state: sdc2-default-state {
 				clk-pins {
 					pins = "sdc2_clk";
-- 
2.51.0

[PATCH 3/3] arm64: dts: qcom: sm8350: Add camera MCLK pinctrl states

[Vladimir Zapolskiy]

Add pinctrl states of six camera sensor MCLK output pins found on
Qualcomm SM8350 SoC.

Signed-off-by: Vladimir Zapolskiy <vz@kernel.org>
---
 arch/arm64/boot/dts/qcom/sm8350.dtsi | 84 ++++++++++++++++++++++++++++
 1 file changed, 84 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index 41dff3736061..437ceaa28fbd 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -3431,6 +3431,90 @@ tlmm: pinctrl@f100000 {
 			gpio-ranges = <&tlmm 0 0 204>;
 			wakeup-parent = <&pdc>;
 
+			cam_mclk0_default: cam-mclk0-default-state {
+				pins = "gpio100";
+				function = "cam_mclk";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			cam_mclk0_sleep: cam-mclk0-sleep-state {
+				pins = "gpio100";
+				function = "cam_mclk";
+				drive-strength = <2>;
+				bias-pull-down;
+			};
+
+			cam_mclk1_default: cam-mclk1-default-state {
+				pins = "gpio101";
+				function = "cam_mclk";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			cam_mclk1_sleep: cam-mclk1-sleep-state {
+				pins = "gpio101";
+				function = "cam_mclk";
+				drive-strength = <2>;
+				bias-pull-down;
+			};
+
+			cam_mclk2_default: cam-mclk2-default-state {
+				pins = "gpio102";
+				function = "cam_mclk";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			cam_mclk2_sleep: cam-mclk2-sleep-state {
+				pins = "gpio102";
+				function = "cam_mclk";
+				drive-strength = <2>;
+				bias-pull-down;
+			};
+
+			cam_mclk3_default: cam-mclk3-default-state {
+				pins = "gpio103";
+				function = "cam_mclk";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			cam_mclk3_sleep: cam-mclk3-sleep-state {
+				pins = "gpio103";
+				function = "cam_mclk";
+				drive-strength = <2>;
+				bias-pull-down;
+			};
+
+			cam_mclk4_default: cam-mclk4-default-state {
+				pins = "gpio104";
+				function = "cam_mclk";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			cam_mclk4_sleep: cam-mclk4-sleep-state {
+				pins = "gpio104";
+				function = "cam_mclk";
+				drive-strength = <2>;
+				bias-pull-down;
+			};
+
+			cam_mclk5_default: cam-mclk5-default-state {
+				pins = "gpio105";
+				function = "cam_mclk";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			cam_mclk5_sleep: cam-mclk5-sleep-state {
+				pins = "gpio105";
+				function = "cam_mclk";
+				drive-strength = <2>;
+				bias-pull-down;
+			};
+
 			cci0_0_default: cci0-0-default-state {
 				/* SDA, SCL */
 				pins = "gpio107", "gpio108";
-- 
2.51.0

Re: [PATCH 2/3] arm64: dts: qcom: sm8350: Add CCI device tree nodes

[Loic Poulain]

On Thu, Nov 5, 2026 at 12:05 AM Vladimir Zapolskiy <vz@kernel.org> wrote:
>
> Add Camera Control Interface (CCI) controller device tree nodes and pin
> configurations of the I2C busses to SM8350 SoC dtsi.
>
> Signed-off-by: Vladimir Zapolskiy <vz@kernel.org>
> ---
>  arch/arm64/boot/dts/qcom/sm8350.dtsi | 147 +++++++++++++++++++++++++++
>  1 file changed, 147 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
> index a51942c99f8a..41dff3736061 100644
> --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
> @@ -10,6 +10,7 @@
>  #include <dt-bindings/clock/qcom,gcc-sm8350.h>
>  #include <dt-bindings/clock/qcom,gpucc-sm8350.h>
>  #include <dt-bindings/clock/qcom,rpmh.h>
> +#include <dt-bindings/clock/qcom,sm8350-camcc.h>
>  #include <dt-bindings/clock/qcom,sm8350-videocc.h>
>  #include <dt-bindings/dma/qcom-gpi.h>
>  #include <dt-bindings/firmware/qcom,scm.h>
> @@ -2830,6 +2831,88 @@ videocc: clock-controller@abf0000 {
>                         #power-domain-cells = <1>;
>                 };
>
> +               cci0: cci@ac4f000 {
> +                       compatible = "qcom,sm8350-cci", "qcom,msm8996-cci";
> +                       reg = <0 0x0ac4f000 0 0x1000>;
> +                       interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
> +                       power-domains = <&camcc TITAN_TOP_GDSC>;
> +
> +                       clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
> +                                <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
> +                                <&camcc CAM_CC_CPAS_AHB_CLK>,
> +                                <&camcc CAM_CC_CCI_0_CLK>,
> +                                <&camcc CAM_CC_CCI_0_CLK_SRC>;
> +                       clock-names = "camnoc_axi",
> +                                     "slow_ahb_src",
> +                                     "cpas_ahb",
> +                                     "cci",
> +                                     "cci_src";
> +
> +                       pinctrl-0 = <&cci0_0_default &cci0_1_default>;
> +                       pinctrl-1 = <&cci0_0_sleep &cci0_1_sleep>;
> +                       pinctrl-names = "default", "sleep";
> +
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +
> +                       status = "disabled";
> +
> +                       cci0_i2c0: i2c-bus@0 {
> +                               reg = <0>;
> +                               clock-frequency = <1000000>;
> +                               #address-cells = <1>;
> +                               #size-cells = <0>;
> +                       };
> +
> +                       cci0_i2c1: i2c-bus@1 {
> +                               reg = <1>;
> +                               clock-frequency = <1000000>;
> +                               #address-cells = <1>;
> +                               #size-cells = <0>;
> +                       };
> +               };
> +
> +               cci1: cci@ac50000 {
> +                       compatible = "qcom,sm8350-cci", "qcom,msm8996-cci";
> +                       reg = <0 0x0ac50000 0 0x1000>;
> +                       interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>;
> +                       power-domains = <&camcc TITAN_TOP_GDSC>;
> +
> +                       clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
> +                                <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
> +                                <&camcc CAM_CC_CPAS_AHB_CLK>,
> +                                <&camcc CAM_CC_CCI_1_CLK>,
> +                                <&camcc CAM_CC_CCI_1_CLK_SRC>;
> +                       clock-names = "camnoc_axi",
> +                                     "slow_ahb_src",
> +                                     "cpas_ahb",
> +                                     "cci",
> +                                     "cci_src";
> +
> +                       pinctrl-0 = <&cci1_0_default &cci1_1_default>;
> +                       pinctrl-1 = <&cci1_0_sleep &cci1_1_sleep>;
> +                       pinctrl-names = "default", "sleep";
> +
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +
> +                       status = "disabled";
> +
> +                       cci1_i2c0: i2c-bus@0 {
> +                               reg = <0>;
> +                               clock-frequency = <1000000>;
> +                               #address-cells = <1>;
> +                               #size-cells = <0>;
> +                       };
> +
> +                       cci1_i2c1: i2c-bus@1 {
> +                               reg = <1>;
> +                               clock-frequency = <1000000>;
> +                               #address-cells = <1>;
> +                               #size-cells = <0>;
> +                       };
> +               };
> +
>                 camcc: clock-controller@ad00000 {
>                         compatible = "qcom,sm8350-camcc";
>                         reg = <0 0x0ad00000 0 0x10000>;
> @@ -3348,6 +3431,70 @@ tlmm: pinctrl@f100000 {
>                         gpio-ranges = <&tlmm 0 0 204>;
>                         wakeup-parent = <&pdc>;
>
> +                       cci0_0_default: cci0-0-default-state {
> +                               /* SDA, SCL */
> +                               pins = "gpio107", "gpio108";
> +                               function = "cci_i2c";
> +                               drive-strength = <2>;
> +                               bias-pull-up;

I had similar comments on a different platform, but why pull-up here
(for SCL/SDA)? Do we expect boards to lack the external pull-ups
required by I2C? If not, enabling the internal pull-ups seems
unnecessary. Also, what is their effective resistance on these
platforms? Aren't they typically too weak to meet the rise-time
requirements of most I2C modes anyway?

> +                       };
> +
> +                       cci0_0_sleep: cci0-0-sleep-state {
> +                               /* SDA, SCL */
> +                               pins = "gpio107", "gpio108";
> +                               function = "cci_i2c";
> +                               drive-strength = <2>;
> +                               bias-pull-down;
> +                       };
> +
> +                       cci0_1_default: cci0-1-default-state {
> +                               /* SDA, SCL */
> +                               pins = "gpio109", "gpio110";
> +                               function = "cci_i2c";
> +                               drive-strength = <2>;
> +                               bias-pull-up;
> +                       };
> +
> +                       cci0_1_sleep: cci0-1-sleep-state {
> +                               /* SDA, SCL */
> +                               pins = "gpio109", "gpio110";
> +                               function = "cci_i2c";
> +                               drive-strength = <2>;
> +                               bias-pull-down;
> +                       };
> +
> +                       cci1_0_default: cci1-0-default-state {
> +                               /* SDA, SCL */
> +                               pins = "gpio111", "gpio112";
> +                               function = "cci_i2c";
> +                               drive-strength = <2>;
> +                               bias-pull-up;
> +                       };
> +
> +                       cci1_0_sleep: cci1-0-sleep-state {
> +                               /* SDA, SCL */
> +                               pins = "gpio111", "gpio112";
> +                               function = "cci_i2c";
> +                               drive-strength = <2>;
> +                               bias-pull-down;
> +                       };
> +
> +                       cci1_1_default: cci1-1-default-state {
> +                               /* SDA, SCL */
> +                               pins = "gpio113", "gpio114";
> +                               function = "cci_i2c";
> +                               drive-strength = <2>;
> +                               bias-pull-up;
> +                       };
> +
> +                       cci1_1_sleep: cci1-1-sleep-state {
> +                               /* SDA, SCL */
> +                               pins = "gpio113", "gpio114";
> +                               function = "cci_i2c";
> +                               drive-strength = <2>;
> +                               bias-pull-down;
> +                       };
> +
>                         sdc2_default_state: sdc2-default-state {
>                                 clk-pins {
>                                         pins = "sdc2_clk";
> --
> 2.51.0
>

Re: [PATCH 1/3] dt-bindings: i2c: qcom-cci: Document SM8350 compatible

[Loic Poulain]

On Thu, Nov 5, 2026 at 12:05 AM Vladimir Zapolskiy <vz@kernel.org> wrote:
>
> Add Qualcomm SM8350 SoC compatible to the CCI device tree bindings,
> SM8350 CCI is compatible with CCI v2 found on MSM8996.
>
> Signed-off-by: Vladimir Zapolskiy <vz@kernel.org>

Reviewed-by: Loic Poulain <loic.poulain@oss.qualcomm.com>


> ---
>  Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml
> index 1e8def25ec0e..63083e0bdd9c 100644
> --- a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml
> +++ b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml
> @@ -40,6 +40,7 @@ properties:
>                - qcom,sm6150-cci
>                - qcom,sm6350-cci
>                - qcom,sm8250-cci
> +              - qcom,sm8350-cci
>                - qcom,sm8450-cci
>                - qcom,sm8550-cci
>                - qcom,sm8650-cci
> @@ -219,6 +220,7 @@ allOf:
>              enum:
>                - qcom,sc7280-cci
>                - qcom,sm8250-cci
> +              - qcom,sm8350-cci
>                - qcom,sm8450-cci
>      then:
>        properties:
> --
> 2.51.0
>

Re: [PATCH 3/3] arm64: dts: qcom: sm8350: Add camera MCLK pinctrl states

[Konrad Dybcio]

On 11/5/26 12:05 AM, Vladimir Zapolskiy wrote:
> Add pinctrl states of six camera sensor MCLK output pins found on
> Qualcomm SM8350 SoC.
> 
> Signed-off-by: Vladimir Zapolskiy <vz@kernel.org>
> ---

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad