[PATCH 0/4] media: qcom: camss: Add SM8350 CAMSS support

[PATCH 0/4] media: qcom: camss: Add SM8350 CAMSS support

[Vladimir Zapolskiy]

Add support of the camera subsystem (CAMSS) found on Qualcomm SM8350
SoC containing:
* three CSID and two CSID lite blocks,
* three VFE and two VFE lite blocks.

The SM8350 CSID and VFE block are programmed like on SM8250.

The series depends on the SM8350 camera clock controller support and
on the change from SM8450 CAMSS series, which allows CSI2 PHY devices
without CSIPHY resources:

  https://lore.kernel.org/all/20261104001704.2744766-1-vz@kernel.org/
  https://lore.kernel.org/all/20261026224957.1115370-4-vz@kernel.org/

SM8350 CSIPHYs are described as separate CSI2 PHY devices, and their
support will be added separately along with their connection to
the CAMSS input ports.

Tested on SM8350-HDK with the CSID internal test pattern generator,
the GCC camera HF AXI and the IFE lite AXI clocks are described in the
device tree bindings, but apparently they are not needed to stream
from TPG:

  media-ctl -d /dev/media0 -r
  media-ctl -d /dev/media0 -l '"msm_csid0":1->"msm_vfe0_rdi0":0[1]'
  media-ctl -d /dev/media0 \
      -V '"msm_csid0":0[fmt:SRGGB10_1X10/1920x1080 field:none]'
  media-ctl -d /dev/media0 \
      -V '"msm_vfe0_rdi0":0[fmt:SRGGB10_1X10/1920x1080 field:none]'
  CSID0=$(media-ctl -d /dev/media0 -e msm_csid0)
  VID0=$(media-ctl -d /dev/media0 -e msm_vfe0_video0)
  v4l2-ctl -d $CSID0 -c test_pattern=9
  yavta -B capture-mplane -c10 -n5 -I -f SRGGB10P -s 1920x1080 -F $VID0

Vladimir Zapolskiy (4):
  dt-bindings: media: Add Qualcomm SM8350 CAMSS
  media: qcom: camss: Select Titan 480 CSID offset by VFE type
  media: qcom: camss: Add SM8350 CAMSS support
  arm64: dts: qcom: sm8350: Add CAMSS device tree node

 .../bindings/media/qcom,sm8350-camss.yaml     | 262 ++++++++++++++++++
 arch/arm64/boot/dts/qcom/sm8350.dtsi          | 110 ++++++++
 .../media/platform/qcom/camss/camss-csid.c    |   5 +-
 drivers/media/platform/qcom/camss/camss-vfe.c |   2 +
 drivers/media/platform/qcom/camss/camss.c     | 213 ++++++++++++++
 drivers/media/platform/qcom/camss/camss.h     |   1 +
 6 files changed, 591 insertions(+), 2 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/media/qcom,sm8350-camss.yaml

-- 
2.51.0

[PATCH 1/4] dt-bindings: media: Add Qualcomm SM8350 CAMSS

[Vladimir Zapolskiy]

Add device tree bindings documentation of Qualcomm SM8350 camera
subsystem.

Qualcomm SM8350 CAMSS contains:
* three CSID and two CSID lite blocks,
* three VFE and two VFE lite blocks,
* six CSIPHY devices are described as separate CSI2 PHY devices.

The SM8350 CAMSS is very similar to the previous generation SM8250 CAMSS,
CSID register spaces are placed inside VFE register spaces.

Signed-off-by: Vladimir Zapolskiy <vz@kernel.org>
---
 .../bindings/media/qcom,sm8350-camss.yaml     | 262 ++++++++++++++++++
 1 file changed, 262 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/media/qcom,sm8350-camss.yaml

diff --git a/Documentation/devicetree/bindings/media/qcom,sm8350-camss.yaml b/Documentation/devicetree/bindings/media/qcom,sm8350-camss.yaml
new file mode 100644
index 000000000000..89504ebdf773
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/qcom,sm8350-camss.yaml
@@ -0,0 +1,262 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/qcom,sm8350-camss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SM8350 Camera Subsystem (CAMSS)
+
+maintainers:
+  - Vladimir Zapolskiy <vz@kernel.org>
+
+description:
+  The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms.
+
+properties:
+  compatible:
+    const: qcom,sm8350-camss
+
+  reg:
+    maxItems: 5
+
+  reg-names:
+    items:
+      - const: vfe0
+      - const: vfe1
+      - const: vfe2
+      - const: vfe_lite0
+      - const: vfe_lite1
+
+  clocks:
+    maxItems: 26
+
+  clock-names:
+    items:
+      - const: camnoc_axi
+      - const: cpas_ahb
+      - const: gcc_hf_axi
+      - const: vfe0
+      - const: vfe0_ahb
+      - const: vfe0_areg
+      - const: vfe0_axi
+      - const: vfe0_cphy_rx
+      - const: vfe0_csid
+      - const: vfe1
+      - const: vfe1_ahb
+      - const: vfe1_areg
+      - const: vfe1_axi
+      - const: vfe1_cphy_rx
+      - const: vfe1_csid
+      - const: vfe2
+      - const: vfe2_ahb
+      - const: vfe2_areg
+      - const: vfe2_axi
+      - const: vfe2_cphy_rx
+      - const: vfe2_csid
+      - const: vfe_lite
+      - const: vfe_lite_ahb
+      - const: vfe_lite_axi
+      - const: vfe_lite_cphy_rx
+      - const: vfe_lite_csid
+
+  interrupts:
+    maxItems: 10
+
+  interrupt-names:
+    items:
+      - const: csid0
+      - const: csid1
+      - const: csid2
+      - const: csid_lite0
+      - const: csid_lite1
+      - const: vfe0
+      - const: vfe1
+      - const: vfe2
+      - const: vfe_lite0
+      - const: vfe_lite1
+
+  iommus:
+    items:
+      - description: S1 HLOS IFE and IFE_LITE non-protected
+
+  interconnects:
+    maxItems: 2
+
+  interconnect-names:
+    items:
+      - const: ahb
+      - const: hf_mnoc
+
+  power-domains:
+    items:
+      - description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller.
+      - description: IFE1 GDSC - Image Front End, Global Distributed Switch Controller.
+      - description: IFE2 GDSC - Image Front End, Global Distributed Switch Controller.
+      - description: Titan GDSC - Titan ISP Block, Global Distributed Switch Controller.
+
+  power-domain-names:
+    items:
+      - const: ife0
+      - const: ife1
+      - const: ife2
+      - const: top
+
+  ports:
+    $ref: /schemas/graph.yaml#/properties/ports
+
+    description:
+      CSI input ports.
+
+    patternProperties:
+      "^port@[0-5]$":
+        $ref: /schemas/graph.yaml#/$defs/port-base
+        unevaluatedProperties: false
+
+        description:
+          Input port for receiving CSI data from a CSIPHY device.
+
+        properties:
+          endpoint:
+            $ref: video-interfaces.yaml#
+            unevaluatedProperties: false
+
+            properties:
+              data-lanes:
+                minItems: 1
+                maxItems: 4
+
+required:
+  - compatible
+  - reg
+  - reg-names
+  - clocks
+  - clock-names
+  - interconnects
+  - interconnect-names
+  - interrupts
+  - interrupt-names
+  - iommus
+  - power-domains
+  - power-domain-names
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/qcom,gcc-sm8350.h>
+    #include <dt-bindings/clock/qcom,sm8350-camcc.h>
+    #include <dt-bindings/interconnect/qcom,sm8350.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    soc {
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        isp@acb4000 {
+            compatible = "qcom,sm8350-camss";
+            reg = <0 0xacb4000 0 0xd000>,
+                  <0 0xacc3000 0 0xd000>,
+                  <0 0xacef000 0 0xd000>,
+                  <0 0xacd9000 0 0x2200>,
+                  <0 0xacdb200 0 0x2200>;
+            reg-names = "vfe0",
+                        "vfe1",
+                        "vfe2",
+                        "vfe_lite0",
+                        "vfe_lite1";
+            clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
+                     <&camcc CAM_CC_CPAS_AHB_CLK>,
+                     <&gcc GCC_CAMERA_HF_AXI_CLK>,
+                     <&camcc CAM_CC_IFE_0_CLK>,
+                     <&camcc CAM_CC_IFE_0_AHB_CLK>,
+                     <&camcc CAM_CC_IFE_0_AREG_CLK>,
+                     <&camcc CAM_CC_IFE_0_AXI_CLK>,
+                     <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
+                     <&camcc CAM_CC_IFE_0_CSID_CLK>,
+                     <&camcc CAM_CC_IFE_1_CLK>,
+                     <&camcc CAM_CC_IFE_1_AHB_CLK>,
+                     <&camcc CAM_CC_IFE_1_AREG_CLK>,
+                     <&camcc CAM_CC_IFE_1_AXI_CLK>,
+                     <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
+                     <&camcc CAM_CC_IFE_1_CSID_CLK>,
+                     <&camcc CAM_CC_IFE_2_CLK>,
+                     <&camcc CAM_CC_IFE_2_AHB_CLK>,
+                     <&camcc CAM_CC_IFE_2_AREG_CLK>,
+                     <&camcc CAM_CC_IFE_2_AXI_CLK>,
+                     <&camcc CAM_CC_IFE_2_CPHY_RX_CLK>,
+                     <&camcc CAM_CC_IFE_2_CSID_CLK>,
+                     <&camcc CAM_CC_IFE_LITE_CLK>,
+                     <&camcc CAM_CC_IFE_LITE_AHB_CLK>,
+                     <&camcc CAM_CC_IFE_LITE_AXI_CLK>,
+                     <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
+                     <&camcc CAM_CC_IFE_LITE_CSID_CLK>;
+            clock-names = "camnoc_axi",
+                          "cpas_ahb",
+                          "gcc_hf_axi",
+                          "vfe0",
+                          "vfe0_ahb",
+                          "vfe0_areg",
+                          "vfe0_axi",
+                          "vfe0_cphy_rx",
+                          "vfe0_csid",
+                          "vfe1",
+                          "vfe1_ahb",
+                          "vfe1_areg",
+                          "vfe1_axi",
+                          "vfe1_cphy_rx",
+                          "vfe1_csid",
+                          "vfe2",
+                          "vfe2_ahb",
+                          "vfe2_areg",
+                          "vfe2_axi",
+                          "vfe2_cphy_rx",
+                          "vfe2_csid",
+                          "vfe_lite",
+                          "vfe_lite_ahb",
+                          "vfe_lite_axi",
+                          "vfe_lite_cphy_rx",
+                          "vfe_lite_csid";
+            interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 640 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 641 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>;
+            interrupt-names = "csid0",
+                              "csid1",
+                              "csid2",
+                              "csid_lite0",
+                              "csid_lite1",
+                              "vfe0",
+                              "vfe1",
+                              "vfe2",
+                              "vfe_lite0",
+                              "vfe_lite1";
+            interconnects = <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_CAMERA_CFG 0>,
+                            <&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_EBI1 0>;
+            interconnect-names = "ahb", "hf_mnoc";
+            iommus = <&apps_smmu 0x800 0x440>;
+            power-domains = <&camcc IFE_0_GDSC>,
+                            <&camcc IFE_1_GDSC>,
+                            <&camcc IFE_2_GDSC>,
+                            <&camcc TITAN_TOP_GDSC>;
+            power-domain-names = "ife0", "ife1", "ife2", "top";
+
+            ports {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                port@1 {
+                    reg = <1>;
+
+                    camss_csiphy1_ep: endpoint {
+                        remote-endpoint = <&csiphy1_out>;
+                    };
+                };
+            };
+        };
+    };
-- 
2.51.0

[PATCH 2/4] media: qcom: camss: Select Titan 480 CSID offset by VFE type

[Vladimir Zapolskiy]

On Titan 480 CSID register spaces are placed inside VFE register spaces,
and the offset of CSID registers differs between VFE and VFE lite blocks.

Instead of the assumption that all VFEs starting from the third one are
VFE lite blocks, check the VFE type in the platform VFE resources.

Signed-off-by: Vladimir Zapolskiy <vz@kernel.org>
---
 drivers/media/platform/qcom/camss/camss-csid.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/media/platform/qcom/camss/camss-csid.c b/drivers/media/platform/qcom/camss/camss-csid.c
index a00791b00feb..9e64e8d44926 100644
--- a/drivers/media/platform/qcom/camss/camss-csid.c
+++ b/drivers/media/platform/qcom/camss/camss-csid.c
@@ -1119,7 +1119,7 @@ int msm_csid_subdev_init(struct camss *camss, struct csid_device *csid,
 		 * between the VFE "top" and "bus" registers. this requires
 		 * VFE to be initialized before CSID
 		 */
-		if (id >= 2) /* VFE/CSID lite */
+		if (camss->res->vfe_res[id].vfe.is_lite)
 			csid->base = csid->res->parent_dev_ops->get_base_address(camss, id)
 				+ VFE_480_LITE_CSID_OFFSET;
 		else
-- 
2.51.0

[PATCH 3/4] media: qcom: camss: Add SM8350 CAMSS support

[Vladimir Zapolskiy]

Add support of the camera subsystem found on Qualcomm SM8350 SoC.

The CAMSS IP on SM8350 contains:
* three CSID and two CSID lite blocks, which are supported by CSID gen2,
* three VFE and two VFE lite blocks, which are supported by VFE 480.

Every CSID and CSID lite block contains a CSI2 test pattern generator,
which is supported by CSID gen2 and controlled by the CSID subdevice
test pattern control.

SM8350 CSID and VFE blocks are known as version 580, the hardware is
programmed in the same way as Titan 480 found on SM8250, in particular
CSID register spaces are placed inside VFE register spaces.

Qualcomm SM8350 CSIPHYs are supported by the CSI2 PHY driver only.

Signed-off-by: Vladimir Zapolskiy <vz@kernel.org>
---
 .../media/platform/qcom/camss/camss-csid.c    |   3 +-
 drivers/media/platform/qcom/camss/camss-vfe.c |   2 +
 drivers/media/platform/qcom/camss/camss.c     | 213 ++++++++++++++++++
 drivers/media/platform/qcom/camss/camss.h     |   1 +
 4 files changed, 218 insertions(+), 1 deletion(-)

diff --git a/drivers/media/platform/qcom/camss/camss-csid.c b/drivers/media/platform/qcom/camss/camss-csid.c
index 9e64e8d44926..800a32b41667 100644
--- a/drivers/media/platform/qcom/camss/camss-csid.c
+++ b/drivers/media/platform/qcom/camss/camss-csid.c
@@ -1114,7 +1114,8 @@ int msm_csid_subdev_init(struct camss *camss, struct csid_device *csid,
 
 	/* Memory */
 
-	if (camss->res->version == CAMSS_8250) {
+	if (camss->res->version == CAMSS_8250 ||
+	    camss->res->version == CAMSS_8350) {
 		/* for titan 480, CSID registers are inside the VFE region,
 		 * between the VFE "top" and "bus" registers. this requires
 		 * VFE to be initialized before CSID
diff --git a/drivers/media/platform/qcom/camss/camss-vfe.c b/drivers/media/platform/qcom/camss/camss-vfe.c
index 2680a9914765..dcebbfc97441 100644
--- a/drivers/media/platform/qcom/camss/camss-vfe.c
+++ b/drivers/media/platform/qcom/camss/camss-vfe.c
@@ -349,6 +349,7 @@ static u32 vfe_src_pad_code(struct vfe_line *line, u32 sink_code,
 	case CAMSS_8250:
 	case CAMSS_8280XP:
 	case CAMSS_8300:
+	case CAMSS_8350:
 	case CAMSS_845:
 	case CAMSS_8550:
 	case CAMSS_8650:
@@ -2009,6 +2010,7 @@ static int vfe_bpl_align_rdi(struct vfe_device *vfe)
 	case CAMSS_8250:
 	case CAMSS_8280XP:
 	case CAMSS_8300:
+	case CAMSS_8350:
 	case CAMSS_845:
 	case CAMSS_8550:
 	case CAMSS_8650:
diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c
index c54185c93a8a..0bca61b630d4 100644
--- a/drivers/media/platform/qcom/camss/camss.c
+++ b/drivers/media/platform/qcom/camss/camss.c
@@ -2242,6 +2242,206 @@ static const struct resources_icc icc_res_sm8250[] = {
 	},
 };
 
+static const struct camss_subdev_resources csid_res_sm8350[] = {
+	/* CSID0 */
+	{
+		.regulators = {},
+		.clock = { "cpas_ahb", "vfe0_areg", "vfe0_csid", "vfe0_cphy_rx" },
+		.clock_rate = { { 80000000 },
+				{ 100000000, 200000000, 300000000, 400000000 },
+				{ 400000000 },
+				{ 400000000 } },
+		.reg = { "csid0" },
+		.interrupt = { "csid0" },
+		.csid = {
+			.hw_ops = &csid_ops_gen2,
+			.parent_dev_ops = &vfe_parent_dev_ops,
+			.formats = &csid_formats_gen2
+		}
+	},
+	/* CSID1 */
+	{
+		.regulators = {},
+		.clock = { "cpas_ahb", "vfe1_areg", "vfe1_csid", "vfe1_cphy_rx" },
+		.clock_rate = { { 80000000 },
+				{ 100000000, 200000000, 300000000, 400000000 },
+				{ 400000000 },
+				{ 400000000 } },
+		.reg = { "csid1" },
+		.interrupt = { "csid1" },
+		.csid = {
+			.hw_ops = &csid_ops_gen2,
+			.parent_dev_ops = &vfe_parent_dev_ops,
+			.formats = &csid_formats_gen2
+		}
+	},
+	/* CSID2 */
+	{
+		.regulators = {},
+		.clock = { "cpas_ahb", "vfe2_areg", "vfe2_csid", "vfe2_cphy_rx" },
+		.clock_rate = { { 80000000 },
+				{ 100000000, 200000000, 300000000, 400000000 },
+				{ 400000000 },
+				{ 400000000 } },
+		.reg = { "csid2" },
+		.interrupt = { "csid2" },
+		.csid = {
+			.hw_ops = &csid_ops_gen2,
+			.parent_dev_ops = &vfe_parent_dev_ops,
+			.formats = &csid_formats_gen2
+		}
+	},
+	/* CSID_LITE0 */
+	{
+		.regulators = {},
+		.clock = { "cpas_ahb", "vfe_lite_csid", "vfe_lite_cphy_rx" },
+		.clock_rate = { { 80000000 },
+				{ 400000000 },
+				{ 400000000 } },
+		.reg = { "csid_lite0" },
+		.interrupt = { "csid_lite0" },
+		.csid = {
+			.is_lite = true,
+			.hw_ops = &csid_ops_gen2,
+			.parent_dev_ops = &vfe_parent_dev_ops,
+			.formats = &csid_formats_gen2
+		}
+	},
+	/* CSID_LITE1 */
+	{
+		.regulators = {},
+		.clock = { "cpas_ahb", "vfe_lite_csid", "vfe_lite_cphy_rx" },
+		.clock_rate = { { 80000000 },
+				{ 400000000 },
+				{ 400000000 } },
+		.reg = { "csid_lite1" },
+		.interrupt = { "csid_lite1" },
+		.csid = {
+			.is_lite = true,
+			.hw_ops = &csid_ops_gen2,
+			.parent_dev_ops = &vfe_parent_dev_ops,
+			.formats = &csid_formats_gen2
+		}
+	}
+};
+
+static const struct camss_subdev_resources vfe_res_sm8350[] = {
+	/* VFE0 */
+	{
+		.regulators = {},
+		.clock = { "camnoc_axi", "cpas_ahb", "vfe0_ahb", "vfe0_areg",
+			   "vfe0", "vfe0_axi" },
+		.clock_rate = { { 300000000, 400000000 },
+				{ 0 },
+				{ 0 },
+				{ 0 },
+				{ 338000000, 475000000, 600000000, 720000000 },
+				{ 0 } },
+		.reg = { "vfe0" },
+		.interrupt = { "vfe0" },
+		.vfe = {
+			.line_num = 3,
+			.pd_name = "ife0",
+			.hw_ops = &vfe_ops_480,
+			.formats_rdi = &vfe_formats_rdi_845,
+			.formats_pix = &vfe_formats_pix_845
+		}
+	},
+	/* VFE1 */
+	{
+		.regulators = {},
+		.clock = { "camnoc_axi", "cpas_ahb", "vfe1_ahb", "vfe1_areg",
+			   "vfe1", "vfe1_axi" },
+		.clock_rate = { { 300000000, 400000000 },
+				{ 0 },
+				{ 0 },
+				{ 0 },
+				{ 338000000, 475000000, 600000000, 720000000 },
+				{ 0 } },
+		.reg = { "vfe1" },
+		.interrupt = { "vfe1" },
+		.vfe = {
+			.line_num = 3,
+			.pd_name = "ife1",
+			.hw_ops = &vfe_ops_480,
+			.formats_rdi = &vfe_formats_rdi_845,
+			.formats_pix = &vfe_formats_pix_845
+		}
+	},
+	/* VFE2 */
+	{
+		.regulators = {},
+		.clock = { "camnoc_axi", "cpas_ahb", "vfe2_ahb", "vfe2_areg",
+			   "vfe2", "vfe2_axi" },
+		.clock_rate = { { 300000000, 400000000 },
+				{ 0 },
+				{ 0 },
+				{ 0 },
+				{ 338000000, 475000000, 600000000, 720000000 },
+				{ 0 } },
+		.reg = { "vfe2" },
+		.interrupt = { "vfe2" },
+		.vfe = {
+			.line_num = 3,
+			.pd_name = "ife2",
+			.hw_ops = &vfe_ops_480,
+			.formats_rdi = &vfe_formats_rdi_845,
+			.formats_pix = &vfe_formats_pix_845
+		}
+	},
+	/* VFE_LITE0 */
+	{
+		.regulators = {},
+		.clock = { "camnoc_axi", "cpas_ahb", "vfe_lite_ahb",
+			   "vfe_lite" },
+		.clock_rate = { { 300000000, 400000000 },
+				{ 0 },
+				{ 0 },
+				{ 400000000, 480000000 } },
+		.reg = { "vfe_lite0" },
+		.interrupt = { "vfe_lite0" },
+		.vfe = {
+			.is_lite = true,
+			.line_num = 4,
+			.hw_ops = &vfe_ops_480,
+			.formats_rdi = &vfe_formats_rdi_845,
+			.formats_pix = &vfe_formats_pix_845
+		}
+	},
+	/* VFE_LITE1 */
+	{
+		.regulators = {},
+		.clock = { "camnoc_axi", "cpas_ahb", "vfe_lite_ahb",
+			   "vfe_lite" },
+		.clock_rate = { { 300000000, 400000000 },
+				{ 0 },
+				{ 0 },
+				{ 400000000, 480000000 } },
+		.reg = { "vfe_lite1" },
+		.interrupt = { "vfe_lite1" },
+		.vfe = {
+			.is_lite = true,
+			.line_num = 4,
+			.hw_ops = &vfe_ops_480,
+			.formats_rdi = &vfe_formats_rdi_845,
+			.formats_pix = &vfe_formats_pix_845
+		}
+	}
+};
+
+static const struct resources_icc icc_res_sm8350[] = {
+	{
+		.name = "ahb",
+		.icc_bw_tbl.avg = 38400,
+		.icc_bw_tbl.peak = 76800,
+	},
+	{
+		.name = "hf_mnoc",
+		.icc_bw_tbl.avg = 2097152,
+		.icc_bw_tbl.peak = 2097152,
+	},
+};
+
 static const struct camss_subdev_resources csiphy_res_7280[] = {
 	/* CSIPHY0 */
 	{
@@ -5738,6 +5938,18 @@ static const struct camss_resources sm8250_resources = {
 	.vfe_num = ARRAY_SIZE(vfe_res_8250),
 };
 
+static const struct camss_resources sm8350_resources = {
+	.version = CAMSS_8350,
+	.pd_name = "top",
+	.csid_res = csid_res_sm8350,
+	.vfe_res = vfe_res_sm8350,
+	.icc_res = icc_res_sm8350,
+	.icc_path_num = ARRAY_SIZE(icc_res_sm8350),
+	.csiphy_num = 6,
+	.csid_num = ARRAY_SIZE(csid_res_sm8350),
+	.vfe_num = ARRAY_SIZE(vfe_res_sm8350),
+};
+
 static const struct camss_resources sc8280xp_resources = {
 	.version = CAMSS_8280XP,
 	.pd_name = "top",
@@ -5825,6 +6037,7 @@ static const struct of_device_id camss_dt_match[] = {
 	{ .compatible = "qcom,sm6150-camss", .data = &sm6150_resources },
 	{ .compatible = "qcom,sm6350-camss", .data = &sm6350_resources },
 	{ .compatible = "qcom,sm8250-camss", .data = &sm8250_resources },
+	{ .compatible = "qcom,sm8350-camss", .data = &sm8350_resources },
 	{ .compatible = "qcom,sm8550-camss", .data = &sm8550_resources },
 	{ .compatible = "qcom,sm8650-camss", .data = &sm8650_resources },
 	{ .compatible = "qcom,x1e80100-camss", .data = &x1e80100_resources },
diff --git a/drivers/media/platform/qcom/camss/camss.h b/drivers/media/platform/qcom/camss/camss.h
index 7dc2fd9f03e0..aa722e68450b 100644
--- a/drivers/media/platform/qcom/camss/camss.h
+++ b/drivers/media/platform/qcom/camss/camss.h
@@ -92,6 +92,7 @@ enum camss_version {
 	CAMSS_8250,
 	CAMSS_8280XP,
 	CAMSS_8300,
+	CAMSS_8350,
 	CAMSS_845,
 	CAMSS_8550,
 	CAMSS_8650,
-- 
2.51.0

[PATCH 4/4] arm64: dts: qcom: sm8350: Add CAMSS device tree node

[Vladimir Zapolskiy]

Add Qualcomm SM8350 CAMSS device tree node to the platform dtsi file.

The CAMSS input ports will be described along with adding CSIPHY
device tree nodes, which are connected to them.

Signed-off-by: Vladimir Zapolskiy <vz@kernel.org>
---
 arch/arm64/boot/dts/qcom/sm8350.dtsi | 110 +++++++++++++++++++++++++++
 1 file changed, 110 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index a51942c99f8a..9488b8578359 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -10,6 +10,7 @@
 #include <dt-bindings/clock/qcom,gcc-sm8350.h>
 #include <dt-bindings/clock/qcom,gpucc-sm8350.h>
 #include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/clock/qcom,sm8350-camcc.h>
 #include <dt-bindings/clock/qcom,sm8350-videocc.h>
 #include <dt-bindings/dma/qcom-gpi.h>
 #include <dt-bindings/firmware/qcom,scm.h>
@@ -2830,6 +2831,115 @@ videocc: clock-controller@abf0000 {
 			#power-domain-cells = <1>;
 		};
 
+		camss: isp@acb4000 {
+			compatible = "qcom,sm8350-camss";
+
+			reg = <0 0x0acb4000 0 0xd000>,
+			      <0 0x0acc3000 0 0xd000>,
+			      <0 0x0acef000 0 0xd000>,
+			      <0 0x0acd9000 0 0x2200>,
+			      <0 0x0acdb200 0 0x2200>;
+			reg-names = "vfe0",
+				    "vfe1",
+				    "vfe2",
+				    "vfe_lite0",
+				    "vfe_lite1";
+
+			clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
+				 <&camcc CAM_CC_CPAS_AHB_CLK>,
+				 <&gcc GCC_CAMERA_HF_AXI_CLK>,
+				 <&camcc CAM_CC_IFE_0_CLK>,
+				 <&camcc CAM_CC_IFE_0_AHB_CLK>,
+				 <&camcc CAM_CC_IFE_0_AREG_CLK>,
+				 <&camcc CAM_CC_IFE_0_AXI_CLK>,
+				 <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
+				 <&camcc CAM_CC_IFE_0_CSID_CLK>,
+				 <&camcc CAM_CC_IFE_1_CLK>,
+				 <&camcc CAM_CC_IFE_1_AHB_CLK>,
+				 <&camcc CAM_CC_IFE_1_AREG_CLK>,
+				 <&camcc CAM_CC_IFE_1_AXI_CLK>,
+				 <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
+				 <&camcc CAM_CC_IFE_1_CSID_CLK>,
+				 <&camcc CAM_CC_IFE_2_CLK>,
+				 <&camcc CAM_CC_IFE_2_AHB_CLK>,
+				 <&camcc CAM_CC_IFE_2_AREG_CLK>,
+				 <&camcc CAM_CC_IFE_2_AXI_CLK>,
+				 <&camcc CAM_CC_IFE_2_CPHY_RX_CLK>,
+				 <&camcc CAM_CC_IFE_2_CSID_CLK>,
+				 <&camcc CAM_CC_IFE_LITE_CLK>,
+				 <&camcc CAM_CC_IFE_LITE_AHB_CLK>,
+				 <&camcc CAM_CC_IFE_LITE_AXI_CLK>,
+				 <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
+				 <&camcc CAM_CC_IFE_LITE_CSID_CLK>;
+			clock-names = "camnoc_axi",
+				      "cpas_ahb",
+				      "gcc_hf_axi",
+				      "vfe0",
+				      "vfe0_ahb",
+				      "vfe0_areg",
+				      "vfe0_axi",
+				      "vfe0_cphy_rx",
+				      "vfe0_csid",
+				      "vfe1",
+				      "vfe1_ahb",
+				      "vfe1_areg",
+				      "vfe1_axi",
+				      "vfe1_cphy_rx",
+				      "vfe1_csid",
+				      "vfe2",
+				      "vfe2_ahb",
+				      "vfe2_areg",
+				      "vfe2_axi",
+				      "vfe2_cphy_rx",
+				      "vfe2_csid",
+				      "vfe_lite",
+				      "vfe_lite_ahb",
+				      "vfe_lite_axi",
+				      "vfe_lite_cphy_rx",
+				      "vfe_lite_csid";
+
+			interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 640 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 641 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "csid0",
+					  "csid1",
+					  "csid2",
+					  "csid_lite0",
+					  "csid_lite1",
+					  "vfe0",
+					  "vfe1",
+					  "vfe2",
+					  "vfe_lite0",
+					  "vfe_lite1";
+
+			interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+					 &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
+					<&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS
+					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+			interconnect-names = "ahb",
+					     "hf_mnoc";
+
+			iommus = <&apps_smmu 0x800 0x440>;
+
+			power-domains = <&camcc IFE_0_GDSC>,
+					<&camcc IFE_1_GDSC>,
+					<&camcc IFE_2_GDSC>,
+					<&camcc TITAN_TOP_GDSC>;
+			power-domain-names = "ife0",
+					     "ife1",
+					     "ife2",
+					     "top";
+
+			status = "disabled";
+		};
+
 		camcc: clock-controller@ad00000 {
 			compatible = "qcom,sm8350-camcc";
 			reg = <0 0x0ad00000 0 0x10000>;
-- 
2.51.0

Re: [PATCH 2/4] media: qcom: camss: Select Titan 480 CSID offset by VFE type

[Bryan O'Donoghue]

On 04/11/2026 23:45, Vladimir Zapolskiy wrote:
> On Titan 480 CSID register spaces are placed inside VFE register spaces,
> and the offset of CSID registers differs between VFE and VFE lite blocks.
> 
> Instead of the assumption that all VFEs starting from the third one are
> VFE lite blocks, check the VFE type in the platform VFE resources.
> 
> Signed-off-by: Vladimir Zapolskiy <vz@kernel.org>
> ---
>   drivers/media/platform/qcom/camss/camss-csid.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/media/platform/qcom/camss/camss-csid.c b/drivers/media/platform/qcom/camss/camss-csid.c
> index a00791b00feb..9e64e8d44926 100644
> --- a/drivers/media/platform/qcom/camss/camss-csid.c
> +++ b/drivers/media/platform/qcom/camss/camss-csid.c
> @@ -1119,7 +1119,7 @@ int msm_csid_subdev_init(struct camss *camss, struct csid_device *csid,
>   		 * between the VFE "top" and "bus" registers. this requires
>   		 * VFE to be initialized before CSID
>   		 */
> -		if (id >= 2) /* VFE/CSID lite */
> +		if (camss->res->vfe_res[id].vfe.is_lite)
>   			csid->base = csid->res->parent_dev_ops->get_base_address(camss, id)
>   				+ VFE_480_LITE_CSID_OFFSET;
>   		else
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

Re: [PATCH 3/4] media: qcom: camss: Add SM8350 CAMSS support

[Bryan O'Donoghue]

On 04/11/2026 23:45, Vladimir Zapolskiy wrote:
> Add support of the camera subsystem found on Qualcomm SM8350 SoC.
> 
> The CAMSS IP on SM8350 contains:
> * three CSID and two CSID lite blocks, which are supported by CSID gen2,
> * three VFE and two VFE lite blocks, which are supported by VFE 480.
> 
> Every CSID and CSID lite block contains a CSI2 test pattern generator,
> which is supported by CSID gen2 and controlled by the CSID subdevice
> test pattern control.
> 
> SM8350 CSID and VFE blocks are known as version 580, the hardware is
> programmed in the same way as Titan 480 found on SM8250, in particular
> CSID register spaces are placed inside VFE register spaces.
> 
> Qualcomm SM8350 CSIPHYs are supported by the CSI2 PHY driver only.
> 
> Signed-off-by: Vladimir Zapolskiy <vz@kernel.org>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

Re: [PATCH 1/4] dt-bindings: media: Add Qualcomm SM8350 CAMSS

[Bryan O'Donoghue]

On 04/11/2026 23:45, Vladimir Zapolskiy wrote:
> Add device tree bindings documentation of Qualcomm SM8350 camera
> subsystem.
> 
> Qualcomm SM8350 CAMSS contains:
> * three CSID and two CSID lite blocks,
> * three VFE and two VFE lite blocks,
> * six CSIPHY devices are described as separate CSI2 PHY devices.
> 
> The SM8350 CAMSS is very similar to the previous generation SM8250 CAMSS,
> CSID register spaces are placed inside VFE register spaces.
> 
> Signed-off-by: Vladimir Zapolskiy <vz@kernel.org>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

Re: [PATCH 4/4] arm64: dts: qcom: sm8350: Add CAMSS device tree node

[Bryan O'Donoghue]

On 04/11/2026 23:45, Vladimir Zapolskiy wrote:
> Add Qualcomm SM8350 CAMSS device tree node to the platform dtsi file.
> 
> The CAMSS input ports will be described along with adding CSIPHY
> device tree nodes, which are connected to them.
> 
> Signed-off-by: Vladimir Zapolskiy <vz@kernel.org>
Missing ports {}

---
bod

Re: [PATCH 1/4] dt-bindings: media: Add Qualcomm SM8350 CAMSS

[Krzysztof Kozlowski]

On Thu, Nov 05, 2026 at 01:45:30AM +0200, Vladimir Zapolskiy wrote:
> Add device tree bindings documentation of Qualcomm SM8350 camera
> subsystem.
> 
> Qualcomm SM8350 CAMSS contains:
> * three CSID and two CSID lite blocks,
> * three VFE and two VFE lite blocks,
> * six CSIPHY devices are described as separate CSI2 PHY devices.
> 
> The SM8350 CAMSS is very similar to the previous generation SM8250 CAMSS,
> CSID register spaces are placed inside VFE register spaces.
> 
> Signed-off-by: Vladimir Zapolskiy <vz@kernel.org>
> ---
>  .../bindings/media/qcom,sm8350-camss.yaml     | 262 ++++++++++++++++++
>  1 file changed, 262 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/media/qcom,sm8350-camss.yaml

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>

Best regards,
Krzysztof