[PATCH v5 0/4] PCI: qcom: add Shikra PCIe and M.2 Wi-Fi/BT support

[PATCH v5 0/4] PCI: qcom: add Shikra PCIe and M.2 Wi-Fi/BT support

[Linghui Wu]

Add PCIe controller support for the Qualcomm Shikra platform and an
overlay for M.2 Key-E Wi-Fi and Bluetooth modules on the Shikra IQS EVK.

The previous overlay revisions depended on PCIe controller and device
tree changes that were only present in the Qualcomm downstream kernel.
Include the required PCIe binding, driver match data and controller/PHY
nodes so the overlay can be reviewed and built against linux-next.

The overlay describes the board variant where hardware rework selects
the M.2 connectivity path instead of the onboard WCN3988 path.

The series has been validated on Shikra hardware.

Changes in v5:
- Rebase the series onto linux-next next-20261111.
- Include the Shikra PCIe binding, driver and DTS prerequisites.
- Make the overlay self-contained on the upstream Shikra device tree.
- Build and validate the base DTB, DTBO and composite DTB.
- Start a new review thread instead of replying to an older revision.

Changes in v4:
- Build a composite DTB to validate that the overlay applies to the base DTB.
- Explain that the product design does not operate the onboard and M.2
  connectivity paths simultaneously.
- Report Bluetooth UART and HCI validation.

Linghui Wu (1):
  arm64: dts: qcom: shikra-iqs: add M.2 Wi-Fi and Bluetooth overlay

Sushrut Shree Trivedi (3):
  dt-bindings: PCI: qcom: document the Shikra PCIe controller
  PCI: qcom: add support for the Shikra PCIe controller
  arm64: dts: qcom: shikra: add PCIe PHY and controller nodes

 .../devicetree/bindings/arm/qcom-soc.yaml     |   1 +
 .../bindings/pci/qcom,pcie-shikra.yaml        | 192 ++++++++++++++++++
 arch/arm64/boot/dts/qcom/Makefile             |   2 +
 .../dts/qcom/shikra-iqs-evk-m2-wifi-bt.dtso   | 122 +++++++++++
 arch/arm64/boot/dts/qcom/shikra.dtsi          | 158 ++++++++++++++
 drivers/pci/controller/dwc/pcie-qcom.c        |   1 +
 6 files changed, 476 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pci/qcom,pcie-shikra.yaml
 create mode 100644 arch/arm64/boot/dts/qcom/shikra-iqs-evk-m2-wifi-bt.dtso


base-commit: aaa2f954c21b205a0bcd0961e5b2be4e82e58455
-- 
2.43.0

[PATCH v5 1/4] dt-bindings: PCI: qcom: document the Shikra PCIe controller

[Linghui Wu]

From: Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com>

Add a dedicated schema for the PCIe controller found on Shikra.

Signed-off-by: Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com>
---
 .../devicetree/bindings/arm/qcom-soc.yaml     |   1 +
 .../bindings/pci/qcom,pcie-shikra.yaml        | 192 ++++++++++++++++++
 2 files changed, 193 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pci/qcom,pcie-shikra.yaml

diff --git a/Documentation/devicetree/bindings/arm/qcom-soc.yaml b/Documentation/devicetree/bindings/arm/qcom-soc.yaml
index 179aadc86a9f..72e0f1a824c6 100644
--- a/Documentation/devicetree/bindings/arm/qcom-soc.yaml
+++ b/Documentation/devicetree/bindings/arm/qcom-soc.yaml
@@ -43,6 +43,7 @@ properties:
         - pattern: "^qcom,sar[0-9]+[a-z]?-.*$"
         - pattern: "^qcom,(sa|sc)8[0-9]+[a-z][a-z]?-.*$"
         - pattern: "^qcom,(eliza|kaanapali|kuno|glymur|hawi|mahua|maili|milos|nord|shikra)-.+$"
+        - const: qcom,pcie-shikra
 
         # Legacy namings - variations of existing patterns/compatibles are OK,
         # but do not add completely new entries to these:
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-shikra.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-shikra.yaml
new file mode 100644
index 000000000000..69463dae9f18
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie-shikra.yaml
@@ -0,0 +1,192 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/qcom,pcie-shikra.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Shikra PCI Express Root Complex
+
+maintainers:
+  - Bjorn Andersson <andersson@kernel.org>
+  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+
+description:
+  Qualcomm Shikra SoC PCIe root complex controller is based on the Synopsys
+  DesignWare PCIe IP.
+
+properties:
+  compatible:
+    const: qcom,pcie-shikra
+
+  reg:
+    minItems: 5
+    maxItems: 6
+
+  reg-names:
+    minItems: 5
+    items:
+      - const: parf # Qualcomm specific registers
+      - const: dbi # DesignWare PCIe registers
+      - const: elbi # External local bus interface registers
+      - const: atu # ATU address space
+      - const: config # PCIe configuration space
+      - const: mhi # MHI registers
+
+  clocks:
+    minItems: 11
+    maxItems: 11
+
+  clock-names:
+    items:
+      - const: aux # Auxiliary clock
+      - const: cfg # Configuration clock
+      - const: bus_master # Master AXI clock
+      - const: bus_slave # Slave AXI clock
+      - const: slave_q2a # Slave Q2A clock
+      - const: sleep # PCIe Sleep clock
+      - const: throttle_core # PCIe throttle core clock
+      - const: throttle_xo # PCIe throttle XO core clock
+      - const: qmip # QMIP PCIe AHB clock
+      - const: ddrss # PCIE MEMNOC clock
+      - const: tile # AXI SYS NoC clock
+
+  interrupts:
+    minItems: 8
+    maxItems: 9
+
+  interrupt-names:
+    minItems: 8
+    items:
+      - const: msi0
+      - const: msi1
+      - const: msi2
+      - const: msi3
+      - const: msi4
+      - const: msi5
+      - const: msi6
+      - const: msi7
+      - const: global
+
+  resets:
+    maxItems: 1
+
+  reset-names:
+    items:
+      - const: pci # PCIe core reset
+
+required:
+  - power-domains
+  - resets
+  - reset-names
+
+allOf:
+  - $ref: qcom,pcie-common.yaml#
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/qcom,shikra-gcc.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/interconnect/qcom,icc.h>
+    #include <dt-bindings/interconnect/qcom,shikra.h>
+
+    soc {
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        pcie: pcie@45e8000 {
+                device_type = "pci";
+                compatible = "qcom,pcie-shikra";
+                reg = <0x0 0x045e8000 0x0 0x3000>,
+                      <0x0 0x60000000 0x0 0xf1d>,
+                      <0x0 0x60000f20 0x0 0xa8>,
+                      <0x0 0x60001000 0x0 0x1000>,
+                      <0x0 0x60100000 0x0 0x100000>,
+                      <0x0 0x045eb000 0x0 0x1000>;
+                reg-names = "parf",
+                            "dbi",
+                            "elbi",
+                            "atu",
+                            "config",
+                            "mhi";
+                #address-cells = <3>;
+                #size-cells = <2>;
+                ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
+                         <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
+                bus-range = <0x00 0xff>;
+
+                linux,pci-domain = <0>;
+                num-lanes = <1>;
+
+                interrupts = <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH 0>,
+                             <GIC_SPI 492 IRQ_TYPE_LEVEL_HIGH 0>,
+                             <GIC_SPI 493 IRQ_TYPE_LEVEL_HIGH 0>,
+                             <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH 0>,
+                             <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>,
+                             <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH 0>,
+                             <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH 0>,
+                             <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH 0>,
+                             <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH 0>;
+                interrupt-names = "msi0",
+                                  "msi1",
+                                  "msi2",
+                                  "msi3",
+                                  "msi4",
+                                  "msi5",
+                                  "msi6",
+                                  "msi7",
+                                  "global";
+
+                #interrupt-cells = <1>;
+                interrupt-map-mask = <0 0 0 0x7>;
+                interrupt-map = <0 0 0 1 &intc GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH 0>,
+                                <0 0 0 2 &intc GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH 0>,
+                                <0 0 0 3 &intc GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH 0>,
+                                <0 0 0 4 &intc GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH 0>;
+
+                clocks = <&gcc GCC_PCIE_AUX_CLK>,
+                         <&gcc GCC_PCIE_CFG_AHB_CLK>,
+                         <&gcc GCC_PCIE_MSTR_AXI_CLK>,
+                         <&gcc GCC_PCIE_SLV_AXI_CLK>,
+                         <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>,
+                         <&gcc GCC_PCIE_SLEEP_CLK>,
+                         <&gcc GCC_PCIE_THROTTLE_CORE_CLK>,
+                         <&gcc GCC_PCIE_THROTTLE_XO_CLK>,
+                         <&gcc GCC_QMIP_PCIE_CFG_AHB_CLK>,
+                         <&gcc GCC_DDRSS_MEMNOC_PCIE_SF_CLK>,
+                         <&gcc GCC_PCIE_TILE_AXI_SYS_NOC_CLK>;
+
+                clock-names = "aux",
+                              "cfg",
+                              "bus_master",
+                              "bus_slave",
+                              "slave_q2a",
+                              "sleep",
+                              "throttle_core",
+                              "throttle_xo",
+                              "qmip",
+                              "ddrss",
+                              "tile";
+                assigned-clocks = <&gcc GCC_PCIE_AUX_CLK>;
+                assigned-clock-rates = <19200000>;
+
+                interconnects = <&system_noc MASTER_PCIE2_0 QCOM_ICC_TAG_ALWAYS
+                                &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>,
+                                <&mem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
+                                &config_noc SLAVE_PCIE2_0 QCOM_ICC_TAG_ACTIVE_ONLY>;
+
+                interconnect-names = "pcie-mem", "cpu-pcie";
+
+                iommu-map = <0x0 &apps_smmu 0x800 0x1>,
+                            <0x100 &apps_smmu 0x801 0x1>;
+
+                resets = <&gcc GCC_PCIE_BCR>;
+                reset-names = "pci";
+
+                power-domains = <&gcc GCC_PCIE_GDSC>;
+
+                max-link-speed = <2>;
+        };
+
+    };
-- 
2.43.0

[PATCH v5 2/4] PCI: qcom: add support for the Shikra PCIe controller

[Linghui Wu]

From: Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com>

Add support for the PCIe controller found on the Qualcomm Shikra platform.

Signed-off-by: Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com>
---
 drivers/pci/controller/dwc/pcie-qcom.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index eba1b2cb30f0..7573c509d7ce 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -2623,6 +2623,7 @@ static const struct of_device_id qcom_pcie_match[] = {
 	{ .compatible = "qcom,pcie-sc8280xp", .data = &cfg_sc8280xp },
 	{ .compatible = "qcom,pcie-sdm845", .data = &cfg_2_7_0 },
 	{ .compatible = "qcom,pcie-sdx55", .data = &cfg_1_9_0 },
+	{ .compatible = "qcom,pcie-shikra", .data = &cfg_1_9_0 },
 	{ .compatible = "qcom,pcie-sm8150", .data = &cfg_1_9_0 },
 	{ .compatible = "qcom,pcie-sm8250", .data = &cfg_1_9_0 },
 	{ .compatible = "qcom,pcie-sm8350", .data = &cfg_1_9_0 },
-- 
2.43.0

[PATCH v5 3/4] arm64: dts: qcom: shikra: add PCIe PHY and controller nodes

[Linghui Wu]

From: Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com>

Shikra supports a single PCIe instance with a 5 GT/s x1 lane. Add the
PCIe controller and PHY nodes for this instance.

Signed-off-by: Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/shikra.dtsi | 158 +++++++++++++++++++++++++++
 1 file changed, 158 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi
index 0a95ad5a5582..fa9b0d41a576 100644
--- a/arch/arm64/boot/dts/qcom/shikra.dtsi
+++ b/arch/arm64/boot/dts/qcom/shikra.dtsi
@@ -1285,6 +1285,164 @@ rng: rng@4454000 {
 			reg = <0x0 0x04454000 0x0 0x1000>;
 		};
 
+		pcie: pcie@45e8000 {
+			device_type = "pci";
+			compatible = "qcom,pcie-shikra";
+			reg = <0x0 0x045e8000 0x0 0x3000>,
+			      <0x0 0x60000000 0x0 0xf1d>,
+			      <0x0 0x60000f20 0x0 0xa8>,
+			      <0x0 0x60001000 0x0 0x1000>,
+			      <0x0 0x60100000 0x0 0x100000>,
+			      <0x0 0x045eb000 0x0 0x1000>;
+			reg-names = "parf",
+				    "dbi",
+				    "elbi",
+				    "atu",
+				    "config",
+				    "mhi";
+			#address-cells = <3>;
+			#size-cells = <2>;
+			ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
+				 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
+			bus-range = <0x00 0xff>;
+
+			linux,pci-domain = <0>;
+			num-lanes = <1>;
+
+			interrupts = <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 492 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 493 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH 0>;
+			interrupt-parent = <&intc>;
+			interrupt-names = "msi0",
+					  "msi1",
+					  "msi2",
+					  "msi3",
+					  "msi4",
+					  "msi5",
+					  "msi6",
+					  "msi7",
+					  "global";
+
+			interrupt-map = <0 0 0 1 &intc 0 0 0 499 IRQ_TYPE_LEVEL_HIGH>,
+					<0 0 0 2 &intc 0 0 0 500 IRQ_TYPE_LEVEL_HIGH>,
+					<0 0 0 3 &intc 0 0 0 501 IRQ_TYPE_LEVEL_HIGH>,
+					<0 0 0 4 &intc 0 0 0 502 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-map-mask = <0 0 0 0x7>;
+			#interrupt-cells = <1>;
+
+			clocks = <&gcc GCC_PCIE_AUX_CLK>,
+				 <&gcc GCC_PCIE_CFG_AHB_CLK>,
+				 <&gcc GCC_PCIE_MSTR_AXI_CLK>,
+				 <&gcc GCC_PCIE_SLV_AXI_CLK>,
+				 <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>,
+				 <&gcc GCC_PCIE_SLEEP_CLK>,
+				 <&gcc GCC_PCIE_THROTTLE_CORE_CLK>,
+				 <&gcc GCC_PCIE_THROTTLE_XO_CLK>,
+				 <&gcc GCC_QMIP_PCIE_CFG_AHB_CLK>,
+				 <&gcc GCC_DDRSS_MEMNOC_PCIE_SF_CLK>,
+				 <&gcc GCC_PCIE_TILE_AXI_SYS_NOC_CLK>;
+
+			clock-names = "aux",
+				      "cfg",
+				      "bus_master",
+				      "bus_slave",
+				      "slave_q2a",
+				      "sleep",
+				      "throttle_core",
+				      "throttle_xo",
+				      "qmip",
+				      "ddrss",
+				      "tile";
+			assigned-clocks = <&gcc GCC_PCIE_AUX_CLK>;
+			assigned-clock-rates = <19200000>;
+
+			interconnects = <&system_noc MASTER_PCIE2_0 QCOM_ICC_TAG_ALWAYS
+					&mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>,
+					<&mem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
+					&config_noc SLAVE_PCIE2_0 QCOM_ICC_TAG_ACTIVE_ONLY>;
+
+			interconnect-names = "pcie-mem",
+					     "cpu-pcie";
+
+			iommu-map = <0x0 &apps_smmu 0x800 0x1>,
+				    <0x100 &apps_smmu 0x801 0x1>;
+
+			resets = <&gcc GCC_PCIE_BCR>;
+			reset-names = "pci";
+
+			power-domains = <&gcc GCC_PCIE_GDSC>;
+
+			max-link-speed = <2>;
+
+			operating-points-v2 = <&pcie_opp_table>;
+
+			status = "disabled";
+
+			pcie_opp_table: opp-table {
+				compatible = "operating-points-v2";
+
+				/* GEN 1 x1 */
+				opp-2500000 {
+					opp-hz = /bits/ 64 <2500000>;
+					required-opps = <&rpmpd_opp_nom>;
+					opp-peak-kBps = <250000 1>;
+					opp-level = <1>;
+				};
+
+				/* GEN 2 x1 */
+				opp-5000000 {
+					opp-hz = /bits/ 64 <5000000>;
+					required-opps = <&rpmpd_opp_nom>;
+					opp-peak-kBps = <500000 1>;
+					opp-level = <2>;
+				};
+			};
+
+			pcie_port0: pcie@0 {
+				device_type = "pci";
+				reg = <0x0 0x0 0x0 0x0 0x0>;
+				#address-cells = <3>;
+				#size-cells = <2>;
+				ranges;
+				bus-range = <0x01 0x8>;
+
+				phys = <&pcie_phy>;
+			};
+		};
+		pcie_phy: phy@45ee000 {
+			compatible = "qcom,shikra-qmp-gen2x1-pcie-phy";
+			reg = <0x0 0x045ee000 0x0 0x1000>;
+
+			clocks = <&gcc GCC_PCIE_AUX_CLK>,
+				 <&gcc GCC_PCIE_CFG_AHB_CLK>,
+				 <&gcc GCC_PCIE_CLKREF_EN>,
+				 <&gcc GCC_PCIE_RCHNG_PHY_CLK>,
+				 <&gcc GCC_PCIE_PIPE_CLK>;
+			clock-names = "aux",
+				      "cfg_ahb",
+				      "ref",
+				      "refgen",
+				      "pipe";
+
+			resets = <&gcc GCC_PCIE_PHY_BCR>;
+			reset-names = "phy";
+
+			assigned-clocks = <&gcc GCC_PCIE_RCHNG_PHY_CLK>;
+			assigned-clock-rates = <100000000>;
+
+			#clock-cells = <0>;
+			clock-output-names = "pcie_pipe_clk";
+
+			#phy-cells = <0>;
+
+			status = "disabled";
+		};
 		rpm_msg_ram: sram@45f0000 {
 			compatible = "qcom,rpm-msg-ram", "mmio-sram";
 			reg = <0x0 0x045f0000 0x0 0x7000>;
-- 
2.43.0

[PATCH v5 4/4] arm64: dts: qcom: shikra-iqs: add M.2 Wi-Fi and Bluetooth overlay

[Linghui Wu]

Add an overlay for M.2 Key-E Wi-Fi and Bluetooth modules on the
Qualcomm Shikra IQS EVK.

The Shikra product design supports either the onboard Apache WCN3988
path or the M.2 HSP Cologne path at a time. The overlay describes the
board after hardware rework selects the M.2 path. Disable the inherited
onboard Wi-Fi and Bluetooth nodes when this overlay is selected.

Describe the PCIe and UART connections through the M.2 connector, the
3.3 V supply, the W_DISABLE signals and the PCIe reset signal.

The series has been validated on Shikra hardware.

Link: https://lore.kernel.org/r/20261102045815.2938940-1-linghui.wu@oss.qualcomm.com
Co-developed-by: Wei Deng <wei.deng@oss.qualcomm.com>
Signed-off-by: Wei Deng <wei.deng@oss.qualcomm.com>
Signed-off-by: Linghui Wu <linghui.wu@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/Makefile             |   2 +
 .../dts/qcom/shikra-iqs-evk-m2-wifi-bt.dtso   | 122 ++++++++++++++++++
 2 files changed, 124 insertions(+)
 create mode 100644 arch/arm64/boot/dts/qcom/shikra-iqs-evk-m2-wifi-bt.dtso

diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index 8329c06b60a3..037dbe8a39ce 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -410,10 +410,12 @@ dtb-$(CONFIG_ARCH_QCOM)	+= shikra-iqs-evk.dtb
 shikra-cqm-evk-imx577-camera-dtbs	:= shikra-cqm-evk.dtb shikra-cqm-cqs-evk-imx577-camera.dtbo
 shikra-cqs-evk-imx577-camera-dtbs	:= shikra-cqs-evk.dtb shikra-cqm-cqs-evk-imx577-camera.dtbo
 shikra-iqs-evk-imx577-camera-dtbs	:= shikra-iqs-evk.dtb shikra-iqs-evk-imx577-camera.dtbo
+shikra-iqs-evk-m2-wifi-bt-dtbs	:= shikra-iqs-evk.dtb shikra-iqs-evk-m2-wifi-bt.dtbo
 
 dtb-$(CONFIG_ARCH_QCOM)	+= shikra-cqm-evk-imx577-camera.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= shikra-cqs-evk-imx577-camera.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= shikra-iqs-evk-imx577-camera.dtb
+dtb-$(CONFIG_ARCH_QCOM)	+= shikra-iqs-evk-m2-wifi-bt.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= sm4250-oneplus-billie2.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= sm4450-qrd.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= sm6115-fxtec-pro1x.dtb
diff --git a/arch/arm64/boot/dts/qcom/shikra-iqs-evk-m2-wifi-bt.dtso b/arch/arm64/boot/dts/qcom/shikra-iqs-evk-m2-wifi-bt.dtso
new file mode 100644
index 000000000000..ef0f197a53f8
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/shikra-iqs-evk-m2-wifi-bt.dtso
@@ -0,0 +1,122 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2026 Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+
+&{/} {
+	m2_keye_3p3: regulator-m2-keye-3p3 {
+		compatible = "regulator-fixed";
+		regulator-name = "VREG_3P3_KEYE";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&expander3 6 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+
+	wifi-bt-connector {
+		compatible = "pcie-m2-e-connector";
+
+		vpcie3v3-supply = <&m2_keye_3p3>;
+		w-disable1-gpios = <&tlmm 61 GPIO_ACTIVE_LOW>;
+		w-disable2-gpios = <&tlmm 60 GPIO_ACTIVE_LOW>;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				m2_e_pcie_ep: endpoint@0 {
+					reg = <0>;
+					remote-endpoint = <&pcie_port0_ep>;
+				};
+			};
+
+			port@3 {
+				reg = <3>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				m2_e_uart_ep: endpoint@0 {
+					reg = <0>;
+					remote-endpoint = <&uart8_ep>;
+				};
+			};
+		};
+	};
+};
+
+&{/wcn3988-pmu} {
+	status = "disabled";
+};
+
+&pcie {
+	iommu-map = <0x0 &apps_smmu 0x0800 0x0 0x1>,
+		    <0x100 &apps_smmu 0x0801 0x0 0x1>;
+	pinctrl-0 = <&pcie_default_state>;
+	pinctrl-names = "default";
+	vddpe-3v3-supply = <&m2_keye_3p3>;
+	wake-gpios = <&tlmm 119 GPIO_ACTIVE_LOW>;
+
+	status = "okay";
+};
+
+&pcie_phy {
+	vdda-phy-supply = <&pm8150_l12>;
+	vdda-pll-supply = <&pm8150_l9>;
+
+	status = "okay";
+};
+
+&pcie_port0 {
+	compatible = "pciclass,0604";
+	reset-gpios = <&tlmm 118 GPIO_ACTIVE_LOW>;
+
+	port {
+		pcie_port0_ep: endpoint {
+			remote-endpoint = <&m2_e_pcie_ep>;
+		};
+	};
+};
+
+&uart8 {
+	bluetooth {
+		status = "disabled";
+	};
+
+	port {
+		uart8_ep: endpoint {
+			remote-endpoint = <&m2_e_uart_ep>;
+		};
+	};
+};
+
+&tlmm {
+	pcie_default_state: pcie-default-state {
+		clkreq-pins {
+			pins = "gpio117";
+			function = "pcie0_clk_req_n";
+			drive-strength = <2>;
+			bias-pull-up;
+		};
+
+		wake-pins {
+			pins = "gpio119";
+			function = "gpio";
+			drive-strength = <2>;
+			bias-pull-up;
+		};
+	};
+};
+
+&wifi {
+	status = "disabled";
+};
-- 
2.43.0

Re: [PATCH v5 2/4] PCI: qcom: add support for the Shikra PCIe controller

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential
issue to consider:
- [Low] PCI: qcom: legacy qcom,pcie-shikra compatible naming in
  qcom_pcie_match
--

commit 929cee16b1f49a3c3c6d6d911e16e73ada7cd7fc
Author: Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com>

PCI: qcom: add support for the Shikra PCIe controller

This commit adds the qcom,pcie-shikra compatible entry to qcom_pcie_match
using cfg_1_9_0.

> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> index eba1b2cb30f0a..7573c509d7ce6 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> @@ -2623,6 +2623,7 @@ static const struct of_device_id qcom_pcie_match[] = {
>  	{ .compatible = "qcom,pcie-sc8280xp", .data = &cfg_sc8280xp },
>  	{ .compatible = "qcom,pcie-sdm845", .data = &cfg_2_7_0 },
>  	{ .compatible = "qcom,pcie-sdx55", .data = &cfg_1_9_0 },
> +	{ .compatible = "qcom,pcie-shikra", .data = &cfg_1_9_0 },

[Severity: Low]
Should this compatible string be "qcom,shikra-pcie" (sorted at the top of
qcom_pcie_match alongside "qcom,hawi-pcie" and "qcom,nord-pcie") instead of
"qcom,pcie-shikra"?

Documentation/devicetree/bindings/arm/qcom-soc.yaml marks qcom,pcie-* as a
legacy pattern that must not be used for new entries and already includes
shikra in the preferred qcom,SoC-IP pattern, so using qcom,pcie-shikra locks
in a non-conforming DT ABI name and required adding a one-off const exception
to qcom-soc.yaml.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261112083355.3884737-1-linghui.wu@oss.qualcomm.com?part=2

Re: [PATCH v5 1/4] dt-bindings: PCI: qcom: document the Shikra PCIe controller

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 4 potential
issues to consider:
- [Low] dt-bindings: PCI: qcom: legacy qcom,IP-SoC compatible order for
  Shikra
- [Low] dt-bindings: PCI: qcom: wrong interconnect slave and tags in
  Shikra example
- [Low] dt-bindings: PCI: qcom: dt-check-style strict violations in
  Shikra example
- [Low] dt-bindings: PCI: qcom: inactive maintainer email in
  qcom,pcie-shikra.yaml
--

commit 283a34a0a4cfab50d007b36100271b61fd8ac267
Author: Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com>

dt-bindings: PCI: qcom: document the Shikra PCIe controller

This commit adds a Devicetree binding schema for the Qualcomm Shikra PCIe
root complex controller and registers its compatible string in
qcom-soc.yaml.

> diff --git a/Documentation/devicetree/bindings/arm/qcom-soc.yaml b/Documentation/devicetree/bindings/arm/qcom-soc.yaml
> index 179aadc86a9f0..72e0f1a824c69 100644
> --- a/Documentation/devicetree/bindings/arm/qcom-soc.yaml
> +++ b/Documentation/devicetree/bindings/arm/qcom-soc.yaml
> @@ -43,6 +43,7 @@ properties:
>          - pattern: "^qcom,sar[0-9]+[a-z]?-.*$"
>          - pattern: "^qcom,(sa|sc)8[0-9]+[a-z][a-z]?-.*$"
>          - pattern: "^qcom,(eliza|kaanapali|kuno|glymur|hawi|mahua|maili|milos|nord|shikra)-.+$"
> +        - const: qcom,pcie-shikra
>  
>          # Legacy namings - variations of existing patterns/compatibles are OK,
>          # but do not add completely new entries to these:

[Severity: Low]
Should this new binding use the qcom,SoC-IP naming order (qcom,shikra-pcie
and qcom,shikra-pcie.yaml) instead of legacy qcom,IP-SoC?

Documentation/devicetree/bindings/arm/qcom-soc.yaml requires new bindings
to use the qcom,SoC-IP format, and the pattern immediately above already
matches qcom,shikra-pcie without needing a one-off exception.  Other Shikra
bindings (such as qcom,shikra-gcc and qcom,shikra-qmp-gen2x1-pcie-phy) and
recent codename PCIe bindings (such as qcom,hawi-pcie and qcom,maili-pcie)
follow this convention.

> diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-shikra.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-shikra.yaml
> new file mode 100644
> index 0000000000000..69463dae9f183
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-shikra.yaml
> @@ -0,0 +1,192 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pci/qcom,pcie-shikra.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm Shikra PCI Express Root Complex
> +
> +maintainers:
> +  - Bjorn Andersson <andersson@kernel.org>
> +  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

[Severity: Low]
Should Manivannan Sadhasivam's email address be mani@kernel.org here?
Commit e3d7fda088c3 ("dt-bindings: PCI: Update the email address for
Manivannan Sadhasivam") replaced the inactive linaro.org address across
the PCI bindings.

[ ... ]

> +examples:
> +  - |
> +    #include <dt-bindings/clock/qcom,shikra-gcc.h>
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +    #include <dt-bindings/interconnect/qcom,icc.h>
> +    #include <dt-bindings/interconnect/qcom,shikra.h>

[ ... ]

> +                interconnects = <&system_noc MASTER_PCIE2_0 QCOM_ICC_TAG_ALWAYS
> +                                &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>,
> +                                <&mem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
> +                                &config_noc SLAVE_PCIE2_0 QCOM_ICC_TAG_ACTIVE_ONLY>;
> +
> +                interconnect-names = "pcie-mem", "cpu-pcie";

[Severity: Low]
Does the cpu-pcie interconnect path point to the wrong slave on config_noc
and use the wrong interconnect tag macros?

In include/dt-bindings/interconnect/qcom,shikra.h, SLAVE_PCIE2_0 (29) is a
system_noc slave ID; on config_noc, index 29 is SLAVE_PKA_WRAPPER_CFG
(&qhs_pka_wrapper in drivers/interconnect/qcom/shikra.c), while the PCIe
config slave on config_noc is SLAVE_PCIE_CFG (26).

In addition, Shikra uses the SMD-RPM interconnect driver
(drivers/interconnect/qcom/icc-rpm.c) and
dt-bindings/interconnect/qcom,rpm-icc.h.  Passing QCOM_ICC_TAG_ACTIVE_ONLY
(0x3) from qcom,icc.h sets both RPM_ACTIVE_TAG (0x1) and RPM_SLEEP_TAG
(0x2), causing qcom_icc_bw_aggregate() to vote for both active and sleep
states instead of active only.

> +
> +                iommu-map = <0x0 &apps_smmu 0x800 0x1>,
> +                            <0x100 &apps_smmu 0x801 0x1>;
> +
> +                resets = <&gcc GCC_PCIE_BCR>;
> +                reset-names = "pci";
> +
> +                power-domains = <&gcc GCC_PCIE_GDSC>;
> +
> +                max-link-speed = <2>;
> +        };
> +
> +    };

[Severity: Low]
The example triggers several scripts/dtc/dt-check-style --mode=strict
warnings:

- pcie@45e8000 has an unused pcie: label.
- Properties inside pcie@45e8000 are indented by 8 spaces instead of 4
  spaces relative to the node, which also pushes several lines past 80
  columns.
- ranges is placed after #address-cells and #size-cells, and standard
  properties such as num-lanes are placed after the vendor-prefixed
  linux,pci-domain property.
- Continuation lines inside interconnects are aligned with the opening '<'
  instead of the first cell value after '<'.
- There is a trailing blank line before the closing brace of the soc node.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261112083355.3884737-1-linghui.wu@oss.qualcomm.com?part=1

Re: [PATCH v5 3/4] arm64: dts: qcom: shikra: add PCIe PHY and controller nodes

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 4 potential
issues to consider:
- [High] arm64: dts: qcom: shikra: missing 4th GIC cell in pcie
  interrupt-map
- [High] arm64: dts: qcom: shikra: wrong slave and ICC tags in pcie
  interconnects
- [High] arm64: dts: qcom: shikra: missing pcie_phy clock phandle in gcc
  node
- [Medium] arm64: dts: qcom: shikra: 1-cell iommu-map entries for 2-cell
  apps_smmu
--

commit 5f4c78a483eb233ec45c85fdfcd5ba4cf541044d
Author: Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com>

arm64: dts: qcom: shikra: add PCIe PHY and controller nodes

This commit adds the PCIe controller and QMP Gen2x1 PHY device tree nodes
for the Qualcomm Shikra SoC.

> diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi
> index 0a95ad5a5582c..fa9b0d41a576c 100644
> --- a/arch/arm64/boot/dts/qcom/shikra.dtsi
> +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi
> @@ -1285,6 +1285,164 @@ rng: rng@4454000 {
>  			reg = <0x0 0x04454000 0x0 0x1000>;
>  		};
>  
> +		pcie: pcie@45e8000 {

[ ... ]

> +			interrupt-map = <0 0 0 1 &intc 0 0 0 499 IRQ_TYPE_LEVEL_HIGH>,
> +					<0 0 0 2 &intc 0 0 0 500 IRQ_TYPE_LEVEL_HIGH>,
> +					<0 0 0 3 &intc 0 0 0 501 IRQ_TYPE_LEVEL_HIGH>,
> +					<0 0 0 4 &intc 0 0 0 502 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-map-mask = <0 0 0 0x7>;
> +			#interrupt-cells = <1>;

[Severity: High]
Are these interrupt-map entries missing the fourth GICv3 interrupt cell?

In shikra.dtsi, &intc declares #address-cells = <2> and
#interrupt-cells = <4> (as used in the interrupts property above).  Each
entry here only provides 5 cells after &intc instead of 6, so
of_irq_parse_imap_parent() consumes the first cell of the next entry and
shifts INTB, INTC, and INTD out of alignment, causing legacy INTx mapping
for those pins to fail with -EINVAL.

[ ... ]

> +			interconnects = <&system_noc MASTER_PCIE2_0 QCOM_ICC_TAG_ALWAYS
> +					&mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>,
> +					<&mem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
> +					&config_noc SLAVE_PCIE2_0 QCOM_ICC_TAG_ACTIVE_ONLY>;
> +
> +			interconnect-names = "pcie-mem",
> +					     "cpu-pcie";

[Severity: High]
Does the cpu-pcie interconnect path point to the wrong slave node and use
RPMh tags on an SMD-RPM platform?

SLAVE_PCIE2_0 (29) is a slave on &system_noc (shikra_sys_noc_nodes),
whereas index 29 in shikra_config_noc_nodes (&config_noc) is
SLAVE_PKA_WRAPPER_CFG, so cpu-pcie votes on qhs_pka_wrapper instead of
PCIe (&system_noc SLAVE_PCIE2_0 or &config_noc SLAVE_PCIE_CFG).  In
addition, Shikra uses the SMD-RPM interconnect driver (icc-rpm.c), where
RPM_ALWAYS_TAG and RPM_ACTIVE_TAG should be used instead of RPMh's
QCOM_ICC_TAG_ALWAYS and QCOM_ICC_TAG_ACTIVE_ONLY (0x3), which sets BIT(1)
and keeps active-only bandwidth voted during system sleep.

> +
> +			iommu-map = <0x0 &apps_smmu 0x800 0x1>,
> +				    <0x100 &apps_smmu 0x801 0x1>;

[Severity: Medium]
Should each iommu-map entry include a second IOMMU specifier cell (such as
<0x0 &apps_smmu 0x800 0x0 0x1>)?

&apps_smmu declares #iommu-cells = <2>, so 4-cell iommu-map entries trigger
runtime warnings in qcom_pcie_config_sid_1_9_0() and of_map_id() as well as
dtbs_check schema errors.

[ ... ]

> +		pcie_phy: phy@45ee000 {

[ ... ]

> +			#clock-cells = <0>;
> +			clock-output-names = "pcie_pipe_clk";
> +
> +			#phy-cells = <0>;
> +
> +			status = "disabled";
> +		};

[Severity: High]
Should the gcc node's clocks property also be updated to reference
<&pcie_phy> at index 6 (DT_PCIE_PIPE_CLK)?

In drivers/clk/qcom/gcc-shikra.c, gcc_pcie_pipe_clk_src resolves its parent
solely through DT index DT_PCIE_PIPE_CLK (6) on &gcc:

drivers/clk/qcom/gcc-shikra.c:
static struct clk_regmap_phy_mux gcc_pcie_pipe_clk_src = {
	.reg = 0xaf058,
	.clkr = {
		.hw.init = &(const struct clk_init_data) {
			.name = "gcc_pcie_pipe_clk_src",
			.parent_data = &(const struct clk_parent_data) {
				.index = DT_PCIE_PIPE_CLK,
			},
			.num_parents = 1,
			.ops = &clk_regmap_phy_mux_ops,
		},
	},
};

Because index 6 of &gcc's clocks property in shikra.dtsi is still <0>,
gcc_pcie_pipe_clk_src and gcc_pcie_pipe_clk remain orphaned and never
parent to pcie_phy's clock provider.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261112083355.3884737-1-linghui.wu@oss.qualcomm.com?part=3

Re: [PATCH v5 4/4] arm64: dts: qcom: shikra-iqs: add M.2 Wi-Fi and Bluetooth overlay

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 5 potential
issues to consider:
- [Medium] arm64: dts: qcom: wake-gpios placed on &pcie host bridge
  instead of &pcie_port0
- [Medium] arm64: dts: qcom: duplicate m2_keye_3p3 supply on &pcie
  bypasses M.2 pwrseq
- [Medium] arm64: dts: qcom: shikra: pcie interrupt-map missing 4th
  GICv3 cell
- [Low] arm64: dts: qcom: shikra-iqs: swapped pcie_phy supplies in M.2
  overlay
- [Low] arm64: dts: qcom: shikra-iqs: redundant iommu-map override in
  M.2 overlay
--

commit 1c809b4232eacddb83a64fcaf6b111c590153326
Author: Linghui Wu <linghui.wu@oss.qualcomm.com>

arm64: dts: qcom: shikra-iqs: add M.2 Wi-Fi and Bluetooth overlay

This commit adds a Device Tree overlay for M.2 Key-E Wi-Fi and Bluetooth
modules on the Qualcomm Shikra IQS EVK and disables the onboard WCN3988
Wi-Fi and Bluetooth nodes when the overlay is applied.

Link: https://lore.kernel.org/r/20261102045815.2938940-1-linghui.wu@oss.qualcomm.com

> diff --git a/arch/arm64/boot/dts/qcom/shikra-iqs-evk-m2-wifi-bt.dtso b/arch/arm64/boot/dts/qcom/shikra-iqs-evk-m2-wifi-bt.dtso
> new file mode 100644
> index 0000000000000..ef0f197a53f85
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/shikra-iqs-evk-m2-wifi-bt.dtso
> @@ -0,0 +1,122 @@

[ ... ]

> +	wifi-bt-connector {
> +		compatible = "pcie-m2-e-connector";
> +
> +		vpcie3v3-supply = <&m2_keye_3p3>;
> +		w-disable1-gpios = <&tlmm 61 GPIO_ACTIVE_LOW>;
> +		w-disable2-gpios = <&tlmm 60 GPIO_ACTIVE_LOW>;

[ ... ]

> +&pcie {
> +	iommu-map = <0x0 &apps_smmu 0x0800 0x0 0x1>,
> +		    <0x100 &apps_smmu 0x0801 0x0 0x1>;

[Severity: Low]
Should this 5-cell iommu-map live in shikra.dtsi instead of being
overridden in this overlay?

In shikra.dtsi (added in commit "arm64: dts: qcom: shikra: add PCIe PHY
and controller nodes"), apps_smmu has #iommu-cells = <2>, but the base
pcie node defines 4-cell iommu-map entries (<0x0 &apps_smmu 0x800 0x1>,
<0x100 &apps_smmu 0x801 0x1>), which triggers the of_check_bad_map()
warning in of_map_id().  Since this overlay maps the exact same BDFs and
SIDs and only supplies the missing second IOMMU specifier cell (0x0),
fixing iommu-map in shikra.dtsi allows dropping this override here.

> +	pinctrl-0 = <&pcie_default_state>;
> +	pinctrl-names = "default";
> +	vddpe-3v3-supply = <&m2_keye_3p3>;

[Severity: Medium]
Does setting vddpe-3v3-supply = <&m2_keye_3p3> on &pcie conflict with
pwrseq-pcie-m2 managing the same rail through wifi-bt-connector's
vpcie3v3-supply?

In qcom_pcie_host_init(), pcie->cfg->ops->init() (qcom_pcie_init_2_7_0())
enables vddpe-3v3-supply before pci_pwrctrl_create_devices() and
pci_pwrctrl_power_on_devices() run:

drivers/pci/controller/dwc/pcie-qcom.c:qcom_pcie_host_init() {
	ret = pcie->cfg->ops->init(pcie);
	if (ret)
		return ret;

	ret = qcom_pcie_phy_power_on(pcie);
	if (ret)
		goto err_deinit;

	if (!pci->suspended) {
		ret = pci_pwrctrl_create_devices(pci->dev);
		if (ret)
			goto err_disable_phy;
	}

	if (!pp->skip_pwrctrl_off) {
		ret = pci_pwrctrl_power_on_devices(pci->dev);
		if (ret)
			goto err_pwrctrl_destroy;
	}
}

This turns on m2_keye_3p3 before the M.2 power sequencer runs, glitches
the 3.3 V rail when qcom_pcie_host_init() unwinds through err_deinit on
an initial -EPROBE_DEFER from pci_pwrctrl_power_on_devices(), and holds an
enable vote on &pcie that prevents pwrseq-pcie-m2 from gating the rail.

> +	wake-gpios = <&tlmm 119 GPIO_ACTIVE_LOW>;

[Severity: Medium]
Should wake-gpios be placed on &pcie_port0 rather than on the &pcie host
bridge node?

Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml marks
wake-gpios on the host bridge node as deprecated in favor of the PCIe root
port node.  At runtime, pcie-qcom.c does not parse wake-gpios, and
pci_configure_of_wake_gpio() in drivers/pci/of.c only looks up wake-gpios
on the OF node attached to a struct pci_dev (such as &pcie_port0), so
PCIe WAKE# is never configured when the property is on &pcie.

> +
> +	status = "okay";
> +};

[Severity: Medium]
When this overlay enables &pcie, does legacy PCI INTx parsing fail due to
the 5-cell interrupt-map entries inherited from shikra.dtsi?

In shikra.dtsi, &intc declares #interrupt-cells = <4> and
#address-cells = <2>, so of_irq_parse_imap_parent() consumes 6 cells after
&intc in each interrupt-map entry.  However, the pcie node in shikra.dtsi
(added in commit "arm64: dts: qcom: shikra: add PCIe PHY and controller
nodes") only provides 5 cells after &intc:

arch/arm64/boot/dts/qcom/shikra.dtsi:
			interrupt-map = <0 0 0 1 &intc 0 0 0 499 IRQ_TYPE_LEVEL_HIGH>,
					<0 0 0 2 &intc 0 0 0 500 IRQ_TYPE_LEVEL_HIGH>,
					<0 0 0 3 &intc 0 0 0 501 IRQ_TYPE_LEVEL_HIGH>,
					<0 0 0 4 &intc 0 0 0 502 IRQ_TYPE_LEVEL_HIGH>;

Because the trailing 4th GICv3 cell (0) is missing from each entry,
of_irq_parse_imap_parent() consumes the first cell of the next entry as
the 4th interrupt cell and misaligns all subsequent entries, causing
INTB, INTC and INTD resolution to fail with -EINVAL.

> +
> +&pcie_phy {
> +	vdda-phy-supply = <&pm8150_l12>;
> +	vdda-pll-supply = <&pm8150_l9>;
> +
> +	status = "okay";
> +};

[Severity: Low]
Are vdda-phy-supply and vdda-pll-supply swapped here?

In shikra-iqs-som.dtsi, pm8150_l9 is the 0.88 V rail (875000..1000000 uV)
and pm8150_l12 is the 1.8 V rail (1650000..1950000 uV).  On QMP PHYs (such
as &usb_qmpphy in shikra-iqs-evk.dts and &pcie_phy in qcs615-ride.dts and
talos-evk-som.dtsi), vdda-phy-supply takes the ~0.88 V rail (&pm8150_l9)
and vdda-pll-supply takes the 1.8 V rail (&pm8150_l12).

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261112083355.3884737-1-linghui.wu@oss.qualcomm.com?part=4

Re: [PATCH v5 1/4] dt-bindings: PCI: qcom: document the Shikra PCIe controller

[Rob Herring]

On Thu, Nov 12, 2026 at 04:33:52PM +0800, Linghui Wu wrote:
> From: Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com>
> 
> Add a dedicated schema for the PCIe controller found on Shikra.
> 
> Signed-off-by: Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com>
> ---
>  .../devicetree/bindings/arm/qcom-soc.yaml     |   1 +
>  .../bindings/pci/qcom,pcie-shikra.yaml        | 192 ++++++++++++++++++
>  2 files changed, 193 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/pci/qcom,pcie-shikra.yaml
> 
> diff --git a/Documentation/devicetree/bindings/arm/qcom-soc.yaml b/Documentation/devicetree/bindings/arm/qcom-soc.yaml
> index 179aadc86a9f..72e0f1a824c6 100644
> --- a/Documentation/devicetree/bindings/arm/qcom-soc.yaml
> +++ b/Documentation/devicetree/bindings/arm/qcom-soc.yaml
> @@ -43,6 +43,7 @@ properties:
>          - pattern: "^qcom,sar[0-9]+[a-z]?-.*$"
>          - pattern: "^qcom,(sa|sc)8[0-9]+[a-z][a-z]?-.*$"
>          - pattern: "^qcom,(eliza|kaanapali|kuno|glymur|hawi|mahua|maili|milos|nord|shikra)-.+$"
> +        - const: qcom,pcie-shikra

Pretty sure we don't want this. Surely this was pointed out before v5.

>  
>          # Legacy namings - variations of existing patterns/compatibles are OK,
>          # but do not add completely new entries to these: