[PATCH 0/2] arm64: dts: allwinner: h6: Enable Ethernet on Tanix TX6

[PATCH 0/2] arm64: dts: allwinner: h6: Enable Ethernet on Tanix TX6

[Jernej Skrabec]

The AC200 MFD and Ethernet PHY drivers and their bindings were merged
in v7.4-rc1. This series adds the device tree parts needed to use them
on H6, starting with the Tanix TX6 and TX6 mini TV boxes, whose only
Ethernet port goes through the PHY in the AC200 co-packaged with the
H6.

Patch 1 describes the AC200 in the H6 dtsi: the I2C3 controller with
the AC200 on it, a pwm-clock that provides its 24 MHz reference clock
from PWM1, the RMII pins and the EPHY calibration value in the SID.
Everything stays disabled.

Patch 2 enables Ethernet on the Tanix boards.

Tested on a Tanix TX6: 100 Mbit/s full duplex, about 11 MB/s in each
direction, and the link comes up both after cold boots with no
Ethernet initialisation in U-Boot and after U-Boot has used it. The
TX6 mini shares the same dtsi and was not tested separately.

The arm64 defconfig does not enable CONFIG_MFD_AC200 and
CONFIG_XPOWERS_ACX00_PHY yet; I can send a separate patch for that.

Best regards,
Jernej

Jernej Skrabec (2):
  arm64: dts: allwinner: sun50i-h6: Add AC200 companion chip
  arm64: dts: allwinner: tanix: Enable Ethernet

 .../boot/dts/allwinner/sun50i-h6-tanix.dtsi   | 40 ++++++++++++++
 arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi  | 53 +++++++++++++++++++
 2 files changed, 93 insertions(+)

-- 
2.43.0

[PATCH 1/2] arm64: dts: allwinner: sun50i-h6: Add AC200 companion chip

[Jernej Skrabec]

Every H6 package contains an X-Powers AC200 die next to the SoC. It is
controlled over I2C3 (PB17/PB18), takes its 24 MHz reference clock from
PWM1 (PB19), and its Fast Ethernet PHY connects to the EMAC through the
RMII pins on port A.

Describe these parts in the SoC dtsi:
- the I2C3 controller with the AC200 at address 0x10 as its child,
- a pwm-clock that runs PWM1 in bypass mode at 24 MHz as the AC200
  input clock,
- the I2C3, PWM1 and RMII pin groups,
- the EPHY calibration value in the SID.

Everything stays disabled. Boards that use the AC200 enable the
pwm-clock, the PWM and I2C3 controllers and describe the PHY package on
their MDIO bus.

Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
---
 arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 53 ++++++++++++++++++++
 1 file changed, 53 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index 48c771223af4..5e48b35d13de 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -17,6 +17,16 @@ / {
 	#address-cells = <1>;
 	#size-cells = <1>;
 
+	ac200_clk: ac200-clk {
+		compatible = "pwm-clock";
+		#clock-cells = <0>;
+		clock-frequency = <24000000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pwm1_pin>;
+		pwms = <&pwm 1 42 0>;
+		status = "disabled";
+	};
+
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -314,6 +324,10 @@ ths_calibration: thermal-sensor-calibration@14 {
 			cpu_speed_grade: cpu-speed-grade@1c {
 				reg = <0x1c 0x4>;
 			};
+
+			ephy_calibration: ephy-calibration@2c {
+				reg = <0x2c 0x1>;
+			};
 		};
 
 		timer@3009000 {
@@ -388,6 +402,11 @@ i2c2_pins: i2c2-pins {
 				function = "i2c2";
 			};
 
+			i2c3_pins: i2c3-pins {
+				pins = "PB17", "PB18";
+				function = "i2c3";
+			};
+
 			mmc0_pins: mmc0-pins {
 				pins = "PF0", "PF1", "PF2", "PF3",
 				       "PF4", "PF5";
@@ -414,6 +433,19 @@ mmc2_pins: mmc2-pins {
 				bias-pull-up;
 			};
 
+			pwm1_pin: pwm1-pin {
+				pins = "PB19";
+				function = "pwm1";
+			};
+
+			/omit-if-no-ref/
+			rmii_pins: rmii-pins {
+				pins = "PA0", "PA1", "PA2", "PA3", "PA4",
+				       "PA5", "PA6", "PA7", "PA8", "PA9";
+				function = "emac";
+				drive-strength = <40>;
+			};
+
 			/omit-if-no-ref/
 			spi0_pins: spi0-pins {
 				pins = "PC0", "PC2", "PC3";
@@ -626,6 +658,27 @@ i2c2: i2c@5002800 {
 			#size-cells = <0>;
 		};
 
+		i2c3: i2c@5002c00 {
+			compatible = "allwinner,sun50i-h6-i2c",
+				     "allwinner,sun6i-a31-i2c";
+			reg = <0x05002c00 0x400>;
+			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_I2C3>;
+			resets = <&ccu RST_BUS_I2C3>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&i2c3_pins>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			/* AC200 is co-packaged with the H6 die. */
+			ac200: mixed-signal@10 {
+				compatible = "x-powers,ac200";
+				reg = <0x10>;
+				clocks = <&ac200_clk>;
+			};
+		};
+
 		spi0: spi@5010000 {
 			compatible = "allwinner,sun50i-h6-spi",
 				     "allwinner,sun8i-h3-spi";
-- 
2.43.0

[PATCH 2/2] arm64: dts: allwinner: tanix: Enable Ethernet

[Jernej Skrabec]

The Tanix TX6 and TX6 mini have a 100 Mbit Ethernet port connected to
the PHY in the AC200 companion chip that is co-packaged with the H6.

Enable the PWM controller and the pwm-clock it drives as the AC200
reference clock, enable the I2C bus to the AC200, and describe the
AC200 Ethernet PHY package on the EMAC MDIO bus, so that the EMAC can
use it over RMII.

Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
---
 .../boot/dts/allwinner/sun50i-h6-tanix.dtsi   | 40 +++++++++++++++++++
 1 file changed, 40 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix.dtsi
index f08077175549..d101001b6f70 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix.dtsi
@@ -11,6 +11,7 @@
 
 / {
 	aliases {
+		ethernet0 = &emac;
 		serial0 = &uart0;
 	};
 
@@ -85,6 +86,10 @@ wifi_pwrseq: wifi-pwrseq {
 	};
 };
 
+&ac200_clk {
+	status = "okay";
+};
+
 &cpu0 {
 	cpu-supply = <&reg_vdd_cpu_gpu>;
 };
@@ -105,6 +110,14 @@ &ehci3 {
 	status = "okay";
 };
 
+&emac {
+	pinctrl-names = "default";
+	pinctrl-0 = <&rmii_pins>;
+	phy-mode = "rmii";
+	phy-handle = <&ac200_ephy>;
+	status = "okay";
+};
+
 &gpu {
 	mali-supply = <&reg_vdd_cpu_gpu>;
 	status = "okay";
@@ -120,6 +133,29 @@ hdmi_out_con: endpoint {
 	};
 };
 
+&i2c3 {
+	status = "okay";
+};
+
+&mdio {
+	ethernet-phy-package@1 {
+		compatible = "x-powers,ac200-ephy-package";
+		reg = <1>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		vcc-supply = <&reg_vcc3v3>;
+		nvmem-cells = <&ephy_calibration>;
+		nvmem-cell-names = "configuration";
+		x-powers,ac200 = <&ac200>;
+		x-powers,xmii-rx-clock-inverted;
+
+		ac200_ephy: ethernet-phy@1 {
+			compatible = "ethernet-phy-id0044.1400";
+			reg = <1>;
+		};
+	};
+};
+
 &mmc0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&mmc0_pins>;
@@ -163,6 +199,10 @@ &pio {
 	vcc-pg-supply = <&reg_vcc1v8>;
 };
 
+&pwm {
+	status = "okay";
+};
+
 &r_ir {
 	status = "okay";
 };
-- 
2.43.0