[PATCH v3] powerpc/dts: Add Device Tree for WatchGuard Firebox T30

[PATCH v3] powerpc/dts: Add Device Tree for WatchGuard Firebox T30

[Lefteris Koutrakis]

Add initial support for the WatchGuard Firebox T30 board based on the
PowerPC architecture, updating the fsl Makefile and adding the new DTS file.
---
 arch/powerpc/boot/dts/fsl/Makefile        |   2 +
 arch/powerpc/boot/dts/fsl/firebox-t30.dts | 398 ++++++++++++++++++++++
 2 files changed, 400 insertions(+)
 create mode 100644 arch/powerpc/boot/dts/fsl/firebox-t30.dts

diff --git a/arch/powerpc/boot/dts/fsl/Makefile b/arch/powerpc/boot/dts/fsl/Makefile
index d2cc8e1f0..0a5c8b596 100644
--- a/arch/powerpc/boot/dts/fsl/Makefile
+++ b/arch/powerpc/boot/dts/fsl/Makefile
@@ -3,6 +3,7 @@
 dtb-$(CONFIG_OF_ALL_DTBS) := $(patsubst $(src)/%.dts,%.dtb, $(wildcard $(src)/*.dts))
 
 # MPC85xx platforms
+dtb-$(CONFIG_MPC85xx_RDB) += firebox-t30.dtb
 dtb-$(CONFIG_BSC9131_RDB) += bsc9131rdb.dtb
 dtb-$(CONFIG_BSC9132_QDS) += bsc9132qds.dtb
 dtb-$(CONFIG_C293_PCIE) += c293pcie.dtb
@@ -44,3 +45,4 @@ dtb-$(CONFIG_GEF_SBC310) += gef_sbc310.dtb
 dtb-$(CONFIG_GEF_SBC610) += gef_sbc610.dtb
 dtb-$(CONFIG_GEF_PPC9A) += gef_ppc9a.dtb
 dtb-$(CONFIG_MVME7100) += mvme7100.dtb
+dtb-$(CONFIG_MPC85xx_RDB) += firebox-t30.dtb
diff --git a/arch/powerpc/boot/dts/fsl/firebox-t30.dts b/arch/powerpc/boot/dts/fsl/firebox-t30.dts
new file mode 100644
index 000000000..6e9ec7f90
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/firebox-t30.dts
@@ -0,0 +1,398 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+
+/include/ "p1020si-pre.dtsi"
+
+/ {
+	model = "Watchguard Firebox T30";
+	compatible = "watchguard,firebox-t30", "fsl,P1020RDB";
+
+	memory {
+		device_type = "memory";
+	};
+
+	cpus {
+		/delete-node/ PowerPC,P1020@1;
+	};
+
+	lbc: localbus@ffe05000 {
+		reg = <0 0xffe05000 0 0x1000>;
+		ranges = <0x0 0x0 0x0 0xefc00000 0x400000>;
+
+		nor@0 {
+			compatible = "cfi-flash";
+			reg = <0x0 0x0 0x400000>;
+			bank-width = <2>;
+			device-width = <1>;
+
+			partitions {
+				compatible = "fixed-partitions";
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				partition@0 {
+					reg = <0x0 0x20000>;
+					label = "nor-cfg0";
+
+					nvmem-layout {
+						compatible = "fixed-layout";
+						#address-cells = <1>;
+						#size-cells = <1>;
+
+						macaddr_nor_cfg0_1830: mac-address@1830 {
+							compatible = "mac-base";
+							reg = <0x1830 0x11>;
+							#nvmem-cell-cells = <1>;
+						};
+
+						macaddr_nor_cfg0_1844: mac-address@1844 {
+							compatible = "mac-base";
+							reg = <0x1844 0x11>;
+							#nvmem-cell-cells = <1>;
+						};
+
+						macaddr_nor_cfg0_1858: mac-address@1858 {
+							compatible = "mac-base";
+							reg = <0x1858 0x11>;
+							#nvmem-cell-cells = <1>;
+						};
+
+						macaddr_nor_cfg0_186c: mac-address@186c {
+							compatible = "mac-base";
+							reg = <0x186c 0x11>;
+							#nvmem-cell-cells = <1>;
+						};
+
+						macaddr_nor_cfg0_1880: mac-address@1880 {
+							compatible = "mac-base";
+							reg = <0x1880 0x11>;
+							#nvmem-cell-cells = <1>;
+						};
+
+						macaddr_nor_cfg0_1894: mac-address@1894 {
+							compatible = "mac-base";
+							reg = <0x1894 0x11>;
+							#nvmem-cell-cells = <1>;
+						};
+					};
+				};
+
+				partition@20000 {
+					reg = <0x20000 0x10000>;
+					label = "nor-cfg1";
+				};
+
+				partition@30000 {
+					reg = <0x30000 0x20000>;
+					label = "nor-mfg";
+				};
+
+				partition@50000 {
+					reg = <0x50000 0xc0000>;
+					label = "nor-bootopt";
+				};
+
+				partition@110000 {
+					reg = <0x110000 0xc0000>;
+					label = "nor-extra1";
+				};
+
+				partition@1d0000 {
+					reg = <0x1d0000 0xc0000>;
+					label = "nor-extra2";
+				};
+
+				partition@290000 {
+					reg = <0x290000 0xe0000>;
+					label = "nor-backup";
+				};
+
+				partition@370000 {
+					reg = <0x370000 0x10000>;
+					label = "nor-ubootenv";
+				};
+
+				partition@380000 {
+					reg = <0x380000 0x80000>;
+					label = "nor-uboot";
+				};
+			};
+		};
+	};
+
+	soc: soc@ffe00000 {
+		ranges = <0x0 0x0 0xffe00000 0x100000>;
+
+		i2c@3000 {
+			rtc@30 {
+				compatible = "sii,s35390a";
+				reg = <0x30>;
+			};
+		};
+
+		i2c@3100 {
+			tpm@29 {
+				compatible = "tpm,tpm_i2c_atmel";
+				reg = <0x29>;
+			};
+		};
+
+		sdhc@2e000 {
+			compatible = "fsl,p1020-esdhc", "fsl,esdhc";
+			sdhci,auto-cmd12;
+			reg = <0x2e000 0x1000>;
+			interrupts = <0x48 0x2 0x0 0x0>;
+			interrupt-parent = <&mpic>;
+			clock-frequency = <0>;
+		};
+
+		spi0: spi@7000 {
+			compatible = "fsl,mpc8536-espi";
+			reg = <0x7000 0x1000>;
+			interrupts = <0x3b 0x2>;
+			interrupt-parent = <&mpic>;
+			fsl,espi-num-chipselects = <4>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			flash@0 {
+				compatible = "everspin,mr25h256", "jedec,spi-nor";
+				reg = <0>;
+				spi-max-frequency = <40000000>;
+				m25p,fast-read;
+
+				partitions {
+					compatible = "fixed-partitions";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					partition@0 {
+						reg = <0x0 0x8000>;
+						label = "spi_mtd_0";
+					};
+				};
+			};
+
+			slic@1 {
+				compatible = "zarlink,le88266";
+				reg = <1>;
+				spi-max-frequency = <500000>;
+			};
+		};
+
+		usb@22000 {
+			phy_type = "ulpi";
+			dr_mode = "host";
+		};
+
+		mdio@24000 {
+			switch0: switch@10 {
+				compatible = "marvell,mv88e6085";
+				reg = <0x10>;
+
+				mdio {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					switch0phy0: ethernet-phy@0 {
+						reg = <0>;
+					};
+
+					switch0phy1: ethernet-phy@1 {
+						reg = <1>;
+					};
+
+					switch0phy2: ethernet-phy@2 {
+						reg = <2>;
+					};
+
+					switch0phy3: ethernet-phy@3 {
+						reg = <3>;
+					};
+
+					switch0phy4: ethernet-phy@4 {
+						reg = <4>;
+					};
+				};
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						reg = <0>;
+						label = "wan";
+						phy-handle = <&switch0phy0>;
+						nvmem-cells = <&macaddr_nor_cfg0_1830 0>;
+						nvmem-cell-names = "mac-address";
+					};
+
+					port@1 {
+						reg = <1>;
+						label = "lan1";
+						phy-handle = <&switch0phy1>;
+						nvmem-cells = <&macaddr_nor_cfg0_1844 0>;
+						nvmem-cell-names = "mac-address";
+					};
+
+					port@2 {
+						reg = <2>;
+						label = "lan2";
+						phy-handle = <&switch0phy2>;
+						nvmem-cells = <&macaddr_nor_cfg0_1858 0>;
+						nvmem-cell-names = "mac-address";
+					};
+
+					port@3 {
+						reg = <3>;
+						label = "lan3";
+						phy-handle = <&switch0phy3>;
+						nvmem-cells = <&macaddr_nor_cfg0_186c 0>;
+						nvmem-cell-names = "mac-address";
+					};
+
+					port@4 {
+						reg = <4>;
+						label = "lan4";
+						phy-handle = <&switch0phy4>;
+						nvmem-cells = <&macaddr_nor_cfg0_1880 0>;
+						nvmem-cell-names = "mac-address";
+					};
+
+					port@6 {
+						reg = <6>;
+						label = "cpu";
+						ethernet = <&enet0>;
+						phy-mode = "rgmii-id";
+
+						fixed-link {
+							speed = <1000>;
+							full-duplex;
+						};
+					};
+				};
+			};
+		};
+
+		mdio@25000 {
+			status = "disabled";
+		};
+
+		mdio@26000 {
+			status = "disabled";
+		};
+
+		enet0: ethernet@b0000 {
+			phy-connection-type = "rgmii-id";
+			rx-internal-delay-ps = <2000>;
+			tx-internal-delay-ps = <2000>;
+			nvmem-cells = <&macaddr_nor_cfg0_1830 0>;
+			nvmem-cell-names = "mac-address";
+
+			fixed-link {
+				speed = <1000>;
+				full-duplex;
+			};
+		};
+
+		enet1: ethernet@b1000 {
+			status = "disabled";
+		};
+
+		enet2: ethernet@b2000 {
+			status = "disabled";
+		};
+
+		gpio0: gpio-controller@fc00 {
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led0: led-0 {
+			gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_ORANGE>;
+			function = LED_FUNCTION_STATUS;
+		};
+
+		led1: led-1 {
+			gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_RED>;
+			function = LED_FUNCTION_STATUS;
+		};
+
+		led2: led-2 {
+			gpios = <&gpio0 4 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_USB;
+		};
+
+		led3: led-3 {
+			gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>;
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_WLAN_5GHZ;
+			default-state = "keep";
+		};
+
+		led4: led-4 {
+			gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
+			color = <LED_COLOR_ID_ORANGE>;
+			function = LED_FUNCTION_WLAN_2GHZ;
+			default-state = "keep";
+		};
+
+		led5: led-5 {
+			gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_POWER;
+			default-state = "on";
+		};
+	};
+
+	pci0: pcie@ffe09000 {
+		reg = <0 0xffe09000 0 0x1000>;
+		ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
+			  0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
+		status = "disabled";
+
+		pcie@0 {
+			ranges = <0x2000000 0x0 0xa0000000
+				  0x2000000 0x0 0xa0000000
+				  0x0 0x20000000
+
+				  0x1000000 0x0 0x0
+				  0x1000000 0x0 0x0
+				  0x0 0x100000>;
+		};
+	};
+
+	pci1: pcie@ffe0a000 {
+		reg = <0 0xffe0a000 0 0x1000>;
+		ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
+			  0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
+
+		pcie@0 {
+			ranges = <0x2000000 0x0 0x80000000
+				  0x2000000 0x0 0x80000000
+				  0x0 0x20000000
+
+				  0x1000000 0x0 0x0
+				  0x1000000 0x0 0x0
+				  0x0 0x100000>;
+
+			ath10k: wifi@0,0 {
+				reg = <0x0000 0 0 0 0>;
+				#gpio-cells = <2>;
+				gpio-controller;
+				nvmem-cells = <&macaddr_nor_cfg0_1894 0>;
+				nvmem-cell-names = "mac-address";
+			};
+		};
+	};
+};
+
+/include/ "p1020si-post.dtsi"
-- 
2.53.0

Re: [PATCH v3] powerpc/dts: Add Device Tree for WatchGuard Firebox T30

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 4 potential issue(s) to consider:
- [Medium] powerpc/dts: invalid compatible string in firebox-t30 tpm@29 node
- [Low] powerpc/dts: duplicate firebox-t30.dtb entry in fsl/Makefile
- [Low] powerpc/dts: malformed spi@7000 interrupts and redundant SoC properties
- [Low] powerpc/dts: firebox-t30: undocumented compatible and unsupported DT properties
--

commit 68d1b53d33f85dd0ec26113a393584818efd23a1
Author: Lefteris Koutrakis <lefteris.koutrakis@gmail.com>

powerpc/dts: Add Device Tree for WatchGuard Firebox T30

This commit adds a new Device Tree source file for the WatchGuard Firebox T30
board based on the Freescale P1020 SoC and hooks it into the Freescale PowerPC
DTS Makefile.

> diff --git a/arch/powerpc/boot/dts/fsl/Makefile b/arch/powerpc/boot/dts/fsl/Makefile
> index d2cc8e1f007ea..0a5c8b5967335 100644
> --- a/arch/powerpc/boot/dts/fsl/Makefile
> +++ b/arch/powerpc/boot/dts/fsl/Makefile
> @@ -3,6 +3,7 @@
>  dtb-$(CONFIG_OF_ALL_DTBS) := $(patsubst $(src)/%.dts,%.dtb, $(wildcard $(src)/*.dts))
>  
>  # MPC85xx platforms
> +dtb-$(CONFIG_MPC85xx_RDB) += firebox-t30.dtb
>  dtb-$(CONFIG_BSC9131_RDB) += bsc9131rdb.dtb
>  dtb-$(CONFIG_BSC9132_QDS) += bsc9132qds.dtb
>  dtb-$(CONFIG_C293_PCIE) += c293pcie.dtb
> @@ -44,3 +45,4 @@ dtb-$(CONFIG_GEF_SBC310) += gef_sbc310.dtb
>  dtb-$(CONFIG_GEF_SBC610) += gef_sbc610.dtb
>  dtb-$(CONFIG_GEF_PPC9A) += gef_ppc9a.dtb
>  dtb-$(CONFIG_MVME7100) += mvme7100.dtb
> +dtb-$(CONFIG_MPC85xx_RDB) += firebox-t30.dtb

[Severity: Low]
Is this second addition of firebox-t30.dtb to dtb-$(CONFIG_MPC85xx_RDB) at
the bottom of arch/powerpc/boot/dts/fsl/Makefile (under the MPC86xx platforms
section) unintended?

Since firebox-t30.dtb is already appended to dtb-$(CONFIG_MPC85xx_RDB) at the
start of the MPC85xx platforms section, building with CONFIG_MPC85xx_RDB=y
causes firebox-t30.dtb to be listed twice in $(dtb-y) and $(obj)/dtbs-list via
scripts/Makefile.dtbs.

> diff --git a/arch/powerpc/boot/dts/fsl/firebox-t30.dts b/arch/powerpc/boot/dts/fsl/firebox-t30.dts
> new file mode 100644
> index 0000000000000..6e9ec7f90ece2
> --- /dev/null
> +++ b/arch/powerpc/boot/dts/fsl/firebox-t30.dts
> @@ -0,0 +1,398 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/input/input.h>
> +#include <dt-bindings/leds/common.h>
> +
> +/include/ "p1020si-pre.dtsi"
> +
> +/ {
> +	model = "Watchguard Firebox T30";
> +	compatible = "watchguard,firebox-t30", "fsl,P1020RDB";

[ ... ]

> +	soc: soc@ffe00000 {
> +		ranges = <0x0 0x0 0xffe00000 0x100000>;
> +
> +		i2c@3000 {
> +			rtc@30 {
> +				compatible = "sii,s35390a";
> +				reg = <0x30>;
> +			};
> +		};
> +
> +		i2c@3100 {
> +			tpm@29 {
> +				compatible = "tpm,tpm_i2c_atmel";
> +				reg = <0x29>;
> +			};
> +		};

[Severity: Medium]
Should the compatible property for tpm@29 under i2c@3100 be
"atmel,at97sc3204t" instead of "tpm,tpm_i2c_atmel"?

In drivers/char/tpm/tpm_i2c_atmel.c, the OF match table only matches
"atmel,at97sc3204t":

    static const struct of_device_id i2c_atmel_of_match[] = {
        {.compatible = "atmel,at97sc3204t"},
        {},
    };
    MODULE_DEVICE_TABLE(of, i2c_atmel_of_match);

When an I2C device is instantiated from Device Tree, i2c_device_uevent() in
drivers/i2c/i2c-core-base.c emits only the OF modalias and returns before
emitting the legacy i2c: modalias:

    rc = of_device_uevent_modalias(dev, env);
    if (rc != -ENODEV)
        return rc;

With compatible = "tpm,tpm_i2c_atmel", the kernel emits
MODALIAS=of:NtpmT(null)Ctpm,tpm_i2c_atmel, which prevents automatic module
loading when CONFIG_TCG_TIS_I2C_ATMEL=m and fails DT schema validation against
Documentation/devicetree/bindings/tpm/tcg,tpm-tis-i2c.yaml.

> +
> +		sdhc@2e000 {
> +			compatible = "fsl,p1020-esdhc", "fsl,esdhc";
> +			sdhci,auto-cmd12;
> +			reg = <0x2e000 0x1000>;
> +			interrupts = <0x48 0x2 0x0 0x0>;
> +			interrupt-parent = <&mpic>;
> +			clock-frequency = <0>;
> +		};
> +
> +		spi0: spi@7000 {
> +			compatible = "fsl,mpc8536-espi";
> +			reg = <0x7000 0x1000>;
> +			interrupts = <0x3b 0x2>;
> +			interrupt-parent = <&mpic>;
> +			fsl,espi-num-chipselects = <4>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;

[Severity: Low]
Can the SoC-level properties in sdhc@2e000 and spi0: spi@7000 be dropped here
so they are inherited from p1020si-post.dtsi?

In spi0: spi@7000, interrupts = <0x3b 0x2> only provides 2 cells for &mpic,
whereas mpic: pic@40000 in pq3-mpic.dtsi requires #interrupt-cells = <4>.
Because p1020si-post.dtsi (which includes pq3-espi-0.dtsi and pq3-esdhc-0.dtsi)
is included at the bottom of firebox-t30.dts, dtc overwrites this 2-cell
specifier with the 4-cell interrupts = <59 0x2 0 0> definition from
pq3-espi-0.dtsi.

Furthermore, sdhc@2e000 only repeats properties already defined in
p1020si-post.dtsi and pq3-esdhc-0.dtsi without adding any board-specific
configuration, and spi@7000 only needs to define its flash@0 and slic@1 child
nodes.

[ ... ]

> +		enet0: ethernet@b0000 {
> +			phy-connection-type = "rgmii-id";
> +			rx-internal-delay-ps = <2000>;
> +			tx-internal-delay-ps = <2000>;
> +			nvmem-cells = <&macaddr_nor_cfg0_1830 0>;
> +			nvmem-cell-names = "mac-address";
> +
> +			fixed-link {
> +				speed = <1000>;
> +				full-duplex;
> +			};
> +		};

[ ... ]

> +			ath10k: wifi@0,0 {
> +				reg = <0x0000 0 0 0 0>;
> +				#gpio-cells = <2>;
> +				gpio-controller;
> +				nvmem-cells = <&macaddr_nor_cfg0_1894 0>;
> +				nvmem-cell-names = "mac-address";
> +			};

[Severity: Low]
Are the following bindings and properties in firebox-t30.dts intentional?

1. The root node uses compatible = "watchguard,firebox-t30", "fsl,P1020RDB",
   where neither the "watchguard" vendor prefix (in
   Documentation/devicetree/bindings/vendor-prefixes.yaml) nor the
   "watchguard,firebox-t30" board compatible string is documented.

2. enet0: ethernet@b0000 (an fsl,etsec2 device from pq3-etsec2-0.dtsi) sets
   rx-internal-delay-ps = <2000> and tx-internal-delay-ps = <2000>, which the
   gianfar driver in drivers/net/ethernet/freescale/gianfar.c does not parse
   or support.

3. ath10k: wifi@0,0 declares gpio-controller and #gpio-cells = <2>, which are
   not supported by the ath10k driver or its binding in
   Documentation/devicetree/bindings/net/wireless/qcom,ath10k.yaml, and are
   not referenced elsewhere in this DTS.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261028143421.145290-1-lefteris.koutrakis@gmail.com?part=1

Re: [PATCH v3] powerpc/dts: Add Device Tree for WatchGuard Firebox T30

[Krzysztof Kozlowski]

On 28/10/2026 15:34, Lefteris Koutrakis wrote:
> Add initial support for the WatchGuard Firebox T30 board based on the
> PowerPC architecture, updating the fsl Makefile and adding the new DTS file.

Please wrap commit message according to Linux coding style / submission
process (neither too early nor over the limit):
https://elixir.bootlin.com/linux/v6.4-rc1/source/Documentation/process/submitting-patches.rst#L597

Missing DCO. Please read carefully submitting patches.


> ---
>  arch/powerpc/boot/dts/fsl/Makefile        |   2 +
>  arch/powerpc/boot/dts/fsl/firebox-t30.dts | 398 ++++++++++++++++++++++
>  2 files changed, 400 insertions(+)
>  create mode 100644 arch/powerpc/boot/dts/fsl/firebox-t30.dts
> 
> diff --git a/arch/powerpc/boot/dts/fsl/Makefile b/arch/powerpc/boot/dts/fsl/Makefile
> index d2cc8e1f0..0a5c8b596 100644
> --- a/arch/powerpc/boot/dts/fsl/Makefile
> +++ b/arch/powerpc/boot/dts/fsl/Makefile
> @@ -3,6 +3,7 @@
>  dtb-$(CONFIG_OF_ALL_DTBS) := $(patsubst $(src)/%.dts,%.dtb, $(wildcard $(src)/*.dts))
>  
>  # MPC85xx platforms
> +dtb-$(CONFIG_MPC85xx_RDB) += firebox-t30.dtb
>  dtb-$(CONFIG_BSC9131_RDB) += bsc9131rdb.dtb
>  dtb-$(CONFIG_BSC9132_QDS) += bsc9132qds.dtb
>  dtb-$(CONFIG_C293_PCIE) += c293pcie.dtb
> @@ -44,3 +45,4 @@ dtb-$(CONFIG_GEF_SBC310) += gef_sbc310.dtb
>  dtb-$(CONFIG_GEF_SBC610) += gef_sbc610.dtb
>  dtb-$(CONFIG_GEF_PPC9A) += gef_ppc9a.dtb
>  dtb-$(CONFIG_MVME7100) += mvme7100.dtb
> +dtb-$(CONFIG_MPC85xx_RDB) += firebox-t30.dtb
> diff --git a/arch/powerpc/boot/dts/fsl/firebox-t30.dts b/arch/powerpc/boot/dts/fsl/firebox-t30.dts
> new file mode 100644
> index 000000000..6e9ec7f90
> --- /dev/null
> +++ b/arch/powerpc/boot/dts/fsl/firebox-t30.dts
> @@ -0,0 +1,398 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/input/input.h>
> +#include <dt-bindings/leds/common.h>
> +
> +/include/ "p1020si-pre.dtsi"
> +
> +/ {
> +	model = "Watchguard Firebox T30";
> +	compatible = "watchguard,firebox-t30", "fsl,P1020RDB";

Missing bindings, but not sure if it matters for PowerPC at all.

Best regards,
Krzysztof