Re: [PATCH v6 v6 4/9] ASoC: qcom: lpass-va-macro: Add shikra compatible

[Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com>]

On 11/11/2026 6:50 AM, Mark Brown wrote:
>> Add shikra specific VA macro data and register programming needed by
>> the LPASS codec v4.1 implementation.
> 
>> +/* LPASS codec v4.1 adaptive filter (ADPT) blocks */
>> +#define CDC_VA_CDC_ADPT0_ADPT_CTRL		0x0800
>> +#define CDC_VA_ADPT_CTRL_EN_MASK		GENMASK(7, 0)
> 
> Is the enable mask really 8 bits wide?
> 

Good catch Mark, it's actually 6 bits. will current in next version.


>> +static const struct reg_default va_4_1_defaults[] = {
>> +	/* VA macro */
>> +	{ CDC_VA_CLK_RST_CTRL_MCLK_CONTROL, 0x00},
>> +	{ CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL, 0x00},
>> +	{ CDC_VA_CLK_RST_CTRL_SWR_CONTROL, 0x00},
>> +	{ CDC_VA_TOP_CSR_TOP_CFG0, 0x00},
>> +	{ CDC_VA_TOP_CSR_DMIC0_CTL, 0x00},
>> +	{ CDC_VA_TOP_CSR_DMIC1_CTL, 0x00},
>> +	{ CDC_VA_TOP_CSR_DMIC2_CTL, 0x00},
>> +	{ CDC_VA_TOP_CSR_DMIC3_CTL, 0x00},
>> +	{ CDC_VA_TOP_CSR_DMIC_CFG, 0x80},
>> +	{ CDC_VA_TOP_CSR_DEBUG_BUS, 0x00},
>> +	{ CDC_VA_TOP_CSR_DEBUG_EN, 0x00},
>> +	{ CDC_VA_TOP_CSR_TX_I2S_CTL, 0x0C},
>> +	{ CDC_VA_TOP_CSR_I2S_CLK, 0x00},
>> +	{ CDC_VA_TOP_CSR_I2S_RESET, 0x00},
>> +	{ CDC_VA_TOP_CSR_CORE_ID_0, 0x00},
>> +	{ CDC_VA_TOP_CSR_CORE_ID_1, 0x00},
>> +	{ CDC_VA_TOP_CSR_CORE_ID_2, 0x00},
>> +	{ CDC_VA_TOP_CSR_CORE_ID_3, 0x00},
>> +	{ CDC_VA_TOP_CSR_SWR_MIC_CTL0, 0xEE},
>> +	{ CDC_VA_TOP_CSR_SWR_MIC_CTL1, 0xEE},
>> +	{ CDC_VA_TOP_CSR_SWR_MIC_CTL2, 0xEE},
>> +	{ CDC_VA_TOP_CSR_SWR_CTRL, 0x06},
>> +	/* VA core */
>> +	{ CDC_VA_TX0_TX_PATH_CTL, 0x04},
> 
> Are we missing defaults for the mux registers?

I missed in this version. will fix in next revision

Best Regards,
Rafi.

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