Re: [PATCH v6 07/15] ASoC: qdsp6: q6afe: add internal mi2s support

[Srinivas Kandagatla <srini@kernel.org>]

On 7/30/26 6:43 PM, Richard Acayan wrote:
> The bindings for LPI MI2S ports, originally exclusive to q6apm, can be
> used for internal MI2S ports on q6afe. Add the port mappings for
> internal MI2S, found on the Snapdragon 660 internal sound card.
> 
> Signed-off-by: Richard Acayan <mailingradian@gmail.com>
> ---
lgtm,

Reviewed-by: Srinivas Kandagatla <srinivas.kandagatla@oss.qualcomm.com>

--srini

>  sound/soc/qcom/qdsp6/q6afe.c | 56 ++++++++++++++++++++++++++++++++++++
>  1 file changed, 56 insertions(+)
> 
> diff --git a/sound/soc/qcom/qdsp6/q6afe.c b/sound/soc/qcom/qdsp6/q6afe.c
> index 40237267fda0..1d68a80e8e0c 100644
> --- a/sound/soc/qcom/qdsp6/q6afe.c
> +++ b/sound/soc/qcom/qdsp6/q6afe.c
> @@ -132,6 +132,20 @@
>  #define AFE_PORT_ID_QUINARY_MI2S_TX	    0x1017
>  #define AFE_PORT_ID_SENARY_MI2S_RX          0x1018
>  #define AFE_PORT_ID_SENARY_MI2S_TX          0x1019
> +#define AFE_PORT_ID_INT0_MI2S_RX	    0x102e
> +#define AFE_PORT_ID_INT0_MI2S_TX	    0x102f
> +#define AFE_PORT_ID_INT1_MI2S_RX	    0x1030
> +#define AFE_PORT_ID_INT1_MI2S_TX	    0x1031
> +#define AFE_PORT_ID_INT2_MI2S_RX	    0x1032
> +#define AFE_PORT_ID_INT2_MI2S_TX	    0x1033
> +#define AFE_PORT_ID_INT3_MI2S_RX	    0x1034
> +#define AFE_PORT_ID_INT3_MI2S_TX	    0x1035
> +#define AFE_PORT_ID_INT4_MI2S_RX	    0x1036
> +#define AFE_PORT_ID_INT4_MI2S_TX	    0x1037
> +#define AFE_PORT_ID_INT5_MI2S_RX	    0x1038
> +#define AFE_PORT_ID_INT5_MI2S_TX	    0x1039
> +#define AFE_PORT_ID_INT6_MI2S_RX	    0x103a
> +#define AFE_PORT_ID_INT6_MI2S_TX	    0x103b
>  
>  /* Start of the range of port IDs for TDM devices. */
>  #define AFE_PORT_ID_TDM_PORT_RANGE_START	0x9000
> @@ -931,6 +945,34 @@ static struct afe_port_map port_maps[AFE_PORT_MAX] = {
>  	[RX_CODEC_DMA_RX_7] = { AFE_PORT_ID_RX_CODEC_DMA_RX_7,
>  				RX_CODEC_DMA_RX_7, 1, 1},
>  	[USB_RX] = { AFE_PORT_ID_USB_RX, USB_RX, 1, 1},
> +	[LPI_MI2S_RX_0] = { AFE_PORT_ID_INT0_MI2S_RX,
> +				LPI_MI2S_RX_0, 1, 1},
> +	[LPI_MI2S_TX_0] = { AFE_PORT_ID_INT0_MI2S_TX,
> +				LPI_MI2S_TX_0, 0, 1},
> +	[LPI_MI2S_RX_1] = { AFE_PORT_ID_INT1_MI2S_RX,
> +				LPI_MI2S_RX_1, 1, 1},
> +	[LPI_MI2S_TX_1] = { AFE_PORT_ID_INT1_MI2S_TX,
> +				LPI_MI2S_TX_1, 0, 1},
> +	[LPI_MI2S_RX_2] = { AFE_PORT_ID_INT2_MI2S_RX,
> +				LPI_MI2S_RX_2, 1, 1},
> +	[LPI_MI2S_TX_2] = { AFE_PORT_ID_INT2_MI2S_TX,
> +				LPI_MI2S_TX_2, 0, 1},
> +	[LPI_MI2S_RX_3] = { AFE_PORT_ID_INT3_MI2S_RX,
> +				LPI_MI2S_RX_3, 1, 1},
> +	[LPI_MI2S_TX_3] = { AFE_PORT_ID_INT3_MI2S_TX,
> +				LPI_MI2S_TX_3, 0, 1},
> +	[LPI_MI2S_RX_4] = { AFE_PORT_ID_INT4_MI2S_RX,
> +				LPI_MI2S_RX_4, 1, 1},
> +	[LPI_MI2S_TX_4] = { AFE_PORT_ID_INT4_MI2S_TX,
> +				LPI_MI2S_TX_4, 0, 1},
> +	[LPI_MI2S_RX_5] = { AFE_PORT_ID_INT5_MI2S_RX,
> +				LPI_MI2S_RX_5, 1, 1},
> +	[LPI_MI2S_TX_5] = { AFE_PORT_ID_INT5_MI2S_TX,
> +				LPI_MI2S_TX_5, 0, 1},
> +	[LPI_MI2S_RX_6] = { AFE_PORT_ID_INT6_MI2S_RX,
> +				LPI_MI2S_RX_6, 1, 1},
> +	[LPI_MI2S_TX_6] = { AFE_PORT_ID_INT6_MI2S_TX,
> +				LPI_MI2S_TX_6, 0, 1},
>  };
>  
>  static void q6afe_port_free(struct kref *ref)
> @@ -1785,6 +1827,20 @@ struct q6afe_port *q6afe_port_get_from_id(struct device *dev, int id)
>  	case AFE_PORT_ID_QUINARY_MI2S_TX:
>  	case AFE_PORT_ID_SENARY_MI2S_RX:
>  	case AFE_PORT_ID_SENARY_MI2S_TX:
> +	case AFE_PORT_ID_INT0_MI2S_RX:
> +	case AFE_PORT_ID_INT0_MI2S_TX:
> +	case AFE_PORT_ID_INT1_MI2S_RX:
> +	case AFE_PORT_ID_INT1_MI2S_TX:
> +	case AFE_PORT_ID_INT2_MI2S_RX:
> +	case AFE_PORT_ID_INT2_MI2S_TX:
> +	case AFE_PORT_ID_INT3_MI2S_RX:
> +	case AFE_PORT_ID_INT3_MI2S_TX:
> +	case AFE_PORT_ID_INT4_MI2S_RX:
> +	case AFE_PORT_ID_INT4_MI2S_TX:
> +	case AFE_PORT_ID_INT5_MI2S_RX:
> +	case AFE_PORT_ID_INT5_MI2S_TX:
> +	case AFE_PORT_ID_INT6_MI2S_RX:
> +	case AFE_PORT_ID_INT6_MI2S_TX:
>  		cfg_type = AFE_PARAM_ID_I2S_CONFIG;
>  		break;
>  	case AFE_PORT_ID_PRIMARY_TDM_RX ... AFE_PORT_ID_QUINARY_TDM_TX_7: