Re: [PATCH 1/2] dt-bindings: cache: qcom,llcc: Document Eliza LLCC block

[Krzysztof Kozlowski <krzk@kernel.org>]

On 06/05/2026 10:49, Konrad Dybcio wrote:
> On 5/6/26 10:25 AM, Krzysztof Kozlowski wrote:
>> On Mon, May 04, 2026 at 01:00:07PM +0300, Abel Vesa wrote:
>>> Document the Last Level Cache Controller on Eliza SoC. Eliza LLCC has 2
>>> base register regions and an additional AND, OR broadcast region, total 4
>>> register regions.
>>>
>>> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
>>> ---
>>>  .../devicetree/bindings/cache/qcom,llcc.yaml       | 22 ++++++++++++++++++++++
>>>  1 file changed, 22 insertions(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
>>> index 995d57815781..90f5a54b76e3 100644
>>> --- a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
>>> +++ b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
>>> @@ -20,6 +20,7 @@ description: |
>>>  properties:
>>>    compatible:
>>>      enum:
>>> +      - qcom,eliza-llcc
>>>        - qcom,glymur-llcc
>>>        - qcom,ipq5424-llcc
>>>        - qcom,kaanapali-llcc
>>> @@ -341,6 +342,27 @@ allOf:
>>>              - const: llcc_broadcast_base
>>>              - const: llcc_broadcast_and_base
>>>  
>>> +  - if:
>>> +      properties:
>>> +        compatible:
>>> +          contains:
>>> +            enum:
>>> +              - qcom,eliza-llcc
>>> +    then:
>>> +      properties:
>>> +        reg:
>>> +          items:
>>> +            - description: LLCC0 base register region
>>> +            - description: LLCC2 base register region
>>
>> LLCC1?
> 
> Unfortunately not

Then let's just skip the names, because it will cause unnecessary
confusion when name is llcc1 (since it is the NEXT entry) but it points
to block called LLCC2 in the manual.


Best regards,
Krzysztof